arm64: dts: zynqmp: DT changes for v5.6
- Switch from fixed to firmware based clock driver - Wire power domain driver - Wire all ina226 chips through IIO and IIO hwmon drivers - Add missing dr_mode property to usb nodes - Use gpio-line-names property instead of comments - Use clock-output-names for si570 differentiation - Minor DT fixes -----BEGIN PGP SIGNATURE----- iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCXibMLgAKCRDKSWXLKUoM IQW6AJ9Szg4yizku9Q6oi+yrR6L3eRxnyACcDiM4EeKIvrlK19cYVnd/58ENPs8= =k6/g -----END PGP SIGNATURE----- Merge tag 'zynqmp-dt-for-v5.6' of https://github.com/Xilinx/linux-xlnx into arm/dt arm64: dts: zynqmp: DT changes for v5.6 - Switch from fixed to firmware based clock driver - Wire power domain driver - Wire all ina226 chips through IIO and IIO hwmon drivers - Add missing dr_mode property to usb nodes - Use gpio-line-names property instead of comments - Use clock-output-names for si570 differentiation - Minor DT fixes * tag 'zynqmp-dt-for-v5.6' of https://github.com/Xilinx/linux-xlnx: (21 commits) arm64: zynqmp: Add label property to all ina226 on zcu106 arm64: zynqmp: Enable iio-hwmon for ina226 on zcu106 arm64: zynqmp: Add label property to all ina226 on zcu102 arm64: zynqmp: Enable iio-hwmon for ina226 on zcu102 arm64: zynqmp: Add label property to all ina226 on zcu111 arm64: zynqmp: Enable iio-hwmon for ina226 on zcu111 arm64: zynqmp: Enable iio-hwmon for ina226 on zcu100 arm64: zynqmp: Setup default number of chipselects for zcu100 arm64: zynqmp: Remove broken-cd from zcu100-revC arm64: zynqmp: Fix the si570 clock frequency on zcu111 arm64: zynqmp: Setup clock-output-names for si570 chips arm64: zynqmp: Turn comment to gpio-line-names arm64: zynqmp: Fix address for tca6416_u97 chip on zcu104 arm64: zynqmp: Remove addition number in node name arm64: zynqmp: Use ethernet-phy as node name for ethernet phys arm64: dts: xilinx: Add the power nodes for zynqmp arm64: dts: xilinx: Remove dtsi for fixed clock arm64: dts: xilinx: Add the clock nodes for zynqmp arm64: zynqmp: Add dr_mode property to usb node arm64: dts: zynqmp: Use decimal values for drm-clock properties ... Link: https://lore.kernel.org/r/c70d2efa-9ee2-a764-5248-0e5bfbf29f8a@monstr.eu Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
498f2a4be6
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@ -0,0 +1,222 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Clock specification for Xilinx ZynqMP
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*
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||||
* (C) Copyright 2017 - 2019, Xilinx, Inc.
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*
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||||
* Michal Simek <michal.simek@xilinx.com>
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||||
*/
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#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
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/ {
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||||
pss_ref_clk: pss_ref_clk {
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||||
u-boot,dm-pre-reloc;
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <33333333>;
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};
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video_clk: video_clk {
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u-boot,dm-pre-reloc;
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <27000000>;
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};
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pss_alt_ref_clk: pss_alt_ref_clk {
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u-boot,dm-pre-reloc;
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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gt_crx_ref_clk: gt_crx_ref_clk {
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u-boot,dm-pre-reloc;
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <108000000>;
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};
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aux_ref_clk: aux_ref_clk {
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u-boot,dm-pre-reloc;
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <27000000>;
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};
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};
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|
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&can0 {
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clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&can1 {
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clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&cpu0 {
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clocks = <&zynqmp_clk ACPU>;
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};
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&fpd_dma_chan1 {
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clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&fpd_dma_chan2 {
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clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&fpd_dma_chan3 {
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clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&fpd_dma_chan4 {
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clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&fpd_dma_chan5 {
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clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&fpd_dma_chan6 {
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clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&fpd_dma_chan7 {
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clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&fpd_dma_chan8 {
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clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&lpd_dma_chan1 {
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clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&lpd_dma_chan2 {
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clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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|
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&lpd_dma_chan3 {
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clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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|
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&lpd_dma_chan4 {
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clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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|
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&lpd_dma_chan5 {
|
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clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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|
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&lpd_dma_chan6 {
|
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clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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|
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&lpd_dma_chan7 {
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clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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|
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&lpd_dma_chan8 {
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clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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|
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&gem0 {
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clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
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<&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
|
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<&zynqmp_clk GEM_TSU>;
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clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
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||||
};
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|
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&gem1 {
|
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clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
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<&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
|
||||
<&zynqmp_clk GEM_TSU>;
|
||||
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
|
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};
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||||
|
||||
&gem2 {
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clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
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<&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
|
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<&zynqmp_clk GEM_TSU>;
|
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clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
|
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};
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|
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&gem3 {
|
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clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
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<&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
|
||||
<&zynqmp_clk GEM_TSU>;
|
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clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
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};
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|
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&gpio {
|
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clocks = <&zynqmp_clk LPD_LSBUS>;
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};
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|
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&i2c0 {
|
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clocks = <&zynqmp_clk I2C0_REF>;
|
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};
|
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|
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&i2c1 {
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clocks = <&zynqmp_clk I2C1_REF>;
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};
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|
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&pcie {
|
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clocks = <&zynqmp_clk PCIE_REF>;
|
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};
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&sata {
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clocks = <&zynqmp_clk SATA_REF>;
|
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};
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|
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&sdhci0 {
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clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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|
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&sdhci1 {
|
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clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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|
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&spi0 {
|
||||
clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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|
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&spi1 {
|
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clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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|
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&ttc0 {
|
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clocks = <&zynqmp_clk LPD_LSBUS>;
|
||||
};
|
||||
|
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&ttc1 {
|
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clocks = <&zynqmp_clk LPD_LSBUS>;
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||||
};
|
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|
||||
&ttc2 {
|
||||
clocks = <&zynqmp_clk LPD_LSBUS>;
|
||||
};
|
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|
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&ttc3 {
|
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clocks = <&zynqmp_clk LPD_LSBUS>;
|
||||
};
|
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|
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&uart0 {
|
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clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
|
||||
};
|
||||
|
||||
&uart1 {
|
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clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&usb0 {
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clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
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};
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&usb1 {
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clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
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};
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&watchdog0 {
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clocks = <&zynqmp_clk WDT>;
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};
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|
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@ -1,213 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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||||
/*
|
||||
* Clock specification for Xilinx ZynqMP
|
||||
*
|
||||
* (C) Copyright 2015 - 2018, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
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/ {
|
||||
clk100: clk100 {
|
||||
compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
|
||||
};
|
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|
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clk125: clk125 {
|
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
|
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};
|
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|
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clk200: clk200 {
|
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
|
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|
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clk250: clk250 {
|
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <250000000>;
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};
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|
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clk300: clk300 {
|
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compatible = "fixed-clock";
|
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#clock-cells = <0>;
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clock-frequency = <300000000>;
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};
|
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|
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clk600: clk600 {
|
||||
compatible = "fixed-clock";
|
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#clock-cells = <0>;
|
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clock-frequency = <600000000>;
|
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};
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|
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dp_aclk: clock0 {
|
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compatible = "fixed-clock";
|
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#clock-cells = <0>;
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clock-frequency = <100000000>;
|
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clock-accuracy = <100>;
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};
|
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|
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dp_aud_clk: clock1 {
|
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compatible = "fixed-clock";
|
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#clock-cells = <0>;
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clock-frequency = <24576000>;
|
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clock-accuracy = <100>;
|
||||
};
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|
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dpdma_clk: dpdma-clk {
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compatible = "fixed-clock";
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#clock-cells = <0x0>;
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clock-frequency = <533000000>;
|
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};
|
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|
||||
drm_clock: drm-clock {
|
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compatible = "fixed-clock";
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#clock-cells = <0x0>;
|
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clock-frequency = <262750000>;
|
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clock-accuracy = <0x64>;
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};
|
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};
|
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|
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&can0 {
|
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clocks = <&clk100 &clk100>;
|
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};
|
||||
|
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&can1 {
|
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clocks = <&clk100 &clk100>;
|
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};
|
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|
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&fpd_dma_chan1 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
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|
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&fpd_dma_chan2 {
|
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clocks = <&clk600>, <&clk100>;
|
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};
|
||||
|
||||
&fpd_dma_chan3 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&fpd_dma_chan4 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
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&fpd_dma_chan5 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&fpd_dma_chan6 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&fpd_dma_chan7 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&fpd_dma_chan8 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&lpd_dma_chan1 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&lpd_dma_chan2 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&lpd_dma_chan3 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&lpd_dma_chan4 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&lpd_dma_chan5 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&lpd_dma_chan6 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&lpd_dma_chan7 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&lpd_dma_chan8 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&gem0 {
|
||||
clocks = <&clk125>, <&clk125>, <&clk125>;
|
||||
};
|
||||
|
||||
&gem1 {
|
||||
clocks = <&clk125>, <&clk125>, <&clk125>;
|
||||
};
|
||||
|
||||
&gem2 {
|
||||
clocks = <&clk125>, <&clk125>, <&clk125>;
|
||||
};
|
||||
|
||||
&gem3 {
|
||||
clocks = <&clk125>, <&clk125>, <&clk125>;
|
||||
};
|
||||
|
||||
&gpio {
|
||||
clocks = <&clk100>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clocks = <&clk100>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clocks = <&clk100>;
|
||||
};
|
||||
|
||||
&sata {
|
||||
clocks = <&clk250>;
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
clocks = <&clk200 &clk200>;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
clocks = <&clk200 &clk200>;
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
clocks = <&clk200 &clk200>;
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
clocks = <&clk200 &clk200>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
clocks = <&clk100 &clk100>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
clocks = <&clk100 &clk100>;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
clocks = <&clk250>, <&clk250>;
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
clocks = <&clk250>, <&clk250>;
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
clocks = <&clk250>;
|
||||
};
|
||||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* dts file for Xilinx ZynqMP ZC1232
|
||||
*
|
||||
* (C) Copyright 2017 - 2018, Xilinx, Inc.
|
||||
* (C) Copyright 2017 - 2019, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
|
@ -10,7 +10,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ZynqMP ZC1232 RevA";
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* dts file for Xilinx ZynqMP ZC1254
|
||||
*
|
||||
* (C) Copyright 2015 - 2018, Xilinx, Inc.
|
||||
* (C) Copyright 2015 - 2019, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
|
||||
|
|
@ -11,7 +11,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ZynqMP ZC1254 RevA";
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* dts file for Xilinx ZynqMP ZC1275
|
||||
*
|
||||
* (C) Copyright 2017 - 2018, Xilinx, Inc.
|
||||
* (C) Copyright 2017 - 2019, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
|
||||
|
|
@ -11,7 +11,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ZynqMP ZC1275 RevA";
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* dts file for Xilinx ZynqMP zc1751-xm015-dc1
|
||||
*
|
||||
* (C) Copyright 2015 - 2018, Xilinx, Inc.
|
||||
* (C) Copyright 2015 - 2019, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
|
@ -10,7 +10,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
|
|
@ -73,7 +73,7 @@
|
|||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@0 {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -128,4 +128,5 @@
|
|||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* dts file for Xilinx ZynqMP zc1751-xm016-dc2
|
||||
*
|
||||
* (C) Copyright 2015 - 2018, Xilinx, Inc.
|
||||
* (C) Copyright 2015 - 2019, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
|
@ -10,7 +10,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
|
|
@ -84,7 +84,7 @@
|
|||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@5 {
|
||||
phy0: ethernet-phy@5 {
|
||||
reg = <5>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
|
|
@ -123,7 +123,7 @@
|
|||
status = "okay";
|
||||
num-cs = <1>;
|
||||
|
||||
spi0_flash0: flash0@0 {
|
||||
spi0_flash0: flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "sst,sst25wf080", "jedec,spi-nor";
|
||||
|
|
@ -141,7 +141,7 @@
|
|||
status = "okay";
|
||||
num-cs = <1>;
|
||||
|
||||
spi1_flash0: flash0@0 {
|
||||
spi1_flash0: flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash";
|
||||
|
|
@ -158,6 +158,7 @@
|
|||
/* ULPI SMSC USB3320 */
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* dts file for Xilinx ZynqMP zc1751-xm017-dc3
|
||||
*
|
||||
* (C) Copyright 2016 - 2018, Xilinx, Inc.
|
||||
* (C) Copyright 2016 - 2019, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
|
@ -10,7 +10,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ZynqMP zc1751-xm017-dc3 RevA";
|
||||
|
|
@ -73,7 +73,7 @@
|
|||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@0 { /* VSC8211 */
|
||||
phy0: ethernet-phy@0 { /* VSC8211 */
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* dts file for Xilinx ZynqMP zc1751-xm018-dc4
|
||||
*
|
||||
* (C) Copyright 2015 - 2018, Xilinx, Inc.
|
||||
* (C) Copyright 2015 - 2019, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
|
@ -10,7 +10,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ZynqMP zc1751-xm018-dc4";
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* dts file for Xilinx ZynqMP zc1751-xm019-dc5
|
||||
*
|
||||
* (C) Copyright 2015 - 2018, Xilinx, Inc.
|
||||
* (C) Copyright 2015 - 2019, Xilinx, Inc.
|
||||
*
|
||||
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
|
|
@ -11,7 +11,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
|
|
@ -74,7 +74,7 @@
|
|||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@0 {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU100 revC
|
||||
*
|
||||
* (C) Copyright 2016 - 2018, Xilinx, Inc.
|
||||
* (C) Copyright 2016 - 2019, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Nathalie Chan King Choy
|
||||
|
|
@ -11,7 +11,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
|
@ -103,6 +103,11 @@
|
|||
reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */
|
||||
post-power-on-delay-ms = <10>;
|
||||
};
|
||||
|
||||
ina226 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;
|
||||
};
|
||||
};
|
||||
|
||||
&dcc {
|
||||
|
|
@ -191,8 +196,9 @@
|
|||
#size-cells = <0>;
|
||||
reg = <5>;
|
||||
/* PS_PMBUS */
|
||||
ina226@40 { /* u35 */
|
||||
u35: ina226@40 { /* u35 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <10000>;
|
||||
/* MIO31 is alert which should be routed to PMUFW */
|
||||
|
|
@ -226,7 +232,6 @@
|
|||
&sdhci0 {
|
||||
status = "okay";
|
||||
no-1-8-v;
|
||||
broken-cd; /* CD has to be enabled by default */
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
|
|
@ -251,11 +256,13 @@
|
|||
&spi0 { /* Low Speed connector */
|
||||
status = "okay";
|
||||
label = "LS-SPI0";
|
||||
num-cs = <1>;
|
||||
};
|
||||
|
||||
&spi1 { /* High Speed connector */
|
||||
status = "okay";
|
||||
label = "HS-SPI1";
|
||||
num-cs = <1>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
|
|
@ -274,11 +281,13 @@
|
|||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
dr_mode = "peripheral";
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU102 RevA
|
||||
*
|
||||
* (C) Copyright 2015 - 2018, Xilinx, Inc.
|
||||
* (C) Copyright 2015 - 2019, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
|
@ -10,7 +10,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
|
|
@ -59,6 +59,79 @@
|
|||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
ina226-u76 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
|
||||
};
|
||||
ina226-u77 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
|
||||
};
|
||||
ina226-u78 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
|
||||
};
|
||||
ina226-u87 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
|
||||
};
|
||||
ina226-u85 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
|
||||
};
|
||||
ina226-u86 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
|
||||
};
|
||||
ina226-u93 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
|
||||
};
|
||||
ina226-u88 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
|
||||
};
|
||||
ina226-u15 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
|
||||
};
|
||||
ina226-u92 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
|
||||
};
|
||||
ina226-u79 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
|
||||
};
|
||||
ina226-u81 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
|
||||
};
|
||||
ina226-u80 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
|
||||
};
|
||||
ina226-u84 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
|
||||
};
|
||||
ina226-u16 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
|
||||
};
|
||||
ina226-u65 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
|
||||
};
|
||||
ina226-u74 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
|
||||
};
|
||||
ina226-u75 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
|
||||
};
|
||||
};
|
||||
|
||||
&can1 {
|
||||
|
|
@ -105,7 +178,7 @@
|
|||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@21 {
|
||||
phy0: ethernet-phy@21 {
|
||||
reg = <21>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
|
|
@ -125,21 +198,11 @@
|
|||
tca6416_u97: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
gpio-controller; /* IRQ not connected */
|
||||
#gpio-cells = <2>;
|
||||
/*
|
||||
* IRQ not connected
|
||||
* Lines:
|
||||
* 0 - PS_GTR_LAN_SEL0
|
||||
* 1 - PS_GTR_LAN_SEL1
|
||||
* 2 - PS_GTR_LAN_SEL2
|
||||
* 3 - PS_GTR_LAN_SEL3
|
||||
* 4 - PCI_CLK_DIR_SEL
|
||||
* 5 - IIC_MUX_RESET_B
|
||||
* 6 - GEM3_EXP_RESET_B
|
||||
* 7, 10 - 17 - not connected
|
||||
*/
|
||||
|
||||
gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
|
||||
"PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
|
||||
"", "", "", "", "", "", "", "", "";
|
||||
gtr-sel0 {
|
||||
gpio-hog;
|
||||
gpios = <0 0>;
|
||||
|
|
@ -169,27 +232,12 @@
|
|||
tca6416_u61: gpio@21 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x21>;
|
||||
gpio-controller;
|
||||
gpio-controller; /* IRQ not connected */
|
||||
#gpio-cells = <2>;
|
||||
/*
|
||||
* IRQ not connected
|
||||
* Lines:
|
||||
* 0 - VCCPSPLL_EN
|
||||
* 1 - MGTRAVCC_EN
|
||||
* 2 - MGTRAVTT_EN
|
||||
* 3 - VCCPSDDRPLL_EN
|
||||
* 4 - MIO26_PMU_INPUT_LS
|
||||
* 5 - PL_PMBUS_ALERT
|
||||
* 6 - PS_PMBUS_ALERT
|
||||
* 7 - MAXIM_PMBUS_ALERT
|
||||
* 10 - PL_DDR4_VTERM_EN
|
||||
* 11 - PL_DDR4_VPP_2V5_EN
|
||||
* 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
|
||||
* 13 - PS_DIMM_SUSPEND_EN
|
||||
* 14 - PS_DDR4_VTERM_EN
|
||||
* 15 - PS_DDR4_VPP_2V5_EN
|
||||
* 16 - 17 - not connected
|
||||
*/
|
||||
gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS",
|
||||
"PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN",
|
||||
"PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN",
|
||||
"PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", "";
|
||||
};
|
||||
|
||||
i2c-mux@75 { /* u60 */
|
||||
|
|
@ -202,53 +250,73 @@
|
|||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
/* PS_PMBUS */
|
||||
ina226@40 { /* u76 */
|
||||
u76: ina226@40 { /* u76 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u76";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@41 { /* u77 */
|
||||
u77: ina226@41 { /* u77 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u77";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@42 { /* u78 */
|
||||
u78: ina226@42 { /* u78 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u78";
|
||||
reg = <0x42>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@43 { /* u87 */
|
||||
u87: ina226@43 { /* u87 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u87";
|
||||
reg = <0x43>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@44 { /* u85 */
|
||||
u85: ina226@44 { /* u85 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u85";
|
||||
reg = <0x44>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@45 { /* u86 */
|
||||
u86: ina226@45 { /* u86 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u86";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@46 { /* u93 */
|
||||
u93: ina226@46 { /* u93 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u93";
|
||||
reg = <0x46>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@47 { /* u88 */
|
||||
u88: ina226@47 { /* u88 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u88";
|
||||
reg = <0x47>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@4a { /* u15 */
|
||||
u15: ina226@4a { /* u15 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u15";
|
||||
reg = <0x4a>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@4b { /* u92 */
|
||||
u92: ina226@4b { /* u92 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u92";
|
||||
reg = <0x4b>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
|
|
@ -258,43 +326,59 @@
|
|||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
/* PL_PMBUS */
|
||||
ina226@40 { /* u79 */
|
||||
u79: ina226@40 { /* u79 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u79";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <2000>;
|
||||
};
|
||||
ina226@41 { /* u81 */
|
||||
u81: ina226@41 { /* u81 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u81";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@42 { /* u80 */
|
||||
u80: ina226@42 { /* u80 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u80";
|
||||
reg = <0x42>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@43 { /* u84 */
|
||||
u84: ina226@43 { /* u84 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u84";
|
||||
reg = <0x43>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@44 { /* u16 */
|
||||
u16: ina226@44 { /* u16 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u16";
|
||||
reg = <0x44>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@45 { /* u65 */
|
||||
u65: ina226@45 { /* u65 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u65";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@46 { /* u74 */
|
||||
u74: ina226@46 { /* u74 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u74";
|
||||
reg = <0x46>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@47 { /* u75 */
|
||||
u75: ina226@47 { /* u75 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u75";
|
||||
reg = <0x47>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
|
|
@ -414,6 +498,7 @@
|
|||
temperature-stability = <50>;
|
||||
factory-fout = <300000000>;
|
||||
clock-frequency = <300000000>;
|
||||
clock-output-names = "si570_user";
|
||||
};
|
||||
};
|
||||
i2c@3 {
|
||||
|
|
@ -427,6 +512,7 @@
|
|||
temperature-stability = <50>; /* copy from zc702 */
|
||||
factory-fout = <156250000>;
|
||||
clock-frequency = <148500000>;
|
||||
clock-output-names = "si570_mgt";
|
||||
};
|
||||
};
|
||||
i2c@4 {
|
||||
|
|
@ -540,6 +626,7 @@
|
|||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
|
||||
&gem3 {
|
||||
phy-handle = <&phyc>;
|
||||
phyc: phy@c {
|
||||
phyc: ethernet-phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
|
|
@ -24,7 +24,7 @@
|
|||
ti,dp83867-rxctrl-strap-quirk;
|
||||
};
|
||||
/* Cleanup from RevA */
|
||||
/delete-node/ phy@21;
|
||||
/delete-node/ ethernet-phy@21;
|
||||
};
|
||||
|
||||
/* Fix collision with u61 */
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU104
|
||||
*
|
||||
* (C) Copyright 2017 - 2018, Xilinx, Inc.
|
||||
* (C) Copyright 2017 - 2019, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
|
@ -10,7 +10,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
|
|
@ -50,7 +50,7 @@
|
|||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@c {
|
||||
phy0: ethernet-phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
|
|
@ -118,9 +118,9 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
tca6416_u97: gpio@21 {
|
||||
tca6416_u97: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x21>;
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
/*
|
||||
|
|
@ -189,6 +189,7 @@
|
|||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU106
|
||||
*
|
||||
* (C) Copyright 2016, Xilinx, Inc.
|
||||
* (C) Copyright 2016 - 2019, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
|
@ -10,7 +10,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
|
|
@ -59,6 +59,79 @@
|
|||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
ina226-u76 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
|
||||
};
|
||||
ina226-u77 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
|
||||
};
|
||||
ina226-u78 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
|
||||
};
|
||||
ina226-u87 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
|
||||
};
|
||||
ina226-u85 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
|
||||
};
|
||||
ina226-u86 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
|
||||
};
|
||||
ina226-u93 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
|
||||
};
|
||||
ina226-u88 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
|
||||
};
|
||||
ina226-u15 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
|
||||
};
|
||||
ina226-u92 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
|
||||
};
|
||||
ina226-u79 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
|
||||
};
|
||||
ina226-u81 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
|
||||
};
|
||||
ina226-u80 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
|
||||
};
|
||||
ina226-u84 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
|
||||
};
|
||||
ina226-u16 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
|
||||
};
|
||||
ina226-u65 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
|
||||
};
|
||||
ina226-u74 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
|
||||
};
|
||||
ina226-u75 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
|
||||
};
|
||||
};
|
||||
|
||||
&can1 {
|
||||
|
|
@ -106,7 +179,7 @@
|
|||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@c {
|
||||
phy0: ethernet-phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
|
|
@ -177,53 +250,73 @@
|
|||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
/* PS_PMBUS */
|
||||
ina226@40 { /* u76 */
|
||||
u76: ina226@40 { /* u76 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u76";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@41 { /* u77 */
|
||||
u77: ina226@41 { /* u77 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u77";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@42 { /* u78 */
|
||||
u78: ina226@42 { /* u78 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u78";
|
||||
reg = <0x42>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@43 { /* u87 */
|
||||
u87: ina226@43 { /* u87 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u87";
|
||||
reg = <0x43>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@44 { /* u85 */
|
||||
u85: ina226@44 { /* u85 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u85";
|
||||
reg = <0x44>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@45 { /* u86 */
|
||||
u86: ina226@45 { /* u86 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u86";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@46 { /* u93 */
|
||||
u93: ina226@46 { /* u93 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u93";
|
||||
reg = <0x46>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@47 { /* u88 */
|
||||
u88: ina226@47 { /* u88 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u88";
|
||||
reg = <0x47>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@4a { /* u15 */
|
||||
u15: ina226@4a { /* u15 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u15";
|
||||
reg = <0x4a>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@4b { /* u92 */
|
||||
u92: ina226@4b { /* u92 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u92";
|
||||
reg = <0x4b>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
|
|
@ -233,43 +326,59 @@
|
|||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
/* PL_PMBUS */
|
||||
ina226@40 { /* u79 */
|
||||
u79: ina226@40 { /* u79 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u79";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <2000>;
|
||||
};
|
||||
ina226@41 { /* u81 */
|
||||
u81: ina226@41 { /* u81 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u81";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@42 { /* u80 */
|
||||
u80: ina226@42 { /* u80 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u80";
|
||||
reg = <0x42>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@43 { /* u84 */
|
||||
u84: ina226@43 { /* u84 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u84";
|
||||
reg = <0x43>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@44 { /* u16 */
|
||||
u16: ina226@44 { /* u16 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u16";
|
||||
reg = <0x44>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@45 { /* u65 */
|
||||
u65: ina226@45 { /* u65 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u65";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@46 { /* u74 */
|
||||
u74: ina226@46 { /* u74 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u74";
|
||||
reg = <0x46>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@47 { /* u75 */
|
||||
u75: ina226@47 { /* u75 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u75";
|
||||
reg = <0x47>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
|
|
@ -388,6 +497,7 @@
|
|||
temperature-stability = <50>;
|
||||
factory-fout = <300000000>;
|
||||
clock-frequency = <300000000>;
|
||||
clock-output-names = "si570_user";
|
||||
};
|
||||
};
|
||||
i2c@3 {
|
||||
|
|
@ -401,6 +511,7 @@
|
|||
temperature-stability = <50>; /* copy from zc702 */
|
||||
factory-fout = <156250000>;
|
||||
clock-frequency = <148500000>;
|
||||
clock-output-names = "si570_mgt";
|
||||
};
|
||||
};
|
||||
i2c@4 {
|
||||
|
|
@ -514,6 +625,7 @@
|
|||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU111
|
||||
*
|
||||
* (C) Copyright 2017 - 2018, Xilinx, Inc.
|
||||
* (C) Copyright 2017 - 2019, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
|
@ -10,7 +10,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
|
|
@ -59,6 +59,63 @@
|
|||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
ina226-u67 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>;
|
||||
};
|
||||
ina226-u59 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>;
|
||||
};
|
||||
ina226-u61 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;
|
||||
};
|
||||
ina226-u60 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;
|
||||
};
|
||||
ina226-u64 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;
|
||||
};
|
||||
ina226-u69 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>;
|
||||
};
|
||||
ina226-u66 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>;
|
||||
};
|
||||
ina226-u65 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
|
||||
};
|
||||
ina226-u63 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;
|
||||
};
|
||||
ina226-u3 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>;
|
||||
};
|
||||
ina226-u71 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>;
|
||||
};
|
||||
ina226-u77 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
|
||||
};
|
||||
ina226-u73 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>;
|
||||
};
|
||||
ina226-u79 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
|
||||
};
|
||||
};
|
||||
|
||||
&dcc {
|
||||
|
|
@ -101,7 +158,7 @@
|
|||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@c {
|
||||
phy0: ethernet-phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
|
|
@ -152,73 +209,101 @@
|
|||
reg = <0>;
|
||||
/* PS_PMBUS */
|
||||
/* PMBUS_ALERT done via pca9544 */
|
||||
ina226@40 { /* u67 */
|
||||
u67: ina226@40 { /* u67 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u67";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <2000>;
|
||||
};
|
||||
ina226@41 { /* u59 */
|
||||
u59: ina226@41 { /* u59 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u59";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@42 { /* u61 */
|
||||
u61: ina226@42 { /* u61 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u61";
|
||||
reg = <0x42>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@43 { /* u60 */
|
||||
u60: ina226@43 { /* u60 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u60";
|
||||
reg = <0x43>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@45 { /* u64 */
|
||||
u64: ina226@45 { /* u64 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u64";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@46 { /* u69 */
|
||||
u69: ina226@46 { /* u69 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u69";
|
||||
reg = <0x46>;
|
||||
shunt-resistor = <2000>;
|
||||
};
|
||||
ina226@47 { /* u66 */
|
||||
u66: ina226@47 { /* u66 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u66";
|
||||
reg = <0x47>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@48 { /* u65 */
|
||||
u65: ina226@48 { /* u65 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u65";
|
||||
reg = <0x48>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@49 { /* u63 */
|
||||
u63: ina226@49 { /* u63 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u63";
|
||||
reg = <0x49>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@4a { /* u3 */
|
||||
u3: ina226@4a { /* u3 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u3";
|
||||
reg = <0x4a>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@4b { /* u71 */
|
||||
u71: ina226@4b { /* u71 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u71";
|
||||
reg = <0x4b>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@4c { /* u77 */
|
||||
u77: ina226@4c { /* u77 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u77";
|
||||
reg = <0x4c>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@4d { /* u73 */
|
||||
u73: ina226@4d { /* u73 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u73";
|
||||
reg = <0x4d>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@4e { /* u79 */
|
||||
u79: ina226@4e { /* u79 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u79";
|
||||
reg = <0x4e>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
|
|
@ -304,6 +389,7 @@
|
|||
temperature-stability = <50>;
|
||||
factory-fout = <300000000>;
|
||||
clock-frequency = <300000000>;
|
||||
clock-output-names = "si570_user";
|
||||
};
|
||||
};
|
||||
i2c@3 {
|
||||
|
|
@ -316,7 +402,8 @@
|
|||
reg = <0x5d>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <156250000>;
|
||||
clock-frequency = <148500000>;
|
||||
clock-frequency = <156250000>;
|
||||
clock-output-names = "si570_mgt";
|
||||
};
|
||||
};
|
||||
i2c@4 {
|
||||
|
|
@ -440,4 +527,5 @@
|
|||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* dts file for Xilinx ZynqMP
|
||||
*
|
||||
* (C) Copyright 2014 - 2015, Xilinx, Inc.
|
||||
* (C) Copyright 2014 - 2019, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*
|
||||
|
|
@ -12,6 +12,8 @@
|
|||
* the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/power/xlnx-zynqmp-power.h>
|
||||
|
||||
/ {
|
||||
compatible = "xlnx,zynqmp";
|
||||
#address-cells = <2>;
|
||||
|
|
@ -118,8 +120,31 @@
|
|||
firmware {
|
||||
zynqmp_firmware: zynqmp-firmware {
|
||||
compatible = "xlnx,zynqmp-firmware";
|
||||
#power-domain-cells = <1>;
|
||||
method = "smc";
|
||||
|
||||
zynqmp_power: zynqmp-power {
|
||||
compatible = "xlnx,zynqmp-power";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 35 4>;
|
||||
};
|
||||
|
||||
zynqmp_clk: clock-controller {
|
||||
u-boot,dm-pre-reloc;
|
||||
#clock-cells = <1>;
|
||||
compatible = "xlnx,zynqmp-clk";
|
||||
clocks = <&pss_ref_clk>,
|
||||
<&video_clk>,
|
||||
<&pss_alt_ref_clk>,
|
||||
<&aux_ref_clk>,
|
||||
<>_crx_ref_clk>;
|
||||
clock-names = "pss_ref_clk",
|
||||
"video_clk",
|
||||
"pss_alt_ref_clk",
|
||||
"aux_ref_clk",
|
||||
"gt_crx_ref_clk";
|
||||
};
|
||||
|
||||
nvmem_firmware {
|
||||
compatible = "xlnx,zynqmp-nvmem-fw";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -187,6 +212,7 @@
|
|||
interrupt-parent = <&gic>;
|
||||
tx-fifo-depth = <0x40>;
|
||||
rx-fifo-depth = <0x40>;
|
||||
power-domains = <&zynqmp_firmware PD_CAN_0>;
|
||||
};
|
||||
|
||||
can1: can@ff070000 {
|
||||
|
|
@ -198,6 +224,7 @@
|
|||
interrupt-parent = <&gic>;
|
||||
tx-fifo-depth = <0x40>;
|
||||
rx-fifo-depth = <0x40>;
|
||||
power-domains = <&zynqmp_firmware PD_CAN_1>;
|
||||
};
|
||||
|
||||
cci: cci@fd6e0000 {
|
||||
|
|
@ -228,6 +255,7 @@
|
|||
interrupts = <0 124 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <128>;
|
||||
power-domains = <&zynqmp_firmware PD_GDMA>;
|
||||
};
|
||||
|
||||
fpd_dma_chan2: dma@fd510000 {
|
||||
|
|
@ -238,6 +266,7 @@
|
|||
interrupts = <0 125 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <128>;
|
||||
power-domains = <&zynqmp_firmware PD_GDMA>;
|
||||
};
|
||||
|
||||
fpd_dma_chan3: dma@fd520000 {
|
||||
|
|
@ -248,6 +277,7 @@
|
|||
interrupts = <0 126 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <128>;
|
||||
power-domains = <&zynqmp_firmware PD_GDMA>;
|
||||
};
|
||||
|
||||
fpd_dma_chan4: dma@fd530000 {
|
||||
|
|
@ -258,6 +288,7 @@
|
|||
interrupts = <0 127 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <128>;
|
||||
power-domains = <&zynqmp_firmware PD_GDMA>;
|
||||
};
|
||||
|
||||
fpd_dma_chan5: dma@fd540000 {
|
||||
|
|
@ -268,6 +299,7 @@
|
|||
interrupts = <0 128 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <128>;
|
||||
power-domains = <&zynqmp_firmware PD_GDMA>;
|
||||
};
|
||||
|
||||
fpd_dma_chan6: dma@fd550000 {
|
||||
|
|
@ -278,6 +310,7 @@
|
|||
interrupts = <0 129 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <128>;
|
||||
power-domains = <&zynqmp_firmware PD_GDMA>;
|
||||
};
|
||||
|
||||
fpd_dma_chan7: dma@fd560000 {
|
||||
|
|
@ -288,6 +321,7 @@
|
|||
interrupts = <0 130 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <128>;
|
||||
power-domains = <&zynqmp_firmware PD_GDMA>;
|
||||
};
|
||||
|
||||
fpd_dma_chan8: dma@fd570000 {
|
||||
|
|
@ -298,6 +332,7 @@
|
|||
interrupts = <0 131 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <128>;
|
||||
power-domains = <&zynqmp_firmware PD_GDMA>;
|
||||
};
|
||||
|
||||
/* LPDDMA default allows only secured access. inorder to enable
|
||||
|
|
@ -312,6 +347,7 @@
|
|||
interrupts = <0 77 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <64>;
|
||||
power-domains = <&zynqmp_firmware PD_ADMA>;
|
||||
};
|
||||
|
||||
lpd_dma_chan2: dma@ffa90000 {
|
||||
|
|
@ -322,6 +358,7 @@
|
|||
interrupts = <0 78 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <64>;
|
||||
power-domains = <&zynqmp_firmware PD_ADMA>;
|
||||
};
|
||||
|
||||
lpd_dma_chan3: dma@ffaa0000 {
|
||||
|
|
@ -332,6 +369,7 @@
|
|||
interrupts = <0 79 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <64>;
|
||||
power-domains = <&zynqmp_firmware PD_ADMA>;
|
||||
};
|
||||
|
||||
lpd_dma_chan4: dma@ffab0000 {
|
||||
|
|
@ -342,6 +380,7 @@
|
|||
interrupts = <0 80 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <64>;
|
||||
power-domains = <&zynqmp_firmware PD_ADMA>;
|
||||
};
|
||||
|
||||
lpd_dma_chan5: dma@ffac0000 {
|
||||
|
|
@ -352,6 +391,7 @@
|
|||
interrupts = <0 81 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <64>;
|
||||
power-domains = <&zynqmp_firmware PD_ADMA>;
|
||||
};
|
||||
|
||||
lpd_dma_chan6: dma@ffad0000 {
|
||||
|
|
@ -362,6 +402,7 @@
|
|||
interrupts = <0 82 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <64>;
|
||||
power-domains = <&zynqmp_firmware PD_ADMA>;
|
||||
};
|
||||
|
||||
lpd_dma_chan7: dma@ffae0000 {
|
||||
|
|
@ -372,6 +413,7 @@
|
|||
interrupts = <0 83 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <64>;
|
||||
power-domains = <&zynqmp_firmware PD_ADMA>;
|
||||
};
|
||||
|
||||
lpd_dma_chan8: dma@ffaf0000 {
|
||||
|
|
@ -382,6 +424,7 @@
|
|||
interrupts = <0 84 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <64>;
|
||||
power-domains = <&zynqmp_firmware PD_ADMA>;
|
||||
};
|
||||
|
||||
mc: memory-controller@fd070000 {
|
||||
|
|
@ -400,6 +443,7 @@
|
|||
clock-names = "pclk", "hclk", "tx_clk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&zynqmp_firmware PD_ETH_0>;
|
||||
};
|
||||
|
||||
gem1: ethernet@ff0c0000 {
|
||||
|
|
@ -411,6 +455,7 @@
|
|||
clock-names = "pclk", "hclk", "tx_clk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&zynqmp_firmware PD_ETH_1>;
|
||||
};
|
||||
|
||||
gem2: ethernet@ff0d0000 {
|
||||
|
|
@ -422,6 +467,7 @@
|
|||
clock-names = "pclk", "hclk", "tx_clk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&zynqmp_firmware PD_ETH_2>;
|
||||
};
|
||||
|
||||
gem3: ethernet@ff0e0000 {
|
||||
|
|
@ -433,6 +479,7 @@
|
|||
clock-names = "pclk", "hclk", "tx_clk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&zynqmp_firmware PD_ETH_3>;
|
||||
};
|
||||
|
||||
gpio: gpio@ff0a0000 {
|
||||
|
|
@ -445,6 +492,7 @@
|
|||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x0 0xff0a0000 0x0 0x1000>;
|
||||
power-domains = <&zynqmp_firmware PD_GPIO>;
|
||||
};
|
||||
|
||||
i2c0: i2c@ff020000 {
|
||||
|
|
@ -455,6 +503,7 @@
|
|||
reg = <0x0 0xff020000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&zynqmp_firmware PD_I2C_0>;
|
||||
};
|
||||
|
||||
i2c1: i2c@ff030000 {
|
||||
|
|
@ -465,6 +514,7 @@
|
|||
reg = <0x0 0xff030000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&zynqmp_firmware PD_I2C_1>;
|
||||
};
|
||||
|
||||
pcie: pcie@fd0e0000 {
|
||||
|
|
@ -496,6 +546,7 @@
|
|||
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
|
||||
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
|
||||
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
|
||||
power-domains = <&zynqmp_firmware PD_PCIE>;
|
||||
pcie_intc: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
|
|
@ -519,24 +570,31 @@
|
|||
reg = <0x0 0xfd0c0000 0x0 0x2000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 133 4>;
|
||||
power-domains = <&zynqmp_firmware PD_SATA>;
|
||||
};
|
||||
|
||||
sdhci0: mmc@ff160000 {
|
||||
compatible = "arasan,sdhci-8.9a";
|
||||
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 48 4>;
|
||||
reg = <0x0 0xff160000 0x0 0x1000>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "clk_out_sd0", "clk_in_sd0";
|
||||
power-domains = <&zynqmp_firmware PD_SD_0>;
|
||||
};
|
||||
|
||||
sdhci1: mmc@ff170000 {
|
||||
compatible = "arasan,sdhci-8.9a";
|
||||
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 49 4>;
|
||||
reg = <0x0 0xff170000 0x0 0x1000>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "clk_out_sd1", "clk_in_sd1";
|
||||
power-domains = <&zynqmp_firmware PD_SD_1>;
|
||||
};
|
||||
|
||||
smmu: smmu@fd800000 {
|
||||
|
|
@ -561,6 +619,7 @@
|
|||
clock-names = "ref_clk", "pclk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&zynqmp_firmware PD_SPI_0>;
|
||||
};
|
||||
|
||||
spi1: spi@ff050000 {
|
||||
|
|
@ -572,6 +631,7 @@
|
|||
clock-names = "ref_clk", "pclk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&zynqmp_firmware PD_SPI_1>;
|
||||
};
|
||||
|
||||
ttc0: timer@ff110000 {
|
||||
|
|
@ -581,6 +641,7 @@
|
|||
interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
|
||||
reg = <0x0 0xff110000 0x0 0x1000>;
|
||||
timer-width = <32>;
|
||||
power-domains = <&zynqmp_firmware PD_TTC_0>;
|
||||
};
|
||||
|
||||
ttc1: timer@ff120000 {
|
||||
|
|
@ -590,6 +651,7 @@
|
|||
interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
|
||||
reg = <0x0 0xff120000 0x0 0x1000>;
|
||||
timer-width = <32>;
|
||||
power-domains = <&zynqmp_firmware PD_TTC_1>;
|
||||
};
|
||||
|
||||
ttc2: timer@ff130000 {
|
||||
|
|
@ -599,6 +661,7 @@
|
|||
interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
|
||||
reg = <0x0 0xff130000 0x0 0x1000>;
|
||||
timer-width = <32>;
|
||||
power-domains = <&zynqmp_firmware PD_TTC_2>;
|
||||
};
|
||||
|
||||
ttc3: timer@ff140000 {
|
||||
|
|
@ -608,6 +671,7 @@
|
|||
interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
|
||||
reg = <0x0 0xff140000 0x0 0x1000>;
|
||||
timer-width = <32>;
|
||||
power-domains = <&zynqmp_firmware PD_TTC_3>;
|
||||
};
|
||||
|
||||
uart0: serial@ff000000 {
|
||||
|
|
@ -617,6 +681,7 @@
|
|||
interrupts = <0 21 4>;
|
||||
reg = <0x0 0xff000000 0x0 0x1000>;
|
||||
clock-names = "uart_clk", "pclk";
|
||||
power-domains = <&zynqmp_firmware PD_UART_0>;
|
||||
};
|
||||
|
||||
uart1: serial@ff010000 {
|
||||
|
|
@ -626,6 +691,7 @@
|
|||
interrupts = <0 22 4>;
|
||||
reg = <0x0 0xff010000 0x0 0x1000>;
|
||||
clock-names = "uart_clk", "pclk";
|
||||
power-domains = <&zynqmp_firmware PD_UART_1>;
|
||||
};
|
||||
|
||||
usb0: usb@fe200000 {
|
||||
|
|
@ -635,6 +701,7 @@
|
|||
interrupts = <0 65 4>;
|
||||
reg = <0x0 0xfe200000 0x0 0x40000>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
power-domains = <&zynqmp_firmware PD_USB_0>;
|
||||
};
|
||||
|
||||
usb1: usb@fe300000 {
|
||||
|
|
@ -644,6 +711,7 @@
|
|||
interrupts = <0 70 4>;
|
||||
reg = <0x0 0xfe300000 0x0 0x40000>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
power-domains = <&zynqmp_firmware PD_USB_1>;
|
||||
};
|
||||
|
||||
watchdog0: watchdog@fd4d0000 {
|
||||
|
|
|
|||
Loading…
Reference in New Issue