drm/i915/gvt: handle force-nonpriv registers, cmd parser part
this patch adds force non-priv registers check in LRI cmds handler v4: transform is_force_nonpriv_mmio() from macro to inline fuction to eliminate checkpatch warning v3: per zhenyu's comment, fix some style warnings v2: per zhenyu's comment, refine the code to remove cascaded ifs Signed-off-by: Zhao Yan <yan.y.zhao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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@ -817,6 +817,25 @@ static bool is_shadowed_mmio(unsigned int offset)
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return ret;
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return ret;
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}
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}
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static inline bool is_force_nonpriv_mmio(unsigned int offset)
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{
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return (offset >= 0x24d0 && offset < 0x2500);
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}
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static int force_nonpriv_reg_handler(struct parser_exec_state *s,
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unsigned int offset, unsigned int index)
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{
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struct intel_gvt *gvt = s->vgpu->gvt;
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unsigned int data = cmd_val(s, index + 1);
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if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data)) {
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gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",
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offset, data);
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return -EINVAL;
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}
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return 0;
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}
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static int cmd_reg_handler(struct parser_exec_state *s,
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static int cmd_reg_handler(struct parser_exec_state *s,
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unsigned int offset, unsigned int index, char *cmd)
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unsigned int offset, unsigned int index, char *cmd)
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{
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{
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@ -841,6 +860,10 @@ static int cmd_reg_handler(struct parser_exec_state *s,
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return 0;
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return 0;
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}
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}
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if (is_force_nonpriv_mmio(offset) &&
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force_nonpriv_reg_handler(s, offset, index))
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return -EINVAL;
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if (offset == i915_mmio_reg_offset(DERRMR) ||
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if (offset == i915_mmio_reg_offset(DERRMR) ||
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offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
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offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
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/* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
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/* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
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@ -2988,3 +2988,20 @@ int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
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write_vreg(vgpu, offset, p_data, bytes);
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write_vreg(vgpu, offset, p_data, bytes);
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return 0;
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return 0;
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}
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}
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/**
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* intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be
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* force-nopriv register
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*
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* @gvt: a GVT device
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* @offset: register offset
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*
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* Returns:
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* True if the register is in force-nonpriv whitelist;
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* False if outside;
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*/
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bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
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unsigned int offset)
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{
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return in_whitelist(offset);
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}
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@ -107,4 +107,7 @@ int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
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void *p_data, unsigned int bytes);
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void *p_data, unsigned int bytes);
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int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
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int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
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void *p_data, unsigned int bytes);
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void *p_data, unsigned int bytes);
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bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
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unsigned int offset);
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#endif
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#endif
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