x86/tsc: Force inlining of cyc2ns bits

Looking at the asm for native_sched_clock() I noticed we don't inline
enough. Mostly caused by sharing code with cyc2ns_read_begin(), which
we didn't used to do. So mark all that __force_inline to make it DTRT.

Fixes: 59eaef78bf ("x86/tsc: Remodel cyc2ns to use seqcount_latch()")
Reported-by: Eric Dumazet <edumazet@google.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: hpa@zytor.com
Cc: eric.dumazet@gmail.com
Cc: bp@alien8.de
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20181011104019.695196158@infradead.org
This commit is contained in:
Peter Zijlstra 2018-10-11 12:38:26 +02:00 committed by Thomas Gleixner
parent 3a27203102
commit 4907c68abd
1 changed files with 3 additions and 3 deletions

View File

@ -58,7 +58,7 @@ struct cyc2ns {
static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns);
void cyc2ns_read_begin(struct cyc2ns_data *data)
void __always_inline cyc2ns_read_begin(struct cyc2ns_data *data)
{
int seq, idx;
@ -75,7 +75,7 @@ void cyc2ns_read_begin(struct cyc2ns_data *data)
} while (unlikely(seq != this_cpu_read(cyc2ns.seq.sequence)));
}
void cyc2ns_read_end(void)
void __always_inline cyc2ns_read_end(void)
{
preempt_enable_notrace();
}
@ -104,7 +104,7 @@ void cyc2ns_read_end(void)
* -johnstul@us.ibm.com "math is hard, lets go shopping!"
*/
static inline unsigned long long cycles_2_ns(unsigned long long cyc)
static __always_inline unsigned long long cycles_2_ns(unsigned long long cyc)
{
struct cyc2ns_data data;
unsigned long long ns;