powerpc/4xx: update ml507 .dts file to release reference design
This patch updates the Xilinx ML507 device tree to match the released ML507 powerpc reference design (ml507_ppc440_emb_ref). This patch is needed to boot Linux on the ML507 powerpc reference design without manually generating and tweaking a device tree from the project directory. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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Grant Likely
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aafbf16b89
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@ -7,6 +7,15 @@
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*
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* ---
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*
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* Device Tree Generator version: 1.1
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*
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* CAUTION: This file is automatically generated by libgen.
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* Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
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*
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* XPS project directory: ml507_ppc440_emb_ref
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*/
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/dts-v1/;
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@ -22,8 +31,8 @@
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reg = < 0 0x10000000 >;
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} ;
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chosen {
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bootargs = "console=ttyS0 ip=on root=/dev/ram";
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linux,stdout-path = "/plb@0/serial@83e00000";
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bootargs = "console=ttyS0 root=/dev/ram";
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linux,stdout-path = &RS232_Uart_1;
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} ;
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cpus {
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#address-cells = <1>;
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@ -136,19 +145,19 @@
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compatible = "xlnx,ll-dma-1.00.a";
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dcr-reg = < 0x80 0x11 >;
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interrupt-parent = <&xps_intc_0>;
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interrupts = < 9 2 0xa 2 >;
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interrupts = < 10 2 11 2 >;
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} ;
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} ;
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} ;
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plb_v46_0: plb@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xlnx,plb-v46-1.02.a", "simple-bus";
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compatible = "xlnx,plb-v46-1.03.a", "simple-bus";
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ranges ;
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DIP_Switches_8Bit: gpio@81460000 {
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compatible = "xlnx,xps-gpio-1.00.a";
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interrupt-parent = <&xps_intc_0>;
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interrupts = < 6 2 >;
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interrupts = < 7 2 >;
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reg = < 0x81460000 0x10000 >;
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xlnx,all-inputs = <1>;
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xlnx,all-inputs-2 = <0>;
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@ -163,6 +172,86 @@
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xlnx,tri-default = <0xffffffff>;
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xlnx,tri-default-2 = <0xffffffff>;
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} ;
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FLASH: flash@fc000000 {
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bank-width = <2>;
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compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
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reg = < 0xfc000000 0x2000000 >;
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xlnx,family = "virtex5";
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xlnx,include-datawidth-matching-0 = <0x1>;
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xlnx,include-datawidth-matching-1 = <0x0>;
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xlnx,include-datawidth-matching-2 = <0x0>;
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xlnx,include-datawidth-matching-3 = <0x0>;
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xlnx,include-negedge-ioregs = <0x0>;
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xlnx,include-plb-ipif = <0x1>;
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xlnx,include-wrbuf = <0x1>;
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xlnx,max-mem-width = <0x10>;
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xlnx,mch-native-dwidth = <0x20>;
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xlnx,mch-plb-clk-period-ps = <0x2710>;
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xlnx,mch-splb-awidth = <0x20>;
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xlnx,mch0-accessbuf-depth = <0x10>;
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xlnx,mch0-protocol = <0x0>;
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xlnx,mch0-rddatabuf-depth = <0x10>;
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xlnx,mch1-accessbuf-depth = <0x10>;
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xlnx,mch1-protocol = <0x0>;
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xlnx,mch1-rddatabuf-depth = <0x10>;
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xlnx,mch2-accessbuf-depth = <0x10>;
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xlnx,mch2-protocol = <0x0>;
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xlnx,mch2-rddatabuf-depth = <0x10>;
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xlnx,mch3-accessbuf-depth = <0x10>;
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xlnx,mch3-protocol = <0x0>;
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xlnx,mch3-rddatabuf-depth = <0x10>;
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xlnx,mem0-width = <0x10>;
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xlnx,mem1-width = <0x20>;
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xlnx,mem2-width = <0x20>;
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xlnx,mem3-width = <0x20>;
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xlnx,num-banks-mem = <0x1>;
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xlnx,num-channels = <0x2>;
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xlnx,priority-mode = <0x0>;
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xlnx,synch-mem-0 = <0x0>;
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xlnx,synch-mem-1 = <0x0>;
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xlnx,synch-mem-2 = <0x0>;
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xlnx,synch-mem-3 = <0x0>;
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xlnx,synch-pipedelay-0 = <0x2>;
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xlnx,synch-pipedelay-1 = <0x2>;
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xlnx,synch-pipedelay-2 = <0x2>;
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xlnx,synch-pipedelay-3 = <0x2>;
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xlnx,tavdv-ps-mem-0 = <0x1adb0>;
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xlnx,tavdv-ps-mem-1 = <0x3a98>;
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xlnx,tavdv-ps-mem-2 = <0x3a98>;
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xlnx,tavdv-ps-mem-3 = <0x3a98>;
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xlnx,tcedv-ps-mem-0 = <0x1adb0>;
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xlnx,tcedv-ps-mem-1 = <0x3a98>;
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xlnx,tcedv-ps-mem-2 = <0x3a98>;
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xlnx,tcedv-ps-mem-3 = <0x3a98>;
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xlnx,thzce-ps-mem-0 = <0x88b8>;
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xlnx,thzce-ps-mem-1 = <0x1b58>;
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xlnx,thzce-ps-mem-2 = <0x1b58>;
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xlnx,thzce-ps-mem-3 = <0x1b58>;
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xlnx,thzoe-ps-mem-0 = <0x1b58>;
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xlnx,thzoe-ps-mem-1 = <0x1b58>;
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xlnx,thzoe-ps-mem-2 = <0x1b58>;
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xlnx,thzoe-ps-mem-3 = <0x1b58>;
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xlnx,tlzwe-ps-mem-0 = <0x88b8>;
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xlnx,tlzwe-ps-mem-1 = <0x0>;
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xlnx,tlzwe-ps-mem-2 = <0x0>;
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xlnx,tlzwe-ps-mem-3 = <0x0>;
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xlnx,twc-ps-mem-0 = <0x2af8>;
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xlnx,twc-ps-mem-1 = <0x3a98>;
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xlnx,twc-ps-mem-2 = <0x3a98>;
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xlnx,twc-ps-mem-3 = <0x3a98>;
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xlnx,twp-ps-mem-0 = <0x11170>;
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xlnx,twp-ps-mem-1 = <0x2ee0>;
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xlnx,twp-ps-mem-2 = <0x2ee0>;
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xlnx,twp-ps-mem-3 = <0x2ee0>;
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xlnx,xcl0-linesize = <0x4>;
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xlnx,xcl0-writexfer = <0x1>;
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xlnx,xcl1-linesize = <0x4>;
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xlnx,xcl1-writexfer = <0x1>;
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xlnx,xcl2-linesize = <0x4>;
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xlnx,xcl2-writexfer = <0x1>;
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xlnx,xcl3-linesize = <0x4>;
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xlnx,xcl3-writexfer = <0x1>;
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} ;
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Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
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#address-cells = <1>;
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#size-cells = <1>;
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@ -185,6 +274,19 @@
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xlnx,txfifo = <0x1000>;
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} ;
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} ;
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IIC_EEPROM: i2c@81600000 {
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compatible = "xlnx,xps-iic-2.00.a";
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interrupt-parent = <&xps_intc_0>;
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interrupts = < 6 2 >;
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reg = < 0x81600000 0x10000 >;
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xlnx,clk-freq = <0x5f5e100>;
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xlnx,family = "virtex5";
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xlnx,gpo-width = <0x1>;
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xlnx,iic-freq = <0x186a0>;
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xlnx,scl-inertial-delay = <0x0>;
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xlnx,sda-inertial-delay = <0x0>;
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xlnx,ten-bit-adr = <0x0>;
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} ;
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LEDs_8Bit: gpio@81400000 {
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compatible = "xlnx,xps-gpio-1.00.a";
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reg = < 0x81400000 0x10000 >;
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@ -220,7 +322,7 @@
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Push_Buttons_5Bit: gpio@81440000 {
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compatible = "xlnx,xps-gpio-1.00.a";
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interrupt-parent = <&xps_intc_0>;
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interrupts = < 7 2 >;
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interrupts = < 8 2 >;
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reg = < 0x81440000 0x10000 >;
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xlnx,all-inputs = <1>;
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xlnx,all-inputs-2 = <0>;
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@ -237,13 +339,13 @@
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} ;
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RS232_Uart_1: serial@83e00000 {
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clock-frequency = <100000000>;
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compatible = "xlnx,xps-uart16550-2.00.a", "ns16550";
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current-speed = <0x2580>;
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compatible = "xlnx,xps-uart16550-2.00.b", "ns16550";
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current-speed = <9600>;
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device_type = "serial";
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interrupt-parent = <&xps_intc_0>;
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interrupts = < 8 2 >;
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interrupts = < 9 2 >;
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reg = < 0x83e00000 0x10000 >;
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reg-offset = <3>;
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reg-offset = <0x1003>;
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reg-shift = <2>;
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xlnx,family = "virtex5";
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xlnx,has-external-rclk = <0>;
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@ -268,7 +370,7 @@
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compatible = "xlnx,xps-intc-1.00.a";
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interrupt-controller ;
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reg = < 0x81800000 0x10000 >;
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xlnx,num-intr-inputs = <0xb>;
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xlnx,num-intr-inputs = <0xc>;
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} ;
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xps_timebase_wdt_1: xps-timebase-wdt@83a00000 {
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compatible = "xlnx,xps-timebase-wdt-1.00.b";
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