ARM: PRIMA2: add new SiRFmarco SMP SoC infrastructures
this patch adds tick timer, smp entries and generic DT machine for SiRFmarco dual-core SMP chips. with the added marco, we change the defconfig, using the same defconfig, we get a zImage which can work on both prima2 and marco. Signed-off-by: Barry Song <Baohua.Song@csr.com> Cc: Mark Rutland <mark.rutland@arm.com>
This commit is contained in:
Barry Song
Barry Song
parent
f2a94192d9
commit
4898de3d15
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@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
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kirkwood-ts219-6281.dtb \
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kirkwood-ts219-6282.dtb \
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kirkwood-openblocks_a6.dtb
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dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
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dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \
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msm8960-cdp.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
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@ -11,6 +11,9 @@ CONFIG_PARTITION_ADVANCED=y
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CONFIG_BSD_DISKLABEL=y
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CONFIG_SOLARIS_X86_PARTITION=y
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CONFIG_ARCH_SIRF=y
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# CONFIG_SWP_EMULATE is not set
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CONFIG_SMP=y
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CONFIG_SCHED_MC=y
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CONFIG_PREEMPT=y
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CONFIG_AEABI=y
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CONFIG_KEXEC=y
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@ -11,6 +11,16 @@ config ARCH_PRIMA2
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help
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Support for CSR SiRFSoC ARM Cortex A9 Platform
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config ARCH_MARCO
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bool "CSR SiRFSoC MARCO ARM Cortex A9 Platform"
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default y
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select ARM_GIC
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select CPU_V7
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select HAVE_SMP
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select SMP_ON_UP
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help
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Support for CSR SiRFSoC ARM Cortex A9 Platform
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endmenu
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config SIRF_IRQ
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@ -5,4 +5,7 @@ obj-$(CONFIG_DEBUG_LL) += lluart.o
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obj-$(CONFIG_CACHE_L2X0) += l2x0.o
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obj-$(CONFIG_SUSPEND) += pm.o sleep.o
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obj-$(CONFIG_SIRF_IRQ) += irq.o
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obj-$(CONFIG_SMP) += platsmp.o headsmp.o
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obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
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obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o
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obj-$(CONFIG_ARCH_MARCO) += timer-marco.o
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@ -8,9 +8,11 @@
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/of_irq.h>
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#include <asm/sizes.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/hardware/gic.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include "common.h"
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@ -30,6 +32,12 @@ void __init sirfsoc_init_late(void)
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sirfsoc_pm_init();
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}
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static __init void sirfsoc_map_io(void)
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{
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sirfsoc_map_lluart();
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sirfsoc_map_scu();
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}
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#ifdef CONFIG_ARCH_PRIMA2
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static const char *prima2_dt_match[] __initdata = {
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"sirf,prima2",
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@ -38,7 +46,7 @@ static const char *prima2_dt_match[] __initdata = {
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DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
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/* Maintainer: Barry Song <baohua.song@csr.com> */
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.map_io = sirfsoc_map_lluart,
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.map_io = sirfsoc_map_io,
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.init_irq = sirfsoc_of_irq_init,
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.init_time = sirfsoc_prima2_timer_init,
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#ifdef CONFIG_MULTI_IRQ_HANDLER
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@ -51,3 +59,33 @@ DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
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.restart = sirfsoc_restart,
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MACHINE_END
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#endif
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#ifdef CONFIG_ARCH_MARCO
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static const struct of_device_id marco_irq_match[] __initconst = {
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{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
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{ /* sentinel */ }
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};
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static void __init marco_init_irq(void)
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{
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of_irq_init(marco_irq_match);
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}
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static const char *marco_dt_match[] __initdata = {
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"sirf,marco",
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NULL
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};
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DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)")
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/* Maintainer: Barry Song <baohua.song@csr.com> */
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.smp = smp_ops(sirfsoc_smp_ops),
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.map_io = sirfsoc_map_io,
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.init_irq = marco_init_irq,
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.init_time = sirfsoc_marco_timer_init,
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.handle_irq = gic_handle_irq,
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.init_machine = sirfsoc_mach_init,
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.init_late = sirfsoc_init_late,
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.dt_compat = marco_dt_match,
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.restart = sirfsoc_restart,
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MACHINE_END
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#endif
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@ -14,6 +14,11 @@
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#include <asm/exception.h>
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extern void sirfsoc_prima2_timer_init(void);
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extern void sirfsoc_marco_timer_init(void);
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extern struct smp_operations sirfsoc_smp_ops;
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extern void sirfsoc_secondary_startup(void);
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extern void sirfsoc_cpu_die(unsigned int cpu);
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extern void __init sirfsoc_of_irq_init(void);
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extern void __init sirfsoc_of_clk_init(void);
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@ -26,6 +31,12 @@ static inline void sirfsoc_map_lluart(void) {}
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extern void __init sirfsoc_map_lluart(void);
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#endif
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#ifndef CONFIG_SMP
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static inline void sirfsoc_map_scu(void) {}
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#else
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extern void sirfsoc_map_scu(void);
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#endif
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#ifdef CONFIG_SUSPEND
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extern int sirfsoc_pm_init(void);
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#else
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@ -0,0 +1,79 @@
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/*
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* Entry of the second core for CSR Marco dual-core SMP SoCs
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*
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* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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__INIT
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/*
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* Cold boot and hardware reset show different behaviour,
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* system will be always panic if we warm-reset the board
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* Here we invalidate L1 of CPU1 to make sure there isn't
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* uninitialized data written into memory later
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*/
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ENTRY(v7_invalidate_l1)
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 2, r0, c0, c0, 0
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mrc p15, 1, r0, c0, c0, 0
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ldr r1, =0x7fff
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and r2, r1, r0, lsr #13
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ldr r1, =0x3ff
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and r3, r1, r0, lsr #3 @ NumWays - 1
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add r2, r2, #1 @ NumSets
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and r0, r0, #0x7
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add r0, r0, #4 @ SetShift
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clz r1, r3 @ WayShift
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add r4, r3, #1 @ NumWays
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1: sub r2, r2, #1 @ NumSets--
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mov r3, r4 @ Temp = NumWays
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2: subs r3, r3, #1 @ Temp--
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mov r5, r3, lsl r1
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mov r6, r2, lsl r0
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orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
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mcr p15, 0, r5, c7, c6, 2
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bgt 2b
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cmp r2, #0
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bgt 1b
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dsb
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isb
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mov pc, lr
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ENDPROC(v7_invalidate_l1)
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/*
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* SIRFSOC specific entry point for secondary CPUs. This provides
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* a "holding pen" into which all secondary cores are held until we're
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* ready for them to initialise.
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*/
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ENTRY(sirfsoc_secondary_startup)
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bl v7_invalidate_l1
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mrc p15, 0, r0, c0, c0, 5
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and r0, r0, #15
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adr r4, 1f
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ldmia r4, {r5, r6}
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sub r4, r4, r5
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add r6, r6, r4
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pen: ldr r7, [r6]
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cmp r7, r0
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bne pen
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/*
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* we've been released from the holding pen: secondary_stack
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* should now contain the SVC stack for this core
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*/
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b secondary_startup
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ENDPROC(sirfsoc_secondary_startup)
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.align
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1: .long .
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.long pen_release
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@ -0,0 +1,41 @@
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/*
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* CPU hotplug support for CSR Marco dual-core SMP SoCs
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*
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* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/smp.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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static inline void platform_do_lowpower(unsigned int cpu)
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{
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flush_cache_all();
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/* we put the platform to just WFI */
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for (;;) {
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__asm__ __volatile__("dsb\n\t" "wfi\n\t"
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: : : "memory");
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if (pen_release == cpu_logical_map(cpu)) {
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/*
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* OK, proper wakeup, we're done
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*/
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break;
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}
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}
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}
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/*
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* platform-specific code to shutdown a CPU
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*
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* Called with IRQs disabled
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*/
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void sirfsoc_cpu_die(unsigned int cpu)
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{
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platform_do_lowpower(cpu);
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}
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@ -0,0 +1,163 @@
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/*
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* plat smp support for CSR Marco dual-core SMP SoCs
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*
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* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <asm/page.h>
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#include <asm/mach/map.h>
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#include <asm/smp_plat.h>
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#include <asm/smp_scu.h>
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#include <asm/cacheflush.h>
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#include <asm/cputype.h>
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#include <asm/hardware/gic.h>
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#include <mach/map.h>
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#include "common.h"
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static void __iomem *scu_base;
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static void __iomem *rsc_base;
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static DEFINE_SPINLOCK(boot_lock);
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static struct map_desc scu_io_desc __initdata = {
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.length = SZ_4K,
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.type = MT_DEVICE,
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};
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void __init sirfsoc_map_scu(void)
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{
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unsigned long base;
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/* Get SCU base */
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asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
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scu_io_desc.virtual = SIRFSOC_VA(base);
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scu_io_desc.pfn = __phys_to_pfn(base);
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iotable_init(&scu_io_desc, 1);
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scu_base = (void __iomem *)SIRFSOC_VA(base);
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}
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static void __cpuinit sirfsoc_secondary_init(unsigned int cpu)
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{
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_secondary_init(0);
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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*/
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pen_release = -1;
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smp_wmb();
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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static struct of_device_id rsc_ids[] = {
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{ .compatible = "sirf,marco-rsc" },
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{},
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};
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static int __cpuinit sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long timeout;
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struct device_node *np;
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np = of_find_matching_node(NULL, rsc_ids);
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if (!np)
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return -ENODEV;
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rsc_base = of_iomap(np, 0);
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if (!rsc_base)
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return -ENOMEM;
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/*
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* write the address of secondary startup into the sram register
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* at offset 0x2C, then write the magic number 0x3CAF5D62 to the
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* RSC register at offset 0x28, which is what boot rom code is
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* waiting for. This would wake up the secondary core from WFE
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*/
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#define SIRFSOC_CPU1_JUMPADDR_OFFSET 0x2C
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__raw_writel(virt_to_phys(sirfsoc_secondary_startup),
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rsc_base + SIRFSOC_CPU1_JUMPADDR_OFFSET);
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#define SIRFSOC_CPU1_WAKEMAGIC_OFFSET 0x28
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__raw_writel(0x3CAF5D62,
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rsc_base + SIRFSOC_CPU1_WAKEMAGIC_OFFSET);
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/* make sure write buffer is drained */
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mb();
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spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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* the holding pen - release it, then wait for it to flag
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* that it has been released by resetting pen_release.
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*
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* Note that "pen_release" is the hardware CPU ID, whereas
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* "cpu" is Linux's internal ID.
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*/
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pen_release = cpu_logical_map(cpu);
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__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
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outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
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/*
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* Send the secondary CPU SEV, thereby causing the boot monitor to read
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* the JUMPADDR and WAKEMAGIC, and branch to the address found there.
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*/
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dsb_sev();
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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smp_rmb();
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if (pen_release == -1)
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break;
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udelay(10);
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}
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/*
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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static void __init sirfsoc_smp_init_cpus(void)
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{
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set_smp_cross_call(gic_raise_softirq);
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}
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static void __init sirfsoc_smp_prepare_cpus(unsigned int max_cpus)
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{
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scu_enable(scu_base);
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}
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struct smp_operations sirfsoc_smp_ops __initdata = {
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.smp_init_cpus = sirfsoc_smp_init_cpus,
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.smp_prepare_cpus = sirfsoc_smp_prepare_cpus,
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.smp_secondary_init = sirfsoc_secondary_init,
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.smp_boot_secondary = sirfsoc_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = sirfsoc_cpu_die,
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#endif
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};
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@ -0,0 +1,316 @@
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/*
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* System timer for CSR SiRFprimaII
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*
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/bitops.h>
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#include <linux/irq.h>
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#include <linux/clk.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <asm/sched_clock.h>
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#include <asm/localtimer.h>
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#include <asm/mach/time.h>
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#include "common.h"
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#define SIRFSOC_TIMER_32COUNTER_0_CTRL 0x0000
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#define SIRFSOC_TIMER_32COUNTER_1_CTRL 0x0004
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#define SIRFSOC_TIMER_MATCH_0 0x0018
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#define SIRFSOC_TIMER_MATCH_1 0x001c
|
||||
#define SIRFSOC_TIMER_COUNTER_0 0x0048
|
||||
#define SIRFSOC_TIMER_COUNTER_1 0x004c
|
||||
#define SIRFSOC_TIMER_INTR_STATUS 0x0060
|
||||
#define SIRFSOC_TIMER_WATCHDOG_EN 0x0064
|
||||
#define SIRFSOC_TIMER_64COUNTER_CTRL 0x0068
|
||||
#define SIRFSOC_TIMER_64COUNTER_LO 0x006c
|
||||
#define SIRFSOC_TIMER_64COUNTER_HI 0x0070
|
||||
#define SIRFSOC_TIMER_64COUNTER_LOAD_LO 0x0074
|
||||
#define SIRFSOC_TIMER_64COUNTER_LOAD_HI 0x0078
|
||||
#define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO 0x007c
|
||||
#define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI 0x0080
|
||||
|
||||
#define SIRFSOC_TIMER_REG_CNT 6
|
||||
|
||||
static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
|
||||
SIRFSOC_TIMER_WATCHDOG_EN,
|
||||
SIRFSOC_TIMER_32COUNTER_0_CTRL,
|
||||
SIRFSOC_TIMER_32COUNTER_1_CTRL,
|
||||
SIRFSOC_TIMER_64COUNTER_CTRL,
|
||||
SIRFSOC_TIMER_64COUNTER_RLATCHED_LO,
|
||||
SIRFSOC_TIMER_64COUNTER_RLATCHED_HI,
|
||||
};
|
||||
|
||||
static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
|
||||
|
||||
static void __iomem *sirfsoc_timer_base;
|
||||
static void __init sirfsoc_of_timer_map(void);
|
||||
|
||||
/* disable count and interrupt */
|
||||
static inline void sirfsoc_timer_count_disable(int idx)
|
||||
{
|
||||
writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7,
|
||||
sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
|
||||
}
|
||||
|
||||
/* enable count and interrupt */
|
||||
static inline void sirfsoc_timer_count_enable(int idx)
|
||||
{
|
||||
writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x7,
|
||||
sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
|
||||
}
|
||||
|
||||
/* timer interrupt handler */
|
||||
static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct clock_event_device *ce = dev_id;
|
||||
int cpu = smp_processor_id();
|
||||
|
||||
/* clear timer interrupt */
|
||||
writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
|
||||
|
||||
if (ce->mode == CLOCK_EVT_MODE_ONESHOT)
|
||||
sirfsoc_timer_count_disable(cpu);
|
||||
|
||||
ce->event_handler(ce);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/* read 64-bit timer counter */
|
||||
static cycle_t sirfsoc_timer_read(struct clocksource *cs)
|
||||
{
|
||||
u64 cycles;
|
||||
|
||||
writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
|
||||
BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
|
||||
|
||||
cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI);
|
||||
cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO);
|
||||
|
||||
return cycles;
|
||||
}
|
||||
|
||||
static int sirfsoc_timer_set_next_event(unsigned long delta,
|
||||
struct clock_event_device *ce)
|
||||
{
|
||||
int cpu = smp_processor_id();
|
||||
|
||||
writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +
|
||||
4 * cpu);
|
||||
writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +
|
||||
4 * cpu);
|
||||
|
||||
/* enable the tick */
|
||||
sirfsoc_timer_count_enable(cpu);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
|
||||
struct clock_event_device *ce)
|
||||
{
|
||||
switch (mode) {
|
||||
case CLOCK_EVT_MODE_ONESHOT:
|
||||
/* enable in set_next_event */
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
sirfsoc_timer_count_disable(smp_processor_id());
|
||||
}
|
||||
|
||||
static void sirfsoc_clocksource_suspend(struct clocksource *cs)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
|
||||
sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
|
||||
}
|
||||
|
||||
static void sirfsoc_clocksource_resume(struct clocksource *cs)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
|
||||
writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
|
||||
|
||||
writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
|
||||
sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
|
||||
writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
|
||||
sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
|
||||
|
||||
writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
|
||||
BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
|
||||
}
|
||||
|
||||
static struct clock_event_device sirfsoc_clockevent = {
|
||||
.name = "sirfsoc_clockevent",
|
||||
.rating = 200,
|
||||
.features = CLOCK_EVT_FEAT_ONESHOT,
|
||||
.set_mode = sirfsoc_timer_set_mode,
|
||||
.set_next_event = sirfsoc_timer_set_next_event,
|
||||
};
|
||||
|
||||
static struct clocksource sirfsoc_clocksource = {
|
||||
.name = "sirfsoc_clocksource",
|
||||
.rating = 200,
|
||||
.mask = CLOCKSOURCE_MASK(64),
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
.read = sirfsoc_timer_read,
|
||||
.suspend = sirfsoc_clocksource_suspend,
|
||||
.resume = sirfsoc_clocksource_resume,
|
||||
};
|
||||
|
||||
static struct irqaction sirfsoc_timer_irq = {
|
||||
.name = "sirfsoc_timer0",
|
||||
.flags = IRQF_TIMER | IRQF_NOBALANCING,
|
||||
.handler = sirfsoc_timer_interrupt,
|
||||
.dev_id = &sirfsoc_clockevent,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_LOCAL_TIMERS
|
||||
|
||||
static struct irqaction sirfsoc_timer1_irq = {
|
||||
.name = "sirfsoc_timer1",
|
||||
.flags = IRQF_TIMER | IRQF_NOBALANCING,
|
||||
.handler = sirfsoc_timer_interrupt,
|
||||
};
|
||||
|
||||
static int __cpuinit sirfsoc_local_timer_setup(struct clock_event_device *ce)
|
||||
{
|
||||
/* Use existing clock_event for cpu 0 */
|
||||
if (!smp_processor_id())
|
||||
return 0;
|
||||
|
||||
ce->irq = sirfsoc_timer1_irq.irq;
|
||||
ce->name = "local_timer";
|
||||
ce->features = sirfsoc_clockevent.features;
|
||||
ce->rating = sirfsoc_clockevent.rating;
|
||||
ce->set_mode = sirfsoc_timer_set_mode;
|
||||
ce->set_next_event = sirfsoc_timer_set_next_event;
|
||||
ce->shift = sirfsoc_clockevent.shift;
|
||||
ce->mult = sirfsoc_clockevent.mult;
|
||||
ce->max_delta_ns = sirfsoc_clockevent.max_delta_ns;
|
||||
ce->min_delta_ns = sirfsoc_clockevent.min_delta_ns;
|
||||
|
||||
sirfsoc_timer1_irq.dev_id = ce;
|
||||
BUG_ON(setup_irq(ce->irq, &sirfsoc_timer1_irq));
|
||||
irq_set_affinity(sirfsoc_timer1_irq.irq, cpumask_of(1));
|
||||
|
||||
clockevents_register_device(ce);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sirfsoc_local_timer_stop(struct clock_event_device *ce)
|
||||
{
|
||||
sirfsoc_timer_count_disable(1);
|
||||
|
||||
remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq);
|
||||
}
|
||||
|
||||
static struct local_timer_ops sirfsoc_local_timer_ops __cpuinitdata = {
|
||||
.setup = sirfsoc_local_timer_setup,
|
||||
.stop = sirfsoc_local_timer_stop,
|
||||
};
|
||||
#endif /* CONFIG_LOCAL_TIMERS */
|
||||
|
||||
static void __init sirfsoc_clockevent_init(void)
|
||||
{
|
||||
clockevents_calc_mult_shift(&sirfsoc_clockevent, CLOCK_TICK_RATE, 60);
|
||||
|
||||
sirfsoc_clockevent.max_delta_ns =
|
||||
clockevent_delta2ns(-2, &sirfsoc_clockevent);
|
||||
sirfsoc_clockevent.min_delta_ns =
|
||||
clockevent_delta2ns(2, &sirfsoc_clockevent);
|
||||
|
||||
sirfsoc_clockevent.cpumask = cpumask_of(0);
|
||||
clockevents_register_device(&sirfsoc_clockevent);
|
||||
#ifdef CONFIG_LOCAL_TIMERS
|
||||
local_timer_register(&sirfsoc_local_timer_ops);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* initialize the kernel jiffy timer source */
|
||||
void __init sirfsoc_marco_timer_init(void)
|
||||
{
|
||||
unsigned long rate;
|
||||
u32 timer_div;
|
||||
struct clk *clk;
|
||||
|
||||
/* initialize clocking early, we want to set the OS timer */
|
||||
sirfsoc_of_clk_init();
|
||||
|
||||
/* timer's input clock is io clock */
|
||||
clk = clk_get_sys("io", NULL);
|
||||
|
||||
BUG_ON(IS_ERR(clk));
|
||||
rate = clk_get_rate(clk);
|
||||
|
||||
BUG_ON(rate < CLOCK_TICK_RATE);
|
||||
BUG_ON(rate % CLOCK_TICK_RATE);
|
||||
|
||||
sirfsoc_of_timer_map();
|
||||
|
||||
/* Initialize the timer dividers */
|
||||
timer_div = rate / CLOCK_TICK_RATE - 1;
|
||||
writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
|
||||
writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
|
||||
writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);
|
||||
|
||||
/* Initialize timer counters to 0 */
|
||||
writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
|
||||
writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
|
||||
writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
|
||||
BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
|
||||
writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
|
||||
writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1);
|
||||
|
||||
/* Clear all interrupts */
|
||||
writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
|
||||
|
||||
BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE));
|
||||
|
||||
BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq));
|
||||
|
||||
sirfsoc_clockevent_init();
|
||||
}
|
||||
|
||||
static struct of_device_id timer_ids[] = {
|
||||
{ .compatible = "sirf,marco-tick" },
|
||||
{},
|
||||
};
|
||||
|
||||
static void __init sirfsoc_of_timer_map(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
||||
np = of_find_matching_node(NULL, timer_ids);
|
||||
if (!np)
|
||||
return;
|
||||
sirfsoc_timer_base = of_iomap(np, 0);
|
||||
if (!sirfsoc_timer_base)
|
||||
panic("unable to map timer cpu registers\n");
|
||||
|
||||
sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
|
||||
if (!sirfsoc_timer_irq.irq)
|
||||
panic("No irq passed for timer0 via DT\n");
|
||||
|
||||
#ifdef CONFIG_LOCAL_TIMERS
|
||||
sirfsoc_timer1_irq.irq = irq_of_parse_and_map(np, 1);
|
||||
if (!sirfsoc_timer1_irq.irq)
|
||||
panic("No irq passed for timer1 via DT\n");
|
||||
#endif
|
||||
|
||||
of_node_put(np);
|
||||
}
|
||||
Loading…
Reference in New Issue