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omap clock changes via Paul Walmsley <paul@pwsan.com>: 

Some miscellaneous OMAP2+ clock fixes, mostly related to the recent
 common clock framework conversion.
 
 Basic test logs are available here:
 
     http://www.pwsan.com/omap/testlogs/clock_devel_a_3.9/20130208120108/
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Merge tag 'omap-for-v3.9/clock-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into late/omap

From Tony Lindgren:
omap clock changes via Paul Walmsley <paul@pwsan.com>:

Some miscellaneous OMAP2+ clock fixes, mostly related to the recent
common clock framework conversion.

Basic test logs are available here:

    http://www.pwsan.com/omap/testlogs/clock_devel_a_3.9/20130208120108/

* tag 'omap-for-v3.9/clock-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP4: clock data: Add missing clkdm association for dpll_usb
  ARM: OMAP AM33XX: clock data: SET_RATE_PARENT in lcd path
  ARM: OMAP2+: clock data: add DEFINE_STRUCT_CLK_FLAGS helper
  ARM: OMAP2+: dpll: am335x - avoid freqsel
  omap3isp: Set cam_mclk rate directly
  ARM: OMAP3: clock: Back-propagate rate change from cam_mclk to dpll4_m5
This commit is contained in:
Olof Johansson 2013-02-12 15:33:15 -08:00
parent 379095930b 14211e2fd2
commit 488c77c961
7 changed files with 46 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm/mach-omap2/cclock33xx_data.c
View File

@ -284,9 +284,10 @@ DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
* TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
* and ALT_CLK1/2)
*/
DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck, 0x0,
AM33XX_CM_DIV_M2_DPLL_DISP, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck,
CLK_SET_RATE_PARENT, AM33XX_CM_DIV_M2_DPLL_DISP,
AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
CLK_DIVIDER_ONE_BASED, NULL);
/* DPLL_PER */
static struct dpll_data dpll_per_dd = {
@ -723,7 +724,8 @@ static struct clk_hw_omap lcd_gclk_hw = {
.clksel_mask = AM33XX_CLKSEL_0_1_MASK,
};
DEFINE_STRUCT_CLK(lcd_gclk, lcd_ck_parents, gpio_fck_ops);
DEFINE_STRUCT_CLK_FLAGS(lcd_gclk, lcd_ck_parents,
gpio_fck_ops, CLK_SET_RATE_PARENT);
DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2);

10
arch/arm/mach-omap2/cclock3xxx_data.c
View File

@ -426,6 +426,7 @@ static struct clk dpll4_m5x2_ck_3630 = {
.parent_names = dpll4_m5x2_ck_parent_names,
.num_parents = ARRAY_SIZE(dpll4_m5x2_ck_parent_names),
.ops = &dpll4_m5x2_ck_3630_ops,
.flags = CLK_SET_RATE_PARENT,
};
static struct clk cam_mclk;
@ -443,7 +444,14 @@ static struct clk_hw_omap cam_mclk_hw = {
.clkdm_name = "cam_clkdm",
};
DEFINE_STRUCT_CLK(cam_mclk, cam_mclk_parent_names, aes2_ick_ops);
static struct clk cam_mclk = {
.name = "cam_mclk",
.hw = &cam_mclk_hw.hw,
.parent_names = cam_mclk_parent_names,
.num_parents = ARRAY_SIZE(cam_mclk_parent_names),
.ops = &aes2_ick_ops,
.flags = CLK_SET_RATE_PARENT,
};
static const struct clksel_rate clkout2_src_core_rates[] = {
{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },

13
arch/arm/mach-omap2/cclock44xx_data.c
View File

@ -605,15 +605,26 @@ static const char *dpll_usb_ck_parents[] = {
static struct clk dpll_usb_ck;
static const struct clk_ops dpll_usb_ck_ops = {
.enable = &omap3_noncore_dpll_enable,
.disable = &omap3_noncore_dpll_disable,
.recalc_rate = &omap3_dpll_recalc,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
.get_parent = &omap2_init_dpll_parent,
.init = &omap2_init_clk_clkdm,
};
static struct clk_hw_omap dpll_usb_ck_hw = {
.hw = {
.clk = &dpll_usb_ck,
},
.dpll_data = &dpll_usb_dd,
.clkdm_name = "l3_init_clkdm",
.ops = &clkhwops_omap3_dpll,
};
DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_ck_ops);
DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_usb_ck_ops);
static const char *dpll_usb_clkdcoldo_ck_parents[] = {
"dpll_usb_ck",

11
arch/arm/mach-omap2/clock.h
View File

@ -65,6 +65,17 @@ struct clockdomain;
.ops = &_clkops_name, \
};
#define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name, \
_clkops_name, _flags) \
static struct clk _name = { \
.name = #_name, \
.hw = &_name##_hw.hw, \
.parent_names = _parent_array_name, \
.num_parents = ARRAY_SIZE(_parent_array_name), \
.ops = &_clkops_name, \
.flags = _flags, \
};
#define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \
static struct clk_hw_omap _name##_hw = { \
.hw = { \

5
arch/arm/mach-omap2/dpll3xxx.c
View File

@ -500,8 +500,9 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
if (dd->last_rounded_rate == 0)
return -EINVAL;
/* No freqsel on OMAP4 and OMAP3630 */
if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
/* No freqsel on AM335x, OMAP4 and OMAP3630 */
if (!soc_is_am33xx() && !cpu_is_omap44xx() &&
!cpu_is_omap3630()) {
freqsel = _omap3_dpll_compute_freqsel(clk,
dd->last_rounded_n);
WARN_ON(!freqsel);

18
drivers/media/platform/omap3isp/isp.c
View File

@ -1338,28 +1338,15 @@ static int isp_enable_clocks(struct isp_device *isp)
{
int r;
unsigned long rate;
int divisor;
/*
* cam_mclk clock chain:
* dpll4 -> dpll4_m5 -> dpll4_m5x2 -> cam_mclk
*
* In OMAP3630 dpll4_m5x2 != 2 x dpll4_m5 but both are
* set to the same value. Hence the rate set for dpll4_m5
* has to be twice of what is set on OMAP3430 to get
* the required value for cam_mclk
*/
divisor = isp->revision == ISP_REVISION_15_0 ? 1 : 2;
r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_ICK]);
if (r) {
dev_err(isp->dev, "failed to enable cam_ick clock\n");
goto out_clk_enable_ick;
}
r = clk_set_rate(isp->clock[ISP_CLK_DPLL4_M5_CK],
CM_CAM_MCLK_HZ/divisor);
r = clk_set_rate(isp->clock[ISP_CLK_CAM_MCLK], CM_CAM_MCLK_HZ);
if (r) {
dev_err(isp->dev, "clk_set_rate for dpll4_m5_ck failed\n");
dev_err(isp->dev, "clk_set_rate for cam_mclk failed\n");
goto out_clk_enable_mclk;
}
r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_MCLK]);
@ -1401,7 +1388,6 @@ static void isp_disable_clocks(struct isp_device *isp)
static const char *isp_clocks[] = {
"cam_ick",
"cam_mclk",
"dpll4_m5_ck",
"csi2_96m_fck",
"l3_ick",
};

8
drivers/media/platform/omap3isp/isp.h
View File

@ -147,7 +147,6 @@ struct isp_platform_callback {
* @ref_count: Reference count for handling multiple ISP requests.
* @cam_ick: Pointer to camera interface clock structure.
* @cam_mclk: Pointer to camera functional clock structure.
* @dpll4_m5_ck: Pointer to DPLL4 M5 clock structure.
* @csi2_fck: Pointer to camera CSI2 complexIO clock structure.
* @l3_ick: Pointer to OMAP3 L3 bus interface clock.
* @irq: Currently attached ISP ISR callbacks information structure.
@ -189,10 +188,9 @@ struct isp_device {
u32 xclk_divisor[2]; /* Two clocks, a and b. */
#define ISP_CLK_CAM_ICK 0
#define ISP_CLK_CAM_MCLK 1
#define ISP_CLK_DPLL4_M5_CK 2
#define ISP_CLK_CSI2_FCK 3
#define ISP_CLK_L3_ICK 4
struct clk *clock[5];
#define ISP_CLK_CSI2_FCK 2
#define ISP_CLK_L3_ICK 3
struct clk *clock[4];
/* ISP modules */
struct ispstat isp_af;