AArch64 kernel fixes:
- correct argument type (pgprot_t) when calling __ioremap() - PCI_IOBASE virtual address change - use architected event for CPU cycle counter - fix ELF core dumping - select CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION - missing completion for secondary CPU boot - booting on systems with all memory beyond 4GB -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) iQIcBAABAgAGBQJQnTIQAAoJEGvWsS0AyF7xZEgP+wf6dEFzL+bt3sccyzjB0THu ir5y99EHN2vDQ74tiQK+SbSDV8zqXs4vgXK+osxz3ooQdU+Ep8JMUSGjRg8j72yj XcQBOxW5Hu79ArYJPaD8KMARBnk0QbnoRZyLGHXzVQgsLli+xpXoigmL2IlhElOh h+A5jpDfaoGCO9e6xVXp9s9GJ/Ho8uoXuIAeWvELP1kvixTT+c4oWn+iD+N9FA/C kiVFMZOHrJ6478se0uqqEktPeszF0vXTW84aTscA5xPA7R145tMJYPRQGhb2+QL1 mC43Ya9KtONbr0REoQFca0w4bqSNRCv9fLtV/xizUI6mZImSF9ZQ+hAaqbBPrMZ+ sx3ohZ8fri4rS5leGAd/bN88Xxue7GNHxo4auNGPxrbMzb7opyNL3bhawhfNPlag ZhCpXQDVkGYuHIgi4Z7VEVQuwg+l57kK2HdXlwlEDVixQHJ0YFAeI2A7goXJofxQ /4mdcoWQpt75GlON4V0wGk9rACp/rEBbpu35Vv6FfBDa3fSlQAVvkBG/HOyp/OFm Gyw6aY4Qk6psIIfmQVXQVVd5svkhkKRBpHHRPdfArZdny2UMOl9NG15zZGqr3nBX ELGndcc8POUaKw9ia5QGP1QmfOrzznZ68jDUz58rwQiZpzMveS9C381kHnkIRunu gDAVjjZCFwHuGzF1uV7S =g5mZ -----END PGP SIGNATURE----- Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64 Pull arm64 fixes from Catalin Marinas: - correct argument type (pgprot_t) when calling __ioremap() - PCI_IOBASE virtual address change - use architected event for CPU cycle counter - fix ELF core dumping - select CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION - missing completion for secondary CPU boot - booting on systems with all memory beyond 4GB * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64: arm64: mm: fix booting on systems with no memory below 4GB arm64: smp: add missing completion for secondary boot arm64: compat: select CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION arm64: elf: fix core dumping definitions for GP and FP registers arm64: perf: use architected event for CPU cycle counter arm64: Move PCI_IOBASE closer to MODULES_VADDR arm64: Use pgprot_t as the last argument when invoking __ioremap()
This commit is contained in:
Linus Torvalds
commit
487bda54d7
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@ -27,17 +27,17 @@ Start End Size Use
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-----------------------------------------------------------------------
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0000000000000000 0000007fffffffff 512GB user
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ffffff8000000000 ffffffbbfffcffff ~240GB vmalloc
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ffffff8000000000 ffffffbbfffeffff ~240GB vmalloc
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ffffffbbfffd0000 ffffffbcfffdffff 64KB [guard page]
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ffffffbbfffe0000 ffffffbcfffeffff 64KB PCI I/O space
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ffffffbbffff0000 ffffffbcffffffff 64KB [guard page]
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ffffffbbffff0000 ffffffbbffffffff 64KB [guard page]
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ffffffbc00000000 ffffffbdffffffff 8GB vmemmap
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ffffffbe00000000 ffffffbffbffffff ~8GB [guard, future vmmemap]
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ffffffbe00000000 ffffffbffbbfffff ~8GB [guard, future vmmemap]
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ffffffbffbe00000 ffffffbffbe0ffff 64KB PCI I/O space
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ffffffbbffff0000 ffffffbcffffffff ~2MB [guard]
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ffffffbffc000000 ffffffbfffffffff 64MB modules
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@ -1,6 +1,7 @@
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config ARM64
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def_bool y
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select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
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select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
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select GENERIC_CLOCKEVENTS
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select GENERIC_HARDIRQS_NO_DEPRECATED
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select GENERIC_IOMAP
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@ -25,12 +25,10 @@
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#include <asm/user.h>
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typedef unsigned long elf_greg_t;
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typedef unsigned long elf_freg_t[3];
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#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
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typedef elf_greg_t elf_gregset_t[ELF_NGREG];
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typedef struct user_fp elf_fpregset_t;
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typedef struct user_fpsimd_state elf_fpregset_t;
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#define EM_AARCH64 183
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@ -87,7 +85,6 @@ typedef struct user_fp elf_fpregset_t;
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#define R_AARCH64_MOVW_PREL_G2_NC 292
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#define R_AARCH64_MOVW_PREL_G3 293
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/*
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* These are used to set parameters in the core dumps.
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*/
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@ -25,9 +25,8 @@
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* - FPSR and FPCR
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* - 32 128-bit data registers
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*
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* Note that user_fp forms a prefix of this structure, which is relied
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* upon in the ptrace FP/SIMD accessors. struct user_fpsimd_state must
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* form a prefix of struct fpsimd_state.
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* Note that user_fpsimd forms a prefix of this structure, which is
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* relied upon in the ptrace FP/SIMD accessors.
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*/
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struct fpsimd_state {
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union {
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@ -114,7 +114,7 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
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* I/O port access primitives.
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*/
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#define IO_SPACE_LIMIT 0xffff
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#define PCI_IOBASE ((void __iomem *)0xffffffbbfffe0000UL)
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#define PCI_IOBASE ((void __iomem *)(MODULES_VADDR - SZ_2M))
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static inline u8 inb(unsigned long addr)
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{
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@ -225,9 +225,9 @@ extern void __iounmap(volatile void __iomem *addr);
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#define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_XN | PTE_ATTRINDX(MT_DEVICE_nGnRE))
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#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL_NC))
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#define ioremap(addr, size) __ioremap((addr), (size), PROT_DEVICE_nGnRE)
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#define ioremap_nocache(addr, size) __ioremap((addr), (size), PROT_DEVICE_nGnRE)
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#define ioremap_wc(addr, size) __ioremap((addr), (size), PROT_NORMAL_NC)
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#define ioremap(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
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#define ioremap_nocache(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
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#define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
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#define iounmap __iounmap
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#define ARCH_HAS_IOREMAP_WC
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@ -43,6 +43,8 @@
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#else
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#define STACK_TOP STACK_TOP_MAX
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#endif /* CONFIG_COMPAT */
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#define ARCH_LOW_ADDRESS_LIMIT PHYS_MASK
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#endif /* __KERNEL__ */
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struct debug_info {
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@ -14,7 +14,6 @@
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifdef CONFIG_COMPAT
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#define __ARCH_WANT_COMPAT_IPC_PARSE_VERSION
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#define __ARCH_WANT_COMPAT_STAT64
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#define __ARCH_WANT_SYS_GETHOSTNAME
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#define __ARCH_WANT_SYS_PAUSE
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@ -613,17 +613,11 @@ enum armv8_pmuv3_perf_types {
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ARMV8_PMUV3_PERFCTR_BUS_ACCESS = 0x19,
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ARMV8_PMUV3_PERFCTR_MEM_ERROR = 0x1A,
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ARMV8_PMUV3_PERFCTR_BUS_CYCLES = 0x1D,
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/*
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* This isn't an architected event.
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* We detect this event number and use the cycle counter instead.
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*/
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ARMV8_PMUV3_PERFCTR_CPU_CYCLES = 0xFF,
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};
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/* PMUv3 HW events mapping. */
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static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
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[PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
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[PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES,
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[PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED,
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[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
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[PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
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@ -1106,7 +1100,7 @@ static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
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unsigned long evtype = event->config_base & ARMV8_EVTYPE_EVENT;
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/* Always place a cycle counter into the cycle counter. */
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if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) {
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if (evtype == ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES) {
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if (test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
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return -EAGAIN;
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@ -309,24 +309,6 @@ struct task_struct *__switch_to(struct task_struct *prev,
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return last;
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}
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/*
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* Fill in the task's elfregs structure for a core dump.
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*/
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int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs)
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{
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elf_core_copy_regs(elfregs, task_pt_regs(t));
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return 1;
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}
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/*
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* fill in the fpe structure for a core dump...
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*/
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int dump_fpu (struct pt_regs *regs, struct user_fp *fp)
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{
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return 0;
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}
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EXPORT_SYMBOL(dump_fpu);
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/*
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* Shuffle the argument into the correct register before calling the
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* thread function. x1 is the thread argument, x2 is the pointer to
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@ -211,8 +211,7 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
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* before we continue.
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*/
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set_cpu_online(cpu, true);
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while (!cpu_active(cpu))
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cpu_relax();
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complete(&cpu_running);
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/*
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* OK, it's off to the idle thread for us
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@ -80,7 +80,7 @@ static void __init zone_sizes_init(unsigned long min, unsigned long max)
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#ifdef CONFIG_ZONE_DMA32
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/* 4GB maximum for 32-bit only capable devices */
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max_dma32 = min(max, MAX_DMA32_PFN);
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zone_size[ZONE_DMA32] = max_dma32 - min;
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zone_size[ZONE_DMA32] = max(min, max_dma32) - min;
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#endif
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zone_size[ZONE_NORMAL] = max - max_dma32;
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