cxl/core: Split decoder setup into alloc + add
The kbuild robot reports:
drivers/cxl/core/bus.c:516:1: warning: stack frame size (1032) exceeds
limit (1024) in function 'devm_cxl_add_decoder'
It is also the case the devm_cxl_add_decoder() is unwieldy to use for
all the different decoder types. Fix the stack usage by splitting the
creation into alloc and add steps. This also allows for context
specific construction before adding.
With the split the caller is responsible for registering a devm callback
to trigger device_unregister() for the decoder rather than it being
implicit in the decoder registration. I.e. the routine that calls alloc
is responsible for calling put_device() if the "add" operation fails.
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Nathan Chancellor <nathan@kernel.org>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Ben Widawsky <ben.widawsky@intel.com>
Link: https://lore.kernel.org/r/163225205828.3038145.6831131648369404859.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Dan Williams
parent
7d3eb23c4c
commit
48667f6761
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@ -82,7 +82,6 @@ static void cxl_add_cfmws_decoders(struct device *dev,
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struct cxl_decoder *cxld;
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acpi_size len, cur = 0;
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void *cedt_subtable;
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unsigned long flags;
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int rc;
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len = acpi_cedt->length - sizeof(*acpi_cedt);
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@ -119,24 +118,36 @@ static void cxl_add_cfmws_decoders(struct device *dev,
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for (i = 0; i < CFMWS_INTERLEAVE_WAYS(cfmws); i++)
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target_map[i] = cfmws->interleave_targets[i];
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flags = cfmws_to_decoder_flags(cfmws->restrictions);
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cxld = devm_cxl_add_decoder(dev, root_port,
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CFMWS_INTERLEAVE_WAYS(cfmws),
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cfmws->base_hpa, cfmws->window_size,
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CFMWS_INTERLEAVE_WAYS(cfmws),
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CFMWS_INTERLEAVE_GRANULARITY(cfmws),
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CXL_DECODER_EXPANDER,
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flags, target_map);
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cxld = cxl_decoder_alloc(root_port,
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CFMWS_INTERLEAVE_WAYS(cfmws));
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if (IS_ERR(cxld))
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goto next;
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if (IS_ERR(cxld)) {
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cxld->flags = cfmws_to_decoder_flags(cfmws->restrictions);
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cxld->target_type = CXL_DECODER_EXPANDER;
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cxld->range = (struct range) {
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.start = cfmws->base_hpa,
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.end = cfmws->base_hpa + cfmws->window_size - 1,
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};
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cxld->interleave_ways = CFMWS_INTERLEAVE_WAYS(cfmws);
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cxld->interleave_granularity =
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CFMWS_INTERLEAVE_GRANULARITY(cfmws);
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rc = cxl_decoder_add(cxld, target_map);
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if (rc)
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put_device(&cxld->dev);
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else
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rc = cxl_decoder_autoremove(dev, cxld);
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if (rc) {
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dev_err(dev, "Failed to add decoder for %#llx-%#llx\n",
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cfmws->base_hpa, cfmws->base_hpa +
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cfmws->window_size - 1);
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} else {
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dev_dbg(dev, "add: %s range %#llx-%#llx\n",
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dev_name(&cxld->dev), cfmws->base_hpa,
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cfmws->base_hpa + cfmws->window_size - 1);
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goto next;
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}
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dev_dbg(dev, "add: %s range %#llx-%#llx\n",
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dev_name(&cxld->dev), cfmws->base_hpa,
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cfmws->base_hpa + cfmws->window_size - 1);
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next:
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cur += c->length;
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}
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}
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@ -266,6 +277,7 @@ static int add_host_bridge_uport(struct device *match, void *arg)
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struct acpi_device *bridge = to_cxl_host_bridge(host, match);
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struct acpi_pci_root *pci_root;
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struct cxl_walk_context ctx;
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int single_port_map[1], rc;
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struct cxl_decoder *cxld;
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struct cxl_dport *dport;
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struct cxl_port *port;
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@ -301,22 +313,46 @@ static int add_host_bridge_uport(struct device *match, void *arg)
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return -ENODEV;
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if (ctx.error)
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return ctx.error;
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if (ctx.count > 1)
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return 0;
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/* TODO: Scan CHBCR for HDM Decoder resources */
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/*
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* In the single-port host-bridge case there are no HDM decoders
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* in the CHBCR and a 1:1 passthrough decode is implied.
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* Per the CXL specification (8.2.5.12 CXL HDM Decoder Capability
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* Structure) single ported host-bridges need not publish a decoder
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* capability when a passthrough decode can be assumed, i.e. all
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* transactions that the uport sees are claimed and passed to the single
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* dport. Disable the range until the first CXL region is enumerated /
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* activated.
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*/
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if (ctx.count == 1) {
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cxld = devm_cxl_add_passthrough_decoder(host, port);
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if (IS_ERR(cxld))
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return PTR_ERR(cxld);
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cxld = cxl_decoder_alloc(port, 1);
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if (IS_ERR(cxld))
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return PTR_ERR(cxld);
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cxld->interleave_ways = 1;
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cxld->interleave_granularity = PAGE_SIZE;
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cxld->target_type = CXL_DECODER_EXPANDER;
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cxld->range = (struct range) {
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.start = 0,
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.end = -1,
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};
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device_lock(&port->dev);
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dport = list_first_entry(&port->dports, typeof(*dport), list);
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device_unlock(&port->dev);
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single_port_map[0] = dport->port_id;
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rc = cxl_decoder_add(cxld, single_port_map);
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if (rc)
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put_device(&cxld->dev);
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else
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rc = cxl_decoder_autoremove(host, cxld);
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if (rc == 0)
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dev_dbg(host, "add: %s\n", dev_name(&cxld->dev));
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}
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return 0;
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return rc;
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}
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static int add_host_bridge_dport(struct device *match, void *arg)
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@ -453,10 +453,8 @@ err:
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}
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EXPORT_SYMBOL_GPL(cxl_add_dport);
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static int decoder_populate_targets(struct device *host,
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struct cxl_decoder *cxld,
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struct cxl_port *port, int *target_map,
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int nr_targets)
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static int decoder_populate_targets(struct cxl_decoder *cxld,
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struct cxl_port *port, int *target_map)
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{
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int rc = 0, i;
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@ -464,66 +462,48 @@ static int decoder_populate_targets(struct device *host,
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return 0;
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device_lock(&port->dev);
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for (i = 0; i < nr_targets; i++) {
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if (list_empty(&port->dports)) {
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rc = -EINVAL;
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goto out_unlock;
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}
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for (i = 0; i < cxld->nr_targets; i++) {
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struct cxl_dport *dport = find_dport(port, target_map[i]);
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if (!dport) {
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rc = -ENXIO;
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break;
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goto out_unlock;
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}
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dev_dbg(host, "%s: target: %d\n", dev_name(dport->dport), i);
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cxld->target[i] = dport;
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}
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out_unlock:
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device_unlock(&port->dev);
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return rc;
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}
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static struct cxl_decoder *
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cxl_decoder_alloc(struct device *host, struct cxl_port *port, int nr_targets,
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resource_size_t base, resource_size_t len,
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int interleave_ways, int interleave_granularity,
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enum cxl_decoder_type type, unsigned long flags,
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int *target_map)
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struct cxl_decoder *cxl_decoder_alloc(struct cxl_port *port, int nr_targets)
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{
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struct cxl_decoder *cxld;
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struct cxl_decoder *cxld, cxld_const_init = {
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.nr_targets = nr_targets,
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};
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struct device *dev;
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int rc = 0;
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if (interleave_ways < 1)
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if (nr_targets > CXL_DECODER_MAX_INTERLEAVE || nr_targets < 1)
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return ERR_PTR(-EINVAL);
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device_lock(&port->dev);
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if (list_empty(&port->dports))
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rc = -EINVAL;
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device_unlock(&port->dev);
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if (rc)
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return ERR_PTR(rc);
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cxld = kzalloc(struct_size(cxld, target, nr_targets), GFP_KERNEL);
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if (!cxld)
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return ERR_PTR(-ENOMEM);
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memcpy(cxld, &cxld_const_init, sizeof(cxld_const_init));
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rc = ida_alloc(&port->decoder_ida, GFP_KERNEL);
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if (rc < 0)
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goto err;
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*cxld = (struct cxl_decoder) {
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.id = rc,
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.range = {
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.start = base,
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.end = base + len - 1,
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},
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.flags = flags,
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.interleave_ways = interleave_ways,
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.interleave_granularity = interleave_granularity,
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.target_type = type,
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};
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rc = decoder_populate_targets(host, cxld, port, target_map, nr_targets);
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if (rc)
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goto err;
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cxld->id = rc;
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dev = &cxld->dev;
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device_initialize(dev);
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device_set_pm_not_required(dev);
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@ -541,72 +521,47 @@ err:
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kfree(cxld);
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return ERR_PTR(rc);
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}
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EXPORT_SYMBOL_GPL(cxl_decoder_alloc);
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struct cxl_decoder *
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devm_cxl_add_decoder(struct device *host, struct cxl_port *port, int nr_targets,
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resource_size_t base, resource_size_t len,
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int interleave_ways, int interleave_granularity,
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enum cxl_decoder_type type, unsigned long flags,
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int *target_map)
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int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map)
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{
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struct cxl_decoder *cxld;
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struct cxl_port *port;
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struct device *dev;
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int rc;
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if (nr_targets > CXL_DECODER_MAX_INTERLEAVE)
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return ERR_PTR(-EINVAL);
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if (WARN_ON_ONCE(!cxld))
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return -EINVAL;
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cxld = cxl_decoder_alloc(host, port, nr_targets, base, len,
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interleave_ways, interleave_granularity, type,
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flags, target_map);
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if (IS_ERR(cxld))
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return cxld;
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if (WARN_ON_ONCE(IS_ERR(cxld)))
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return PTR_ERR(cxld);
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if (cxld->interleave_ways < 1)
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return -EINVAL;
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port = to_cxl_port(cxld->dev.parent);
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rc = decoder_populate_targets(cxld, port, target_map);
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if (rc)
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return rc;
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dev = &cxld->dev;
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rc = dev_set_name(dev, "decoder%d.%d", port->id, cxld->id);
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if (rc)
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goto err;
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return rc;
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rc = device_add(dev);
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if (rc)
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goto err;
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rc = devm_add_action_or_reset(host, unregister_cxl_dev, dev);
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if (rc)
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return ERR_PTR(rc);
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return cxld;
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err:
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put_device(dev);
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return ERR_PTR(rc);
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return device_add(dev);
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}
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EXPORT_SYMBOL_GPL(devm_cxl_add_decoder);
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EXPORT_SYMBOL_GPL(cxl_decoder_add);
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/*
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* Per the CXL specification (8.2.5.12 CXL HDM Decoder Capability Structure)
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* single ported host-bridges need not publish a decoder capability when a
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* passthrough decode can be assumed, i.e. all transactions that the uport sees
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* are claimed and passed to the single dport. Default the range a 0-base
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* 0-length until the first CXL region is activated.
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*/
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struct cxl_decoder *devm_cxl_add_passthrough_decoder(struct device *host,
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struct cxl_port *port)
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static void cxld_unregister(void *dev)
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{
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struct cxl_dport *dport;
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int target_map[1];
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device_lock(&port->dev);
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dport = list_first_entry_or_null(&port->dports, typeof(*dport), list);
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device_unlock(&port->dev);
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if (!dport)
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return ERR_PTR(-ENXIO);
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target_map[0] = dport->port_id;
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return devm_cxl_add_decoder(host, port, 1, 0, 0, 1, PAGE_SIZE,
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CXL_DECODER_EXPANDER, 0, target_map);
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device_unregister(dev);
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}
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EXPORT_SYMBOL_GPL(devm_cxl_add_passthrough_decoder);
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int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld)
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{
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return devm_add_action_or_reset(host, cxld_unregister, &cxld->dev);
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}
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EXPORT_SYMBOL_GPL(cxl_decoder_autoremove);
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/**
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* __cxl_driver_register - register a driver for the cxl bus
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@ -9,11 +9,6 @@ extern const struct device_type cxl_nvdimm_type;
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extern struct attribute_group cxl_base_attribute_group;
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static inline void unregister_cxl_dev(void *dev)
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{
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device_unregister(dev);
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}
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struct cxl_send_command;
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struct cxl_mem_query_commands;
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int cxl_query_cmd(struct cxl_memdev *cxlmd,
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@ -222,6 +222,11 @@ static struct cxl_nvdimm *cxl_nvdimm_alloc(struct cxl_memdev *cxlmd)
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return cxl_nvd;
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}
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static void cxl_nvd_unregister(void *dev)
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{
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device_unregister(dev);
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}
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/**
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* devm_cxl_add_nvdimm() - add a bridge between a cxl_memdev and an nvdimm
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* @host: same host as @cxlmd
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@ -251,7 +256,7 @@ int devm_cxl_add_nvdimm(struct device *host, struct cxl_memdev *cxlmd)
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dev_dbg(host, "%s: register %s\n", dev_name(dev->parent),
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dev_name(dev));
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return devm_add_action_or_reset(host, unregister_cxl_dev, dev);
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return devm_add_action_or_reset(host, cxl_nvd_unregister, dev);
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err:
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put_device(dev);
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@ -195,6 +195,7 @@ enum cxl_decoder_type {
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* @interleave_granularity: data stride per dport
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* @target_type: accelerator vs expander (type2 vs type3) selector
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* @flags: memory type capabilities and locking
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* @nr_targets: number of elements in @target
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* @target: active ordered target list in current decoder configuration
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*/
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struct cxl_decoder {
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@ -205,6 +206,7 @@ struct cxl_decoder {
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int interleave_granularity;
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enum cxl_decoder_type target_type;
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unsigned long flags;
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const int nr_targets;
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struct cxl_dport *target[];
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};
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@ -286,15 +288,10 @@ int cxl_add_dport(struct cxl_port *port, struct device *dport, int port_id,
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struct cxl_decoder *to_cxl_decoder(struct device *dev);
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bool is_root_decoder(struct device *dev);
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struct cxl_decoder *
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devm_cxl_add_decoder(struct device *host, struct cxl_port *port, int nr_targets,
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resource_size_t base, resource_size_t len,
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int interleave_ways, int interleave_granularity,
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enum cxl_decoder_type type, unsigned long flags,
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int *target_map);
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struct cxl_decoder *cxl_decoder_alloc(struct cxl_port *port, int nr_targets);
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int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map);
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int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld);
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struct cxl_decoder *devm_cxl_add_passthrough_decoder(struct device *host,
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struct cxl_port *port);
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extern struct bus_type cxl_bus_type;
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struct cxl_driver {
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