powerpc/mm: Move book3s64 specifics in subdirectory mm/book3s64
Many files in arch/powerpc/mm are only for book3S64. This patch
creates a subdirectory for them.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
[mpe: Update the selftest sym links, shorten new filenames, cleanup some
whitespace and formatting in the new files.]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Christophe Leroy
Michael Ellerman
parent
9d9f2cccde
commit
47d99948ee
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@ -5,53 +5,34 @@
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ccflags-$(CONFIG_PPC64) := $(NO_MINIMAL_TOC)
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CFLAGS_REMOVE_slb.o = $(CC_FLAGS_FTRACE)
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obj-y := fault.o mem.o pgtable.o mmap.o \
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init_$(BITS).o pgtable_$(BITS).o \
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init-common.o mmu_context.o drmem.o
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obj-$(CONFIG_PPC_MMU_NOHASH) += mmu_context_nohash.o tlb_nohash.o \
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tlb_nohash_low.o
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obj-$(CONFIG_PPC_BOOK3E) += tlb_low_$(BITS)e.o
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hash64-$(CONFIG_PPC_NATIVE) := hash_native_64.o
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obj-$(CONFIG_PPC_BOOK3E_64) += pgtable-book3e.o
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obj-$(CONFIG_PPC_BOOK3S_64) += pgtable-hash64.o hash_utils_64.o slb.o \
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$(hash64-y) mmu_context_book3s64.o \
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pgtable-book3s64.o pgtable-frag.o
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obj-$(CONFIG_PPC_BOOK3S_64) += book3s64/
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obj-$(CONFIG_PPC_BOOK3S_64) += pgtable-frag.o
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obj-$(CONFIG_PPC32) += pgtable-frag.o
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obj-$(CONFIG_PPC_RADIX_MMU) += pgtable-radix.o tlb-radix.o
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obj-$(CONFIG_PPC_BOOK3S_32) += ppc_mmu_32.o hash_low_32.o mmu_context_hash32.o
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obj-$(CONFIG_PPC_BOOK3S) += tlb_hash$(BITS).o
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ifdef CONFIG_PPC_BOOK3S_64
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obj-$(CONFIG_PPC_4K_PAGES) += hash64_4k.o
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obj-$(CONFIG_PPC_64K_PAGES) += hash64_64k.o
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endif
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obj-$(CONFIG_PPC_BOOK3S_32) += tlb_hash32.o
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obj-$(CONFIG_40x) += 40x_mmu.o
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obj-$(CONFIG_44x) += 44x_mmu.o
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obj-$(CONFIG_PPC_8xx) += 8xx_mmu.o
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obj-$(CONFIG_PPC_FSL_BOOK3E) += fsl_booke_mmu.o
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obj-$(CONFIG_NEED_MULTIPLE_NODES) += numa.o
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obj-$(CONFIG_PPC_SPLPAR) += vphn.o
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obj-$(CONFIG_PPC_MM_SLICES) += slice.o
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obj-y += hugetlbpage.o
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ifdef CONFIG_HUGETLB_PAGE
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obj-$(CONFIG_PPC_BOOK3S_64) += hugetlbpage-hash64.o
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obj-$(CONFIG_PPC_RADIX_MMU) += hugetlbpage-radix.o
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obj-$(CONFIG_PPC_BOOK3E_MMU) += hugetlbpage-book3e.o
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endif
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obj-$(CONFIG_TRANSPARENT_HUGEPAGE) += hugepage-hash64.o
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obj-$(CONFIG_PPC_SUBPAGE_PROT) += subpage-prot.o
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obj-$(CONFIG_NOT_COHERENT_CACHE) += dma-noncoherent.o
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obj-$(CONFIG_HIGHMEM) += highmem.o
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obj-$(CONFIG_PPC_COPRO_BASE) += copro_fault.o
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obj-$(CONFIG_SPAPR_TCE_IOMMU) += mmu_context_iommu.o
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obj-$(CONFIG_PPC_PTDUMP) += ptdump/
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obj-$(CONFIG_PPC_MEM_KEYS) += pkeys.o
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# Disable kcov instrumentation on sensitive code
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# This is necessary for booting with kcov enabled on book3e machines
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KCOV_INSTRUMENT_tlb_nohash.o := n
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KCOV_INSTRUMENT_fsl_booke_mmu.o := n
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# Instrumenting the SLB fault path can lead to duplicate SLB entries
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KCOV_INSTRUMENT_slb.o := n
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@ -0,0 +1,24 @@
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# SPDX-License-Identifier: GPL-2.0
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ccflags-y := $(NO_MINIMAL_TOC)
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CFLAGS_REMOVE_slb.o = $(CC_FLAGS_FTRACE)
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obj-y += hash_pgtable.o hash_utils.o slb.o \
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mmu_context.o pgtable.o hash_tlb.o
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obj-$(CONFIG_PPC_NATIVE) += hash_native.o
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obj-$(CONFIG_PPC_RADIX_MMU) += radix_pgtable.o radix_tlb.o
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obj-$(CONFIG_PPC_4K_PAGES) += hash_4k.o
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obj-$(CONFIG_PPC_64K_PAGES) += hash_64k.o
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obj-$(CONFIG_PPC_SPLPAR) += vphn.o
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obj-$(CONFIG_HUGETLB_PAGE) += hash_hugetlbpage.o
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ifdef CONFIG_HUGETLB_PAGE
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obj-$(CONFIG_PPC_RADIX_MMU) += radix_hugetlbpage.o
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endif
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obj-$(CONFIG_TRANSPARENT_HUGEPAGE) += hash_hugepage.o
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obj-$(CONFIG_PPC_SUBPAGE_PROT) += subpage_prot.o
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obj-$(CONFIG_SPAPR_TCE_IOMMU) += iommu_api.o
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obj-$(CONFIG_PPC_MEM_KEYS) += pkeys.o
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# Instrumenting the SLB fault path can lead to duplicate SLB entries
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KCOV_INSTRUMENT_slb.o := n
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@ -1,6 +1,6 @@
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/*
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* Copyright IBM Corporation, 2015
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* Author Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
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* Author Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU Lesser General Public License
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@ -1,6 +1,6 @@
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/*
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* Copyright IBM Corporation, 2015
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* Author Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
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* Author Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU Lesser General Public License
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@ -1,6 +1,6 @@
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/*
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* Copyright IBM Corporation, 2013
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* Author Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
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* Author Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2.1 of the GNU Lesser General Public License
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@ -34,7 +34,8 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
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/* Search the Linux page table for a match with va */
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vpn = hpt_vpn(ea, vsid, ssize);
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/* At this point, we have a pte (old_pte) which can be used to build
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/*
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* At this point, we have a pte (old_pte) which can be used to build
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* or update an HPTE. There are 2 cases:
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*
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* 1. There is a valid (present) pte with no associated HPTE (this is
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@ -55,8 +56,10 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
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if (unlikely(!check_pte_access(access, old_pte)))
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return 1;
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/* Try to lock the PTE, add ACCESSED and DIRTY if it was
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* a write access */
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/*
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* Try to lock the PTE, add ACCESSED and DIRTY if it was
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* a write access
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*/
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new_pte = old_pte | H_PAGE_BUSY | _PAGE_ACCESSED;
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if (access & _PAGE_WRITE)
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new_pte |= _PAGE_DIRTY;
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@ -74,8 +77,10 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
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rpte = __real_pte(__pte(old_pte), ptep, offset);
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if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
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/* No CPU has hugepages but lacks no execute, so we
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* don't need to worry about that case */
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/*
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* No CPU has hugepages but lacks no execute, so we
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* don't need to worry about that case
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*/
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rflags = hash_page_do_lazy_icache(rflags, __pte(old_pte), trap);
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/* Check if pte already has an hpte (case 2) */
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@ -55,7 +55,8 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
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i = batch->index;
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/* Get page size (maybe move back to caller).
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/*
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* Get page size (maybe move back to caller).
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*
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* NOTE: when using special 64K mappings in 4K environment like
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* for SPEs, we obtain the page size from the slice, which thus
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@ -77,10 +78,12 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
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#endif
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} else {
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psize = pte_pagesize_index(mm, addr, pte);
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/* Mask the address for the standard page size. If we
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/*
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* Mask the address for the standard page size. If we
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* have a 64k page kernel, but the hardware does not
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* support 64k pages, this might be different from the
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* hardware page size encoded in the slice table. */
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* hardware page size encoded in the slice table.
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*/
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addr &= PAGE_MASK;
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offset = PTRS_PER_PTE;
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}
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@ -161,7 +164,8 @@ void hash__tlb_flush(struct mmu_gather *tlb)
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{
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struct ppc64_tlb_batch *tlbbatch = &get_cpu_var(ppc64_tlb_batch);
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/* If there's a TLB batch pending, then we must flush it because the
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/*
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* If there's a TLB batch pending, then we must flush it because the
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* pages are going to be freed and we really don't want to have a CPU
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* access a freed page because it has a stale TLB
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*/
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@ -201,7 +205,8 @@ void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
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BUG_ON(!mm->pgd);
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/* Note: Normally, we should only ever use a batch within a
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/*
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* Note: Normally, we should only ever use a batch within a
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* PTE locked section. This violates the rule, but will work
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* since we don't actually modify the PTEs, we just flush the
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* hash while leaving the PTEs intact (including their reference
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@ -238,7 +243,8 @@ void flush_tlb_pmd_range(struct mm_struct *mm, pmd_t *pmd, unsigned long addr)
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unsigned long flags;
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addr = _ALIGN_DOWN(addr, PMD_SIZE);
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/* Note: Normally, we should only ever use a batch within a
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/*
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* Note: Normally, we should only ever use a batch within a
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* PTE locked section. This violates the rule, but will work
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* since we don't actually modify the PTEs, we just flush the
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* hash while leaving the PTEs intact (including their reference
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@ -128,7 +128,8 @@ static DEFINE_SPINLOCK(linear_map_hash_lock);
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struct mmu_hash_ops mmu_hash_ops;
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EXPORT_SYMBOL(mmu_hash_ops);
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/* There are definitions of page sizes arrays to be used when none
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/*
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* These are definitions of page sizes arrays to be used when none
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* is provided by the firmware.
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*/
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@ -145,7 +146,8 @@ static struct mmu_psize_def mmu_psize_defaults[] = {
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},
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};
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/* POWER4, GPUL, POWER5
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/*
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* POWER4, GPUL, POWER5
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*
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* Support for 16Mb large pages
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*/
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@ -479,7 +481,8 @@ static int __init htab_dt_scan_page_sizes(unsigned long node,
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}
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#ifdef CONFIG_HUGETLB_PAGE
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/* Scan for 16G memory blocks that have been set aside for huge pages
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/*
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* Scan for 16G memory blocks that have been set aside for huge pages
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* and reserve those blocks for 16G huge pages.
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*/
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static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
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@ -496,8 +499,10 @@ static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
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if (type == NULL || strcmp(type, "memory") != 0)
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return 0;
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/* This property is the log base 2 of the number of virtual pages that
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* will represent this memory block. */
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/*
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* This property is the log base 2 of the number of virtual pages that
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* will represent this memory block.
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*/
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page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
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if (page_count_prop == NULL)
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return 0;
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@ -673,7 +678,8 @@ static void __init htab_init_page_sizes(void)
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#endif /* CONFIG_PPC_64K_PAGES */
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#ifdef CONFIG_SPARSEMEM_VMEMMAP
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/* We try to use 16M pages for vmemmap if that is supported
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/*
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* We try to use 16M pages for vmemmap if that is supported
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* and we have at least 1G of RAM at boot
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*/
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if (mmu_psize_defs[MMU_PAGE_16M].shift &&
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@ -742,7 +748,8 @@ unsigned htab_shift_for_mem_size(unsigned long mem_size)
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static unsigned long __init htab_get_table_size(void)
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{
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/* If hash size isn't already provided by the platform, we try to
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/*
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* If hash size isn't already provided by the platform, we try to
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* retrieve it from the device-tree. If it's not there neither, we
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* calculate it now based on the total RAM size
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*/
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@ -1043,7 +1050,8 @@ void __init hash__early_init_mmu(void)
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if (!mmu_hash_ops.hpte_insert)
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panic("hash__early_init_mmu: No MMU hash ops defined!\n");
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/* Initialize the MMU Hash table and create the linear mapping
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/*
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* Initialize the MMU Hash table and create the linear mapping
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* of memory. Has to be done before SLB initialization as this is
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* currently where the page size encoding is obtained.
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*/
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@ -1228,7 +1236,8 @@ static void check_paca_psize(unsigned long ea, struct mm_struct *mm,
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}
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}
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/* Result code is:
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/*
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* Result code is:
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* 0 - handled
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* 1 - normal page fault
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* -1 - critical hash insertion error
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@ -1276,8 +1285,9 @@ int hash_page_mm(struct mm_struct *mm, unsigned long ea,
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ssize = mmu_kernel_ssize;
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break;
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default:
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/* Not a valid range
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* Send the problem up to do_page_fault
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/*
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* Not a valid range
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* Send the problem up to do_page_fault()
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*/
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rc = 1;
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goto bail;
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@ -1302,7 +1312,8 @@ int hash_page_mm(struct mm_struct *mm, unsigned long ea,
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flags |= HPTE_LOCAL_UPDATE;
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#ifndef CONFIG_PPC_64K_PAGES
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/* If we use 4K pages and our psize is not 4K, then we might
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/*
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* If we use 4K pages and our psize is not 4K, then we might
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* be hitting a special driver mapping, and need to align the
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* address before we fetch the PTE.
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*
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@ -1324,7 +1335,8 @@ int hash_page_mm(struct mm_struct *mm, unsigned long ea,
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/* Add _PAGE_PRESENT to the required access perm */
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access |= _PAGE_PRESENT;
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/* Pre-check access permissions (will be re-checked atomically
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/*
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* Pre-check access permissions (will be re-checked atomically
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* in __hash_page_XX but this pre-check is a fast path
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*/
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if (!check_pte_access(access, pte_val(*ptep))) {
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@ -1371,7 +1383,8 @@ int hash_page_mm(struct mm_struct *mm, unsigned long ea,
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psize = MMU_PAGE_4K;
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}
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/* If this PTE is non-cacheable and we have restrictions on
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/*
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* If this PTE is non-cacheable and we have restrictions on
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* using non cacheable large pages, then we switch to 4k
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*/
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if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) {
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@ -1412,7 +1425,8 @@ int hash_page_mm(struct mm_struct *mm, unsigned long ea,
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flags, ssize, spp);
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}
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/* Dump some info in case of hash insertion failure, they should
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/*
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* Dump some info in case of hash insertion failure, they should
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* never happen so it is really useful to know if/when they do
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*/
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if (rc == -1)
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@ -1653,7 +1667,8 @@ unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift,
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return gslot;
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}
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/* WARNING: This is called from hash_low_64.S, if you change this prototype,
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/*
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* WARNING: This is called from hash_low_64.S, if you change this prototype,
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* do not forget to update the assembly call site !
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*/
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void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
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@ -1874,7 +1889,8 @@ void __kernel_map_pages(struct page *page, int numpages, int enable)
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void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
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phys_addr_t first_memblock_size)
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{
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/* We don't currently support the first MEMBLOCK not mapping 0
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/*
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* We don't currently support the first MEMBLOCK not mapping 0
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* physical on those processors
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*/
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BUG_ON(first_memblock_base != 0);
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@ -681,7 +681,8 @@ void radix__mmu_cleanup_all(void)
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void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
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phys_addr_t first_memblock_size)
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{
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/* We don't currently support the first MEMBLOCK not mapping 0
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/*
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* We don't currently support the first MEMBLOCK not mapping 0
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* physical on those processors
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*/
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BUG_ON(first_memblock_base != 0);
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@ -1003,45 +1004,44 @@ pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long addre
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void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
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pgtable_t pgtable)
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{
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struct list_head *lh = (struct list_head *) pgtable;
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struct list_head *lh = (struct list_head *) pgtable;
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assert_spin_locked(pmd_lockptr(mm, pmdp));
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assert_spin_locked(pmd_lockptr(mm, pmdp));
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/* FIFO */
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if (!pmd_huge_pte(mm, pmdp))
|
||||
INIT_LIST_HEAD(lh);
|
||||
else
|
||||
list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp));
|
||||
pmd_huge_pte(mm, pmdp) = pgtable;
|
||||
/* FIFO */
|
||||
if (!pmd_huge_pte(mm, pmdp))
|
||||
INIT_LIST_HEAD(lh);
|
||||
else
|
||||
list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp));
|
||||
pmd_huge_pte(mm, pmdp) = pgtable;
|
||||
}
|
||||
|
||||
pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
|
||||
{
|
||||
pte_t *ptep;
|
||||
pgtable_t pgtable;
|
||||
struct list_head *lh;
|
||||
pte_t *ptep;
|
||||
pgtable_t pgtable;
|
||||
struct list_head *lh;
|
||||
|
||||
assert_spin_locked(pmd_lockptr(mm, pmdp));
|
||||
assert_spin_locked(pmd_lockptr(mm, pmdp));
|
||||
|
||||
/* FIFO */
|
||||
pgtable = pmd_huge_pte(mm, pmdp);
|
||||
lh = (struct list_head *) pgtable;
|
||||
if (list_empty(lh))
|
||||
pmd_huge_pte(mm, pmdp) = NULL;
|
||||
else {
|
||||
pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next;
|
||||
list_del(lh);
|
||||
}
|
||||
ptep = (pte_t *) pgtable;
|
||||
*ptep = __pte(0);
|
||||
ptep++;
|
||||
*ptep = __pte(0);
|
||||
return pgtable;
|
||||
/* FIFO */
|
||||
pgtable = pmd_huge_pte(mm, pmdp);
|
||||
lh = (struct list_head *) pgtable;
|
||||
if (list_empty(lh))
|
||||
pmd_huge_pte(mm, pmdp) = NULL;
|
||||
else {
|
||||
pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next;
|
||||
list_del(lh);
|
||||
}
|
||||
ptep = (pte_t *) pgtable;
|
||||
*ptep = __pte(0);
|
||||
ptep++;
|
||||
*ptep = __pte(0);
|
||||
return pgtable;
|
||||
}
|
||||
|
||||
|
||||
pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
|
||||
unsigned long addr, pmd_t *pmdp)
|
||||
unsigned long addr, pmd_t *pmdp)
|
||||
{
|
||||
pmd_t old_pmd;
|
||||
unsigned long old;
|
||||
|
|
@ -554,7 +554,8 @@ void slb_initialize(void)
|
|||
asm volatile("isync; slbia; isync":::"memory");
|
||||
create_shadowed_slbe(PAGE_OFFSET, mmu_kernel_ssize, lflags, LINEAR_INDEX);
|
||||
|
||||
/* For the boot cpu, we're running on the stack in init_thread_union,
|
||||
/*
|
||||
* For the boot cpu, we're running on the stack in init_thread_union,
|
||||
* which is in the first segment of the linear mapping, and also
|
||||
* get_paca()->kstack hasn't been initialized yet.
|
||||
* For secondary cpus, we need to bolt the kernel stack entry now.
|
||||
|
|
@ -42,7 +42,8 @@ int vphn_unpack_associativity(const long *packed, __be32 *unpacked)
|
|||
u16 new = be16_to_cpup(field++);
|
||||
|
||||
if (is_32bit) {
|
||||
/* Let's concatenate the 16 bits of this field to the
|
||||
/*
|
||||
* Let's concatenate the 16 bits of this field to the
|
||||
* 15 lower bits of the previous field
|
||||
*/
|
||||
unpacked[++nr_assoc_doms] =
|
||||
|
|
@ -56,7 +57,8 @@ int vphn_unpack_associativity(const long *packed, __be32 *unpacked)
|
|||
unpacked[++nr_assoc_doms] =
|
||||
cpu_to_be32(new & VPHN_FIELD_MASK);
|
||||
} else {
|
||||
/* Data is in the lower 15 bits of this field
|
||||
/*
|
||||
* Data is in the lower 15 bits of this field
|
||||
* concatenated with the next 16 bit field
|
||||
*/
|
||||
last = new;
|
||||
|
|
@ -2,8 +2,7 @@
|
|||
#ifndef _ARCH_POWERPC_MM_VPHN_H_
|
||||
#define _ARCH_POWERPC_MM_VPHN_H_
|
||||
|
||||
/* The H_HOME_NODE_ASSOCIATIVITY h_call returns 6 64-bit registers.
|
||||
*/
|
||||
/* The H_HOME_NODE_ASSOCIATIVITY h_call returns 6 64-bit registers. */
|
||||
#define VPHN_REGISTER_COUNT 6
|
||||
|
||||
/*
|
||||
|
|
@ -1068,7 +1068,7 @@ u64 memory_hotplug_max(void)
|
|||
/* Virtual Processor Home Node (VPHN) support */
|
||||
#ifdef CONFIG_PPC_SPLPAR
|
||||
|
||||
#include "vphn.h"
|
||||
#include "book3s64/vphn.h"
|
||||
|
||||
struct topology_update_data {
|
||||
struct topology_update_data *next;
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
../../../../../arch/powerpc/mm/vphn.c
|
||||
../../../../../arch/powerpc/mm/book3s64/vphn.c
|
||||
|
|
@ -1 +1 @@
|
|||
../../../../../arch/powerpc/mm/vphn.h
|
||||
../../../../../arch/powerpc/mm/book3s64/vphn.h
|
||||
Loading…
Reference in New Issue