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i2c: npcm: Remove own slave addresses 2:10 

NPCM can support up to 10 own slave addresses. In practice, only one
address is actually being used. In order to access addresses 2 and above,
need to switch register banks. The switch needs spinlock.
To avoid using spinlock for this useless feature removed support of SA >=
2. Also fix returned slave event enum.

Remove some comment since the bank selection is not required. The bank
selection is not required since the supported slave addresses are reduced.

Fixes: 56a1485b10 ("i2c: npcm7xx: Add Nuvoton NPCM I2C controller driver")
Signed-off-by: Tali Perry <tali.perry1@gmail.com>
Signed-off-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
This commit is contained in:
Tali Perry 2022-05-25 11:23:38 +08:00 committed by Wolfram Sang
parent 29d2bff1c3
commit 47d506d1a2
1 changed files with 16 additions and 25 deletions
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41
drivers/i2c/busses/i2c-npcm7xx.c
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@ -123,11 +123,11 @@ enum i2c_addr {
* Since the addr regs are sprinkled all over the address space, * Since the addr regs are sprinkled all over the address space,
* use this array to get the address or each register. * use this array to get the address or each register.
*/ */
#define I2C_NUM_OWN_ADDR 10 #define I2C_NUM_OWN_ADDR 2
#define I2C_NUM_OWN_ADDR_SUPPORTED 2
static const int npcm_i2caddr[I2C_NUM_OWN_ADDR] = { static const int npcm_i2caddr[I2C_NUM_OWN_ADDR] = {
NPCM_I2CADDR1, NPCM_I2CADDR2, NPCM_I2CADDR3, NPCM_I2CADDR4, NPCM_I2CADDR1, NPCM_I2CADDR2,
NPCM_I2CADDR5, NPCM_I2CADDR6, NPCM_I2CADDR7, NPCM_I2CADDR8,
NPCM_I2CADDR9, NPCM_I2CADDR10,
}; };
#endif #endif
@ -392,14 +392,10 @@ static void npcm_i2c_disable(struct npcm_i2c *bus)
#if IS_ENABLED(CONFIG_I2C_SLAVE) #if IS_ENABLED(CONFIG_I2C_SLAVE)
int i; int i;
/* select bank 0 for I2C addresses */
npcm_i2c_select_bank(bus, I2C_BANK_0);
/* Slave addresses removal */ /* Slave addresses removal */
for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR; i++) for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR_SUPPORTED; i++)
iowrite8(0, bus->reg + npcm_i2caddr[i]); iowrite8(0, bus->reg + npcm_i2caddr[i]);
npcm_i2c_select_bank(bus, I2C_BANK_1);
#endif #endif
/* Disable module */ /* Disable module */
i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2); i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
@ -604,8 +600,7 @@ static int npcm_i2c_slave_enable(struct npcm_i2c *bus, enum i2c_addr addr_type,
i2cctl1 &= ~NPCM_I2CCTL1_GCMEN; i2cctl1 &= ~NPCM_I2CCTL1_GCMEN;
iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1); iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
return 0; return 0;
} } else if (addr_type == I2C_ARP_ADDR) {
if (addr_type == I2C_ARP_ADDR) {
i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3); i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
if (enable) if (enable)
i2cctl3 |= I2CCTL3_ARPMEN; i2cctl3 |= I2CCTL3_ARPMEN;
@ -614,16 +609,16 @@ static int npcm_i2c_slave_enable(struct npcm_i2c *bus, enum i2c_addr addr_type,
iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3); iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
return 0; return 0;
} }
if (addr_type > I2C_SLAVE_ADDR2 && addr_type <= I2C_SLAVE_ADDR10)
dev_err(bus->dev, "try to enable more than 2 SA not supported\n");
if (addr_type >= I2C_ARP_ADDR) if (addr_type >= I2C_ARP_ADDR)
return -EFAULT; return -EFAULT;
/* select bank 0 for address 3 to 10 */
if (addr_type > I2C_SLAVE_ADDR2)
npcm_i2c_select_bank(bus, I2C_BANK_0);
/* Set and enable the address */ /* Set and enable the address */
iowrite8(sa_reg, bus->reg + npcm_i2caddr[addr_type]); iowrite8(sa_reg, bus->reg + npcm_i2caddr[addr_type]);
npcm_i2c_slave_int_enable(bus, enable); npcm_i2c_slave_int_enable(bus, enable);
if (addr_type > I2C_SLAVE_ADDR2)
npcm_i2c_select_bank(bus, I2C_BANK_1);
return 0; return 0;
} }
#endif #endif
@ -846,15 +841,11 @@ static u8 npcm_i2c_get_slave_addr(struct npcm_i2c *bus, enum i2c_addr addr_type)
{ {
u8 slave_add; u8 slave_add;
/* select bank 0 for address 3 to 10 */ if (addr_type > I2C_SLAVE_ADDR2 && addr_type <= I2C_SLAVE_ADDR10)
if (addr_type > I2C_SLAVE_ADDR2) dev_err(bus->dev, "get slave: try to use more than 2 SA not supported\n");
npcm_i2c_select_bank(bus, I2C_BANK_0);
slave_add = ioread8(bus->reg + npcm_i2caddr[(int)addr_type]); slave_add = ioread8(bus->reg + npcm_i2caddr[(int)addr_type]);
if (addr_type > I2C_SLAVE_ADDR2)
npcm_i2c_select_bank(bus, I2C_BANK_1);
return slave_add; return slave_add;
} }
@ -864,12 +855,12 @@ static int npcm_i2c_remove_slave_addr(struct npcm_i2c *bus, u8 slave_add)
/* Set the enable bit */ /* Set the enable bit */
slave_add |= 0x80; slave_add |= 0x80;
npcm_i2c_select_bank(bus, I2C_BANK_0);
for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR; i++) { for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR_SUPPORTED; i++) {
if (ioread8(bus->reg + npcm_i2caddr[i]) == slave_add) if (ioread8(bus->reg + npcm_i2caddr[i]) == slave_add)
iowrite8(0, bus->reg + npcm_i2caddr[i]); iowrite8(0, bus->reg + npcm_i2caddr[i]);
} }
npcm_i2c_select_bank(bus, I2C_BANK_1);
return 0; return 0;
} }