stmmac: add GMAC4 core support
This is the initial support for GMAC4 that includes the main callbacks to setup the core module: including Csum, basic filtering, mac address and interrupt (MMC, MTL, PMT) No LPI added. Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Alexandre TORGUE
David S. Miller
parent
48863ce594
commit
477286b53f
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@ -3,7 +3,7 @@ stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o \
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chain_mode.o dwmac_lib.o dwmac1000_core.o dwmac1000_dma.o \
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dwmac100_core.o dwmac100_dma.o enh_desc.o norm_desc.o \
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mmc_core.o stmmac_hwtstamp.o stmmac_ptp.o dwmac4_descs.o \
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dwmac4_dma.o dwmac4_lib.o $(stmmac-y)
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dwmac4_dma.o dwmac4_lib.o dwmac4_core.o $(stmmac-y)
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# Ordering matters. Generic driver must be last.
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obj-$(CONFIG_STMMAC_PLATFORM) += stmmac-platform.o
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@ -527,15 +527,21 @@ struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins,
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int perfect_uc_entries,
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int *synopsys_id);
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struct mac_device_info *dwmac100_setup(void __iomem *ioaddr, int *synopsys_id);
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struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins,
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int perfect_uc_entries, int *synopsys_id);
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void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
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unsigned int high, unsigned int low);
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void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
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unsigned int high, unsigned int low);
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void stmmac_set_mac(void __iomem *ioaddr, bool enable);
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void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
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unsigned int high, unsigned int low);
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void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
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unsigned int high, unsigned int low);
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void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);
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void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
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extern const struct stmmac_mode_ops ring_mode_ops;
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extern const struct stmmac_mode_ops chain_mode_ops;
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@ -221,4 +221,35 @@ enum power_event {
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/* To dump the core regs excluding the Address Registers */
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#define GMAC_REG_NUM 132
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/* MTL debug */
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#define MTL_DEBUG_TXSTSFSTS BIT(5)
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#define MTL_DEBUG_TXFSTS BIT(4)
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#define MTL_DEBUG_TWCSTS BIT(3)
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/* MTL debug: Tx FIFO Read Controller Status */
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#define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1)
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#define MTL_DEBUG_TRCSTS_SHIFT 1
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#define MTL_DEBUG_TRCSTS_IDLE 0
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#define MTL_DEBUG_TRCSTS_READ 1
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#define MTL_DEBUG_TRCSTS_TXW 2
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#define MTL_DEBUG_TRCSTS_WRITE 3
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#define MTL_DEBUG_TXPAUSED BIT(0)
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/* MAC debug: GMII or MII Transmit Protocol Engine Status */
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#define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4)
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#define MTL_DEBUG_RXFSTS_SHIFT 4
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#define MTL_DEBUG_RXFSTS_EMPTY 0
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#define MTL_DEBUG_RXFSTS_BT 1
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#define MTL_DEBUG_RXFSTS_AT 2
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#define MTL_DEBUG_RXFSTS_FULL 3
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#define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1)
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#define MTL_DEBUG_RRCSTS_SHIFT 1
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#define MTL_DEBUG_RRCSTS_IDLE 0
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#define MTL_DEBUG_RRCSTS_RDATA 1
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#define MTL_DEBUG_RRCSTS_RSTAT 2
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#define MTL_DEBUG_RRCSTS_FLUSH 3
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#define MTL_DEBUG_RWCSTS BIT(0)
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extern const struct stmmac_dma_ops dwmac4_dma_ops;
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extern const struct stmmac_dma_ops dwmac410_dma_ops;
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#endif /* __DWMAC4_H__ */
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@ -0,0 +1,407 @@
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/*
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* This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
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* DWC Ether MAC version 4.00 has been used for developing this code.
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*
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* This only implements the mac core functions for this chip.
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*
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* Copyright (C) 2015 STMicroelectronics Ltd
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* Author: Alexandre Torgue <alexandre.torgue@st.com>
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*/
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#include <linux/crc32.h>
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#include <linux/slab.h>
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#include <linux/ethtool.h>
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#include <linux/io.h>
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#include "dwmac4.h"
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static void dwmac4_core_init(struct mac_device_info *hw, int mtu)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value = readl(ioaddr + GMAC_CONFIG);
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value |= GMAC_CORE_INIT;
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if (mtu > 1500)
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value |= GMAC_CONFIG_2K;
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if (mtu > 2000)
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value |= GMAC_CONFIG_JE;
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writel(value, ioaddr + GMAC_CONFIG);
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/* Mask GMAC interrupts */
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writel(GMAC_INT_PMT_EN, ioaddr + GMAC_INT_EN);
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}
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static void dwmac4_dump_regs(struct mac_device_info *hw)
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{
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void __iomem *ioaddr = hw->pcsr;
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int i;
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pr_debug("\tDWMAC4 regs (base addr = 0x%p)\n", ioaddr);
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for (i = 0; i < GMAC_REG_NUM; i++) {
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int offset = i * 4;
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pr_debug("\tReg No. %d (offset 0x%x): 0x%08x\n", i,
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offset, readl(ioaddr + offset));
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}
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}
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static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value = readl(ioaddr + GMAC_CONFIG);
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if (hw->rx_csum)
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value |= GMAC_CONFIG_IPC;
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else
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value &= ~GMAC_CONFIG_IPC;
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writel(value, ioaddr + GMAC_CONFIG);
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value = readl(ioaddr + GMAC_CONFIG);
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return !!(value & GMAC_CONFIG_IPC);
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}
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static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
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{
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void __iomem *ioaddr = hw->pcsr;
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unsigned int pmt = 0;
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if (mode & WAKE_MAGIC) {
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pr_debug("GMAC: WOL Magic frame\n");
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pmt |= power_down | magic_pkt_en;
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}
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if (mode & WAKE_UCAST) {
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pr_debug("GMAC: WOL on global unicast\n");
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pmt |= global_unicast;
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}
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writel(pmt, ioaddr + GMAC_PMT);
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}
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static void dwmac4_set_umac_addr(struct mac_device_info *hw,
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unsigned char *addr, unsigned int reg_n)
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{
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void __iomem *ioaddr = hw->pcsr;
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stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
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GMAC_ADDR_LOW(reg_n));
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}
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static void dwmac4_get_umac_addr(struct mac_device_info *hw,
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unsigned char *addr, unsigned int reg_n)
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{
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void __iomem *ioaddr = hw->pcsr;
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stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
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GMAC_ADDR_LOW(reg_n));
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}
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static void dwmac4_set_filter(struct mac_device_info *hw,
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struct net_device *dev)
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{
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void __iomem *ioaddr = (void __iomem *)dev->base_addr;
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unsigned int value = 0;
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if (dev->flags & IFF_PROMISC) {
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value = GMAC_PACKET_FILTER_PR;
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} else if ((dev->flags & IFF_ALLMULTI) ||
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(netdev_mc_count(dev) > HASH_TABLE_SIZE)) {
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/* Pass all multi */
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value = GMAC_PACKET_FILTER_PM;
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/* Set the 64 bits of the HASH tab. To be updated if taller
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* hash table is used
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*/
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writel(0xffffffff, ioaddr + GMAC_HASH_TAB_0_31);
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writel(0xffffffff, ioaddr + GMAC_HASH_TAB_32_63);
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} else if (!netdev_mc_empty(dev)) {
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u32 mc_filter[2];
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struct netdev_hw_addr *ha;
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/* Hash filter for multicast */
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value = GMAC_PACKET_FILTER_HMC;
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memset(mc_filter, 0, sizeof(mc_filter));
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netdev_for_each_mc_addr(ha, dev) {
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/* The upper 6 bits of the calculated CRC are used to
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* index the content of the Hash Table Reg 0 and 1.
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*/
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int bit_nr =
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(bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26);
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/* The most significant bit determines the register
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* to use while the other 5 bits determines the bit
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* within the selected register
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*/
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mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1F));
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}
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writel(mc_filter[0], ioaddr + GMAC_HASH_TAB_0_31);
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writel(mc_filter[1], ioaddr + GMAC_HASH_TAB_32_63);
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}
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/* Handle multiple unicast addresses */
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if (netdev_uc_count(dev) > GMAC_MAX_PERFECT_ADDRESSES) {
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/* Switch to promiscuous mode if more than 128 addrs
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* are required
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*/
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value |= GMAC_PACKET_FILTER_PR;
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} else if (!netdev_uc_empty(dev)) {
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int reg = 1;
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struct netdev_hw_addr *ha;
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netdev_for_each_uc_addr(ha, dev) {
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dwmac4_set_umac_addr(ioaddr, ha->addr, reg);
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reg++;
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}
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}
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writel(value, ioaddr + GMAC_PACKET_FILTER);
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}
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static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
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unsigned int fc, unsigned int pause_time)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 channel = STMMAC_CHAN0; /* FIXME */
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unsigned int flow = 0;
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pr_debug("GMAC Flow-Control:\n");
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if (fc & FLOW_RX) {
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pr_debug("\tReceive Flow-Control ON\n");
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flow |= GMAC_RX_FLOW_CTRL_RFE;
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writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
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}
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if (fc & FLOW_TX) {
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pr_debug("\tTransmit Flow-Control ON\n");
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flow |= GMAC_TX_FLOW_CTRL_TFE;
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writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(channel));
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if (duplex) {
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pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
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flow |= (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
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writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(channel));
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}
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}
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}
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static void dwmac4_ctrl_ane(struct mac_device_info *hw, bool restart)
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{
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void __iomem *ioaddr = hw->pcsr;
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/* auto negotiation enable and External Loopback enable */
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u32 value = GMAC_AN_CTRL_ANE | GMAC_AN_CTRL_ELE;
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if (restart)
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value |= GMAC_AN_CTRL_RAN;
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writel(value, ioaddr + GMAC_AN_CTRL);
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}
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static void dwmac4_get_adv(struct mac_device_info *hw, struct rgmii_adv *adv)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value = readl(ioaddr + GMAC_AN_ADV);
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if (value & GMAC_AN_FD)
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adv->duplex = DUPLEX_FULL;
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if (value & GMAC_AN_HD)
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adv->duplex |= DUPLEX_HALF;
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adv->pause = (value & GMAC_AN_PSE_MASK) >> GMAC_AN_PSE_SHIFT;
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value = readl(ioaddr + GMAC_AN_LPA);
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if (value & GMAC_AN_FD)
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adv->lp_duplex = DUPLEX_FULL;
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if (value & GMAC_AN_HD)
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adv->lp_duplex = DUPLEX_HALF;
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adv->lp_pause = (value & GMAC_AN_PSE_MASK) >> GMAC_AN_PSE_SHIFT;
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}
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static int dwmac4_irq_status(struct mac_device_info *hw,
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struct stmmac_extra_stats *x)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 mtl_int_qx_status;
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u32 intr_status;
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int ret = 0;
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intr_status = readl(ioaddr + GMAC_INT_STATUS);
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/* Not used events (e.g. MMC interrupts) are not handled. */
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if ((intr_status & mmc_tx_irq))
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x->mmc_tx_irq_n++;
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if (unlikely(intr_status & mmc_rx_irq))
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x->mmc_rx_irq_n++;
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if (unlikely(intr_status & mmc_rx_csum_offload_irq))
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x->mmc_rx_csum_offload_irq_n++;
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/* Clear the PMT bits 5 and 6 by reading the PMT status reg */
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if (unlikely(intr_status & pmt_irq)) {
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readl(ioaddr + GMAC_PMT);
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x->irq_receive_pmt_irq_n++;
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}
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if ((intr_status & pcs_ane_irq) || (intr_status & pcs_link_irq)) {
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readl(ioaddr + GMAC_AN_STATUS);
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x->irq_pcs_ane_n++;
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}
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mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
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/* Check MTL Interrupt: Currently only one queue is used: Q0. */
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if (mtl_int_qx_status & MTL_INT_Q0) {
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/* read Queue 0 Interrupt status */
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u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(STMMAC_CHAN0));
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if (status & MTL_RX_OVERFLOW_INT) {
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/* clear Interrupt */
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writel(status | MTL_RX_OVERFLOW_INT,
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ioaddr + MTL_CHAN_INT_CTRL(STMMAC_CHAN0));
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ret = CORE_IRQ_MTL_RX_OVERFLOW;
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}
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}
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return ret;
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}
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static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x)
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{
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u32 value;
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/* Currently only channel 0 is supported */
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value = readl(ioaddr + MTL_CHAN_TX_DEBUG(STMMAC_CHAN0));
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if (value & MTL_DEBUG_TXSTSFSTS)
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x->mtl_tx_status_fifo_full++;
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if (value & MTL_DEBUG_TXFSTS)
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x->mtl_tx_fifo_not_empty++;
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if (value & MTL_DEBUG_TWCSTS)
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x->mmtl_fifo_ctrl++;
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if (value & MTL_DEBUG_TRCSTS_MASK) {
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u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
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>> MTL_DEBUG_TRCSTS_SHIFT;
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if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
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x->mtl_tx_fifo_read_ctrl_write++;
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else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
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x->mtl_tx_fifo_read_ctrl_wait++;
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else if (trcsts == MTL_DEBUG_TRCSTS_READ)
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x->mtl_tx_fifo_read_ctrl_read++;
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else
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x->mtl_tx_fifo_read_ctrl_idle++;
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}
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if (value & MTL_DEBUG_TXPAUSED)
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x->mac_tx_in_pause++;
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value = readl(ioaddr + MTL_CHAN_RX_DEBUG(STMMAC_CHAN0));
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if (value & MTL_DEBUG_RXFSTS_MASK) {
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u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
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>> MTL_DEBUG_RRCSTS_SHIFT;
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if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
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x->mtl_rx_fifo_fill_level_full++;
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else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
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x->mtl_rx_fifo_fill_above_thresh++;
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else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
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x->mtl_rx_fifo_fill_below_thresh++;
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else
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x->mtl_rx_fifo_fill_level_empty++;
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}
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if (value & MTL_DEBUG_RRCSTS_MASK) {
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u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
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MTL_DEBUG_RRCSTS_SHIFT;
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if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
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x->mtl_rx_fifo_read_ctrl_flush++;
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else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
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x->mtl_rx_fifo_read_ctrl_read_data++;
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else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
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x->mtl_rx_fifo_read_ctrl_status++;
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else
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x->mtl_rx_fifo_read_ctrl_idle++;
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}
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if (value & MTL_DEBUG_RWCSTS)
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x->mtl_rx_fifo_ctrl_active++;
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/* GMAC debug */
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value = readl(ioaddr + GMAC_DEBUG);
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if (value & GMAC_DEBUG_TFCSTS_MASK) {
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u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
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>> GMAC_DEBUG_TFCSTS_SHIFT;
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if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
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||||
x->mac_tx_frame_ctrl_xfer++;
|
||||
else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
|
||||
x->mac_tx_frame_ctrl_pause++;
|
||||
else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
|
||||
x->mac_tx_frame_ctrl_wait++;
|
||||
else
|
||||
x->mac_tx_frame_ctrl_idle++;
|
||||
}
|
||||
if (value & GMAC_DEBUG_TPESTS)
|
||||
x->mac_gmii_tx_proto_engine++;
|
||||
if (value & GMAC_DEBUG_RFCFCSTS_MASK)
|
||||
x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
|
||||
>> GMAC_DEBUG_RFCFCSTS_SHIFT;
|
||||
if (value & GMAC_DEBUG_RPESTS)
|
||||
x->mac_gmii_rx_proto_engine++;
|
||||
}
|
||||
|
||||
static const struct stmmac_ops dwmac4_ops = {
|
||||
.core_init = dwmac4_core_init,
|
||||
.rx_ipc = dwmac4_rx_ipc_enable,
|
||||
.dump_regs = dwmac4_dump_regs,
|
||||
.host_irq_status = dwmac4_irq_status,
|
||||
.flow_ctrl = dwmac4_flow_ctrl,
|
||||
.pmt = dwmac4_pmt,
|
||||
.set_umac_addr = dwmac4_set_umac_addr,
|
||||
.get_umac_addr = dwmac4_get_umac_addr,
|
||||
.ctrl_ane = dwmac4_ctrl_ane,
|
||||
.get_adv = dwmac4_get_adv,
|
||||
.debug = dwmac4_debug,
|
||||
.set_filter = dwmac4_set_filter,
|
||||
};
|
||||
|
||||
struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins,
|
||||
int perfect_uc_entries, int *synopsys_id)
|
||||
{
|
||||
struct mac_device_info *mac;
|
||||
u32 hwid = readl(ioaddr + GMAC_VERSION);
|
||||
|
||||
mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
|
||||
if (!mac)
|
||||
return NULL;
|
||||
|
||||
mac->pcsr = ioaddr;
|
||||
mac->multicast_filter_bins = mcbins;
|
||||
mac->unicast_filter_entries = perfect_uc_entries;
|
||||
mac->mcast_bits_log2 = 0;
|
||||
|
||||
if (mac->multicast_filter_bins)
|
||||
mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
|
||||
|
||||
mac->mac = &dwmac4_ops;
|
||||
|
||||
mac->link.port = GMAC_CONFIG_PS;
|
||||
mac->link.duplex = GMAC_CONFIG_DM;
|
||||
mac->link.speed = GMAC_CONFIG_FES;
|
||||
mac->mii.addr = GMAC_MDIO_ADDR;
|
||||
mac->mii.data = GMAC_MDIO_DATA;
|
||||
|
||||
/* Get and dump the chip ID */
|
||||
*synopsys_id = stmmac_get_synopsys_id(hwid);
|
||||
|
||||
if (*synopsys_id > DWMAC_CORE_4_00)
|
||||
mac->dma = &dwmac410_dma_ops;
|
||||
else
|
||||
mac->dma = &dwmac4_dma_ops;
|
||||
|
||||
return mac;
|
||||
}
|
||||
Loading…
Reference in New Issue