spi/omap2_mcspi: add turbo mode support
Turbo mode allows to read data to shift register when rx-buffer is full thus improving the perfomance. This feature is available for RX-only mode. In PIO turbo mode when the penultimate word is available in RX-buffer the controller should be disabled before reading data to prevent the next transaction triggering. The controller itself handles the last word to be correctly loaded to shift-register and then transferred to RX-buffer. The turbo mode is enabled by setting turbo_mode parameter to 1. This parameter is a part of omap2_mcspi_device_config structure which is passed through the spi_device controller_data pointer. Signed-off-by: Roman Tereshonkov <roman.tereshonkov@nokia.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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8b66c13474
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@ -38,7 +38,7 @@
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#include <plat/dma.h>
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#include <plat/clock.h>
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#include <plat/mcspi.h>
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#define OMAP2_MCSPI_MAX_FREQ 48000000
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@ -229,6 +229,8 @@ static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
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l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
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mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
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/* Flash post-writes */
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mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
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}
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static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
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@ -303,11 +305,14 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
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unsigned int count, c;
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unsigned long base, tx_reg, rx_reg;
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int word_len, data_type, element_count;
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int elements;
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u32 l;
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u8 * rx;
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const u8 * tx;
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mcspi = spi_master_get_devdata(spi->master);
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mcspi_dma = &mcspi->dma_channels[spi->chip_select];
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l = mcspi_cached_chconf0(spi);
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count = xfer->len;
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c = count;
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@ -346,8 +351,12 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
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}
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if (rx != NULL) {
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elements = element_count - 1;
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if (l & OMAP2_MCSPI_CHCONF_TURBO)
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elements--;
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omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
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data_type, element_count - 1, 1,
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data_type, elements, 1,
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OMAP_DMA_SYNC_ELEMENT,
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mcspi_dma->dma_rx_sync_dev, 1);
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@ -379,17 +388,42 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
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wait_for_completion(&mcspi_dma->dma_rx_completion);
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dma_unmap_single(NULL, xfer->rx_dma, count, DMA_FROM_DEVICE);
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omap2_mcspi_set_enable(spi, 0);
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if (l & OMAP2_MCSPI_CHCONF_TURBO) {
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if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
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& OMAP2_MCSPI_CHSTAT_RXS)) {
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u32 w;
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w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
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if (word_len <= 8)
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((u8 *)xfer->rx_buf)[elements++] = w;
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else if (word_len <= 16)
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((u16 *)xfer->rx_buf)[elements++] = w;
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else /* word_len <= 32 */
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((u32 *)xfer->rx_buf)[elements++] = w;
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} else {
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dev_err(&spi->dev,
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"DMA RX penultimate word empty");
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count -= (word_len <= 8) ? 2 :
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(word_len <= 16) ? 4 :
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/* word_len <= 32 */ 8;
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omap2_mcspi_set_enable(spi, 1);
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return count;
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}
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}
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if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
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& OMAP2_MCSPI_CHSTAT_RXS)) {
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u32 w;
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w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
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if (word_len <= 8)
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((u8 *)xfer->rx_buf)[element_count - 1] = w;
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((u8 *)xfer->rx_buf)[elements] = w;
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else if (word_len <= 16)
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((u16 *)xfer->rx_buf)[element_count - 1] = w;
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((u16 *)xfer->rx_buf)[elements] = w;
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else /* word_len <= 32 */
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((u32 *)xfer->rx_buf)[element_count - 1] = w;
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((u32 *)xfer->rx_buf)[elements] = w;
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} else {
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dev_err(&spi->dev, "DMA RX last word empty");
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count -= (word_len <= 8) ? 1 :
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@ -433,7 +467,6 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
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word_len = cs->word_len;
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l = mcspi_cached_chconf0(spi);
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l &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
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/* We store the pre-calculated register addresses on stack to speed
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* up the transfer loop. */
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@ -468,11 +501,26 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
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dev_err(&spi->dev, "RXS timed out\n");
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goto out;
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}
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/* prevent last RX_ONLY read from triggering
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* more word i/o: switch to rx+tx
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*/
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if (c == 0 && tx == NULL)
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mcspi_write_chconf0(spi, l);
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if (c == 1 && tx == NULL &&
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(l & OMAP2_MCSPI_CHCONF_TURBO)) {
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omap2_mcspi_set_enable(spi, 0);
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*rx++ = __raw_readl(rx_reg);
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#ifdef VERBOSE
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dev_dbg(&spi->dev, "read-%d %02x\n",
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word_len, *(rx - 1));
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#endif
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if (mcspi_wait_for_reg_bit(chstat_reg,
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OMAP2_MCSPI_CHSTAT_RXS) < 0) {
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dev_err(&spi->dev,
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"RXS timed out\n");
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goto out;
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}
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c = 0;
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} else if (c == 0 && tx == NULL) {
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omap2_mcspi_set_enable(spi, 0);
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}
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*rx++ = __raw_readl(rx_reg);
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#ifdef VERBOSE
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dev_dbg(&spi->dev, "read-%d %02x\n",
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@ -506,11 +554,26 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
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dev_err(&spi->dev, "RXS timed out\n");
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goto out;
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}
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/* prevent last RX_ONLY read from triggering
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* more word i/o: switch to rx+tx
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*/
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if (c == 0 && tx == NULL)
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mcspi_write_chconf0(spi, l);
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if (c == 2 && tx == NULL &&
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(l & OMAP2_MCSPI_CHCONF_TURBO)) {
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omap2_mcspi_set_enable(spi, 0);
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*rx++ = __raw_readl(rx_reg);
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#ifdef VERBOSE
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dev_dbg(&spi->dev, "read-%d %04x\n",
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word_len, *(rx - 1));
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#endif
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if (mcspi_wait_for_reg_bit(chstat_reg,
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OMAP2_MCSPI_CHSTAT_RXS) < 0) {
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dev_err(&spi->dev,
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"RXS timed out\n");
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goto out;
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}
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c = 0;
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} else if (c == 0 && tx == NULL) {
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omap2_mcspi_set_enable(spi, 0);
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}
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*rx++ = __raw_readl(rx_reg);
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#ifdef VERBOSE
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dev_dbg(&spi->dev, "read-%d %04x\n",
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@ -544,11 +607,26 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
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dev_err(&spi->dev, "RXS timed out\n");
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goto out;
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}
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/* prevent last RX_ONLY read from triggering
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* more word i/o: switch to rx+tx
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*/
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if (c == 0 && tx == NULL)
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mcspi_write_chconf0(spi, l);
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if (c == 4 && tx == NULL &&
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(l & OMAP2_MCSPI_CHCONF_TURBO)) {
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omap2_mcspi_set_enable(spi, 0);
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*rx++ = __raw_readl(rx_reg);
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#ifdef VERBOSE
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dev_dbg(&spi->dev, "read-%d %08x\n",
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word_len, *(rx - 1));
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#endif
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if (mcspi_wait_for_reg_bit(chstat_reg,
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OMAP2_MCSPI_CHSTAT_RXS) < 0) {
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dev_err(&spi->dev,
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"RXS timed out\n");
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goto out;
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}
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c = 0;
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} else if (c == 0 && tx == NULL) {
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omap2_mcspi_set_enable(spi, 0);
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}
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*rx++ = __raw_readl(rx_reg);
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#ifdef VERBOSE
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dev_dbg(&spi->dev, "read-%d %08x\n",
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dev_err(&spi->dev, "EOT timed out\n");
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}
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out:
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omap2_mcspi_set_enable(spi, 1);
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return count - c;
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}
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@ -797,6 +876,7 @@ static void omap2_mcspi_work(struct work_struct *work)
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struct spi_transfer *t = NULL;
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int cs_active = 0;
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struct omap2_mcspi_cs *cs;
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struct omap2_mcspi_device_config *cd;
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int par_override = 0;
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int status = 0;
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u32 chconf;
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@ -809,6 +889,7 @@ static void omap2_mcspi_work(struct work_struct *work)
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spi = m->spi;
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cs = spi->controller_state;
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cd = spi->controller_data;
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omap2_mcspi_set_enable(spi, 1);
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list_for_each_entry(t, &m->transfers, transfer_list) {
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@ -832,10 +913,19 @@ static void omap2_mcspi_work(struct work_struct *work)
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chconf = mcspi_cached_chconf0(spi);
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chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
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chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
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if (t->tx_buf == NULL)
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chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
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else if (t->rx_buf == NULL)
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chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
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if (cd && cd->turbo_mode && t->tx_buf == NULL) {
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/* Turbo mode is for more than one word */
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if (t->len > ((cs->word_len + 7) >> 3))
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chconf |= OMAP2_MCSPI_CHCONF_TURBO;
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}
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mcspi_write_chconf0(spi, chconf);
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if (t->len) {
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