ARM: OMAP: ctrl: Fix CONTROL_DSIPHY register fields
Fix the shift and mask macros for DSIx_PPID fields in CONTROL_DSIPHY. The OMAP4430 Public TRM vV has these fields mentioned correctly. Signed-off-by: Archit Taneja <archit@ti.com> Acked-by: Benoit Cousson <b-cousson@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
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@ -941,10 +941,10 @@
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#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
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#define OMAP4_DSI1_LANEENABLE_SHIFT 24
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#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
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#define OMAP4_DSI1_PIPD_SHIFT 19
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#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
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#define OMAP4_DSI2_PIPD_SHIFT 14
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#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
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#define OMAP4_DSI2_PIPD_SHIFT 19
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#define OMAP4_DSI2_PIPD_MASK (0x1f << 19)
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#define OMAP4_DSI1_PIPD_SHIFT 14
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#define OMAP4_DSI1_PIPD_MASK (0x1f << 14)
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/* CONTROL_MCBSPLP */
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#define OMAP4_ALBCTRLRX_FSX_SHIFT 31
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