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Pin control fixes for v5.18: 

- Fix some register offsets on Intel Alderlake
 
 - Fix the order the UFS and SDC pins on Qualcomm SM6350
 
 - Fix a build error in Mediatek Moore.
 
 - Fix a pin function table in the Sunplus SP7021.
 
 - Fix some Kconfig and static keywords on the Samsung
   Tesla FSD SoC.
 
 - Fix up the EOI function for edge triggered IRQs and keep
   the block clock enabled for level IRQs in the
   STM32 driver.
 
 - Fix some bits and order in the Rockchip RK3308 driver.
 
 - Handle the errorpath in the Pistachio driver probe()
   properly.
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Merge tag 'pinctrl-v5.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:

 - Fix some register offsets on Intel Alderlake

 - Fix the order the UFS and SDC pins on Qualcomm SM6350

 - Fix a build error in Mediatek Moore.

 - Fix a pin function table in the Sunplus SP7021.

 - Fix some Kconfig and static keywords on the Samsung Tesla FSD SoC.

 - Fix up the EOI function for edge triggered IRQs and keep the block
   clock enabled for level IRQs in the STM32 driver.

 - Fix some bits and order in the Rockchip RK3308 driver.

 - Handle the errorpath in the Pistachio driver probe() properly.

* tag 'pinctrl-v5.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: pistachio: fix use of irq_of_parse_and_map()
  pinctrl: stm32: Keep pinctrl block clock enabled when LEVEL IRQ requested
  pinctrl: rockchip: sort the rk3308_mux_recalced_data entries
  pinctrl: rockchip: fix RK3308 pinmux bits
  pinctrl: stm32: Do not call stm32_gpio_get() for edge triggered IRQs in EOI
  pinctrl: Fix an error in pin-function table of SP7021
  pinctrl: samsung: fix missing GPIOLIB on ARM64 Exynos config
  pinctrl: mediatek: moore: Fix build error
  pinctrl: qcom: sm6350: fix order of UFS & SDC pins
  pinctrl: alderlake: Fix register offsets for ADL-N variant
  pinctrl: samsung: staticize fsd_pin_ctrl
This commit is contained in:
Linus Torvalds 2022-04-26 16:34:11 -07:00
parent cf424ef014 0c9843a74a
commit 46cf2c613f
10 changed files with 131 additions and 72 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/mach-exynos/Kconfig
View File

@ -17,7 +17,6 @@ menuconfig ARCH_EXYNOS
select EXYNOS_PMU
select EXYNOS_SROM
select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS
select GPIOLIB
select HAVE_ARM_ARCH_TIMER if ARCH_EXYNOS5
select HAVE_ARM_SCU if SMP
select PINCTRL

60
drivers/pinctrl/intel/pinctrl-alderlake.c
View File

@ -14,11 +14,17 @@
#include "pinctrl-intel.h"
#define ADL_PAD_OWN 0x0a0
#define ADL_PADCFGLOCK 0x110
#define ADL_HOSTSW_OWN 0x150
#define ADL_GPI_IS 0x200
#define ADL_GPI_IE 0x220
#define ADL_N_PAD_OWN 0x020
#define ADL_N_PADCFGLOCK 0x080
#define ADL_N_HOSTSW_OWN 0x0b0
#define ADL_N_GPI_IS 0x100
#define ADL_N_GPI_IE 0x120
#define ADL_S_PAD_OWN 0x0a0
#define ADL_S_PADCFGLOCK 0x110
#define ADL_S_HOSTSW_OWN 0x150
#define ADL_S_GPI_IS 0x200
#define ADL_S_GPI_IE 0x220
#define ADL_GPP(r, s, e, g) \
{ \
@ -28,14 +34,28 @@
.gpio_base = (g), \
}
#define ADL_COMMUNITY(b, s, e, g) \
#define ADL_N_COMMUNITY(b, s, e, g) \
{ \
.barno = (b), \
.padown_offset = ADL_PAD_OWN, \
.padcfglock_offset = ADL_PADCFGLOCK, \
.hostown_offset = ADL_HOSTSW_OWN, \
.is_offset = ADL_GPI_IS, \
.ie_offset = ADL_GPI_IE, \
.padown_offset = ADL_N_PAD_OWN, \
.padcfglock_offset = ADL_N_PADCFGLOCK, \
.hostown_offset = ADL_N_HOSTSW_OWN, \
.is_offset = ADL_N_GPI_IS, \
.ie_offset = ADL_N_GPI_IE, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
.gpps = (g), \
.ngpps = ARRAY_SIZE(g), \
}
#define ADL_S_COMMUNITY(b, s, e, g) \
{ \
.barno = (b), \
.padown_offset = ADL_S_PAD_OWN, \
.padcfglock_offset = ADL_S_PADCFGLOCK, \
.hostown_offset = ADL_S_HOSTSW_OWN, \
.is_offset = ADL_S_GPI_IS, \
.ie_offset = ADL_S_GPI_IE, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
.gpps = (g), \
@ -342,10 +362,10 @@ static const struct intel_padgroup adln_community5_gpps[] = {
};
static const struct intel_community adln_communities[] = {
ADL_COMMUNITY(0, 0, 66, adln_community0_gpps),
ADL_COMMUNITY(1, 67, 168, adln_community1_gpps),
ADL_COMMUNITY(2, 169, 248, adln_community4_gpps),
ADL_COMMUNITY(3, 249, 256, adln_community5_gpps),
ADL_N_COMMUNITY(0, 0, 66, adln_community0_gpps),
ADL_N_COMMUNITY(1, 67, 168, adln_community1_gpps),
ADL_N_COMMUNITY(2, 169, 248, adln_community4_gpps),
ADL_N_COMMUNITY(3, 249, 256, adln_community5_gpps),
};
static const struct intel_pinctrl_soc_data adln_soc_data = {
@ -713,11 +733,11 @@ static const struct intel_padgroup adls_community5_gpps[] = {
};
static const struct intel_community adls_communities[] = {
ADL_COMMUNITY(0, 0, 94, adls_community0_gpps),
ADL_COMMUNITY(1, 95, 150, adls_community1_gpps),
ADL_COMMUNITY(2, 151, 199, adls_community3_gpps),
ADL_COMMUNITY(3, 200, 269, adls_community4_gpps),
ADL_COMMUNITY(4, 270, 303, adls_community5_gpps),
ADL_S_COMMUNITY(0, 0, 94, adls_community0_gpps),
ADL_S_COMMUNITY(1, 95, 150, adls_community1_gpps),
ADL_S_COMMUNITY(2, 151, 199, adls_community3_gpps),
ADL_S_COMMUNITY(3, 200, 269, adls_community4_gpps),
ADL_S_COMMUNITY(4, 270, 303, adls_community5_gpps),
};
static const struct intel_pinctrl_soc_data adls_soc_data = {

1
drivers/pinctrl/mediatek/Kconfig
View File

@ -30,6 +30,7 @@ config PINCTRL_MTK_MOORE
select GENERIC_PINMUX_FUNCTIONS
select GPIOLIB
select OF_GPIO
select EINT_MTK
select PINCTRL_MTK_V2
config PINCTRL_MTK_PARIS

6
drivers/pinctrl/pinctrl-pistachio.c
View File

@ -1374,10 +1374,10 @@ static int pistachio_gpio_register(struct pistachio_pinctrl *pctl)
}
irq = irq_of_parse_and_map(child, 0);
if (irq < 0) {
dev_err(pctl->dev, "No IRQ for bank %u: %d\n", i, irq);
if (!irq) {
dev_err(pctl->dev, "No IRQ for bank %u\n", i);
of_node_put(child);
ret = irq;
ret = -EINVAL;
goto err;
}

75
drivers/pinctrl/pinctrl-rockchip.c
View File

@ -457,95 +457,110 @@ static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
{
/* gpio1b6_sel */
.num = 1,
.pin = 14,
.reg = 0x28,
.bit = 12,
.mask = 0xf
}, {
/* gpio1b7_sel */
.num = 1,
.pin = 15,
.reg = 0x2c,
.bit = 0,
.mask = 0x3
}, {
/* gpio1c2_sel */
.num = 1,
.pin = 18,
.reg = 0x30,
.bit = 4,
.mask = 0xf
}, {
/* gpio1c3_sel */
.num = 1,
.pin = 19,
.reg = 0x30,
.bit = 8,
.mask = 0xf
}, {
/* gpio1c4_sel */
.num = 1,
.pin = 20,
.reg = 0x30,
.bit = 12,
.mask = 0xf
}, {
/* gpio1c5_sel */
.num = 1,
.pin = 21,
.reg = 0x34,
.bit = 0,
.mask = 0xf
}, {
/* gpio1c6_sel */
.num = 1,
.pin = 22,
.reg = 0x34,
.bit = 4,
.mask = 0xf
}, {
/* gpio1c7_sel */
.num = 1,
.pin = 23,
.reg = 0x34,
.bit = 8,
.mask = 0xf
}, {
/* gpio2a2_sel */
.num = 2,
.pin = 2,
.reg = 0x40,
.bit = 4,
.mask = 0x3
}, {
/* gpio2a3_sel */
.num = 2,
.pin = 3,
.reg = 0x40,
.bit = 6,
.mask = 0x3
}, {
/* gpio2c0_sel */
.num = 2,
.pin = 16,
.reg = 0x50,
.bit = 0,
.mask = 0x3
}, {
/* gpio3b2_sel */
.num = 3,
.pin = 10,
.reg = 0x68,
.bit = 4,
.mask = 0x3
}, {
/* gpio3b3_sel */
.num = 3,
.pin = 11,
.reg = 0x68,
.bit = 6,
.mask = 0x3
}, {
/* gpio3b4_sel */
.num = 3,
.pin = 12,
.reg = 0x68,
.bit = 8,
.mask = 0xf
}, {
/* gpio3b5_sel */
.num = 3,
.pin = 13,
.reg = 0x68,
.bit = 12,
.mask = 0xf
}, {
.num = 2,
.pin = 2,
.reg = 0x608,
.bit = 0,
.mask = 0x7
}, {
.num = 2,
.pin = 3,
.reg = 0x608,
.bit = 4,
.mask = 0x7
}, {
.num = 2,
.pin = 16,
.reg = 0x610,
.bit = 8,
.mask = 0x7
}, {
.num = 3,
.pin = 10,
.reg = 0x610,
.bit = 0,
.mask = 0x7
}, {
.num = 3,
.pin = 11,
.reg = 0x610,
.bit = 4,
.mask = 0x7
},
};

16
drivers/pinctrl/qcom/pinctrl-sm6350.c
View File

@ -264,14 +264,14 @@ static const struct pinctrl_pin_desc sm6350_pins[] = {
PINCTRL_PIN(153, "GPIO_153"),
PINCTRL_PIN(154, "GPIO_154"),
PINCTRL_PIN(155, "GPIO_155"),
PINCTRL_PIN(156, "SDC1_RCLK"),
PINCTRL_PIN(157, "SDC1_CLK"),
PINCTRL_PIN(158, "SDC1_CMD"),
PINCTRL_PIN(159, "SDC1_DATA"),
PINCTRL_PIN(160, "SDC2_CLK"),
PINCTRL_PIN(161, "SDC2_CMD"),
PINCTRL_PIN(162, "SDC2_DATA"),
PINCTRL_PIN(163, "UFS_RESET"),
PINCTRL_PIN(156, "UFS_RESET"),
PINCTRL_PIN(157, "SDC1_RCLK"),
PINCTRL_PIN(158, "SDC1_CLK"),
PINCTRL_PIN(159, "SDC1_CMD"),
PINCTRL_PIN(160, "SDC1_DATA"),
PINCTRL_PIN(161, "SDC2_CLK"),
PINCTRL_PIN(162, "SDC2_CMD"),
PINCTRL_PIN(163, "SDC2_DATA"),
};
#define DECLARE_MSM_GPIO_PINS(pin) \

11
drivers/pinctrl/samsung/Kconfig
View File

@ -4,14 +4,13 @@
#
config PINCTRL_SAMSUNG
bool
depends on OF_GPIO
select GPIOLIB
select PINMUX
select PINCONF
config PINCTRL_EXYNOS
bool "Pinctrl common driver part for Samsung Exynos SoCs"
depends on OF_GPIO
depends on ARCH_EXYNOS || ARCH_S5PV210 || COMPILE_TEST
depends on ARCH_EXYNOS || ARCH_S5PV210 || (COMPILE_TEST && OF)
select PINCTRL_SAMSUNG
select PINCTRL_EXYNOS_ARM if ARM && (ARCH_EXYNOS || ARCH_S5PV210)
select PINCTRL_EXYNOS_ARM64 if ARM64 && ARCH_EXYNOS
@ -26,12 +25,10 @@ config PINCTRL_EXYNOS_ARM64
config PINCTRL_S3C24XX
bool "Samsung S3C24XX SoC pinctrl driver"
depends on OF_GPIO
depends on ARCH_S3C24XX || COMPILE_TEST
depends on ARCH_S3C24XX || (COMPILE_TEST && OF)
select PINCTRL_SAMSUNG
config PINCTRL_S3C64XX
bool "Samsung S3C64XX SoC pinctrl driver"
depends on OF_GPIO
depends on ARCH_S3C64XX || COMPILE_TEST
depends on ARCH_S3C64XX || (COMPILE_TEST && OF)
select PINCTRL_SAMSUNG

2
drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
View File

@ -770,7 +770,7 @@ static const struct samsung_pin_bank_data fsd_pin_banks2[] __initconst = {
EXYNOS850_PIN_BANK_EINTN(3, 0x00, "gpq0"),
};
const struct samsung_pin_ctrl fsd_pin_ctrl[] __initconst = {
static const struct samsung_pin_ctrl fsd_pin_ctrl[] __initconst = {
{
/* pin-controller instance 0 FSYS0 data */
.pin_banks = fsd_pin_banks0,

23
drivers/pinctrl/stm32/pinctrl-stm32.c
View File

@ -225,6 +225,13 @@ static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
pinctrl_gpio_free(chip->base + offset);
}
static int stm32_gpio_get_noclk(struct gpio_chip *chip, unsigned int offset)
{
struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
}
static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
@ -232,7 +239,7 @@ static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
clk_enable(bank->clk);
ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
ret = stm32_gpio_get_noclk(chip, offset);
clk_disable(bank->clk);
@ -311,8 +318,12 @@ static void stm32_gpio_irq_trigger(struct irq_data *d)
struct stm32_gpio_bank *bank = d->domain->host_data;
int level;
/* Do not access the GPIO if this is not LEVEL triggered IRQ. */
if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK))
return;
/* If level interrupt type then retrig */
level = stm32_gpio_get(&bank->gpio_chip, d->hwirq);
level = stm32_gpio_get_noclk(&bank->gpio_chip, d->hwirq);
if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||
(level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))
irq_chip_retrigger_hierarchy(d);
@ -354,6 +365,7 @@ static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
{
struct stm32_gpio_bank *bank = irq_data->domain->host_data;
struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
unsigned long flags;
int ret;
ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
@ -367,6 +379,10 @@ static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
return ret;
}
flags = irqd_get_trigger_type(irq_data);
if (flags & IRQ_TYPE_LEVEL_MASK)
clk_enable(bank->clk);
return 0;
}
@ -374,6 +390,9 @@ static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
{
struct stm32_gpio_bank *bank = irq_data->domain->host_data;
if (bank->irq_type[irq_data->hwirq] & IRQ_TYPE_LEVEL_MASK)
clk_disable(bank->clk);
gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
}

8
drivers/pinctrl/sunplus/sppctl_sp7021.c
View File

@ -419,7 +419,15 @@ static const struct sppctl_grp sp7021grps_prbp[] = {
EGRP("PROBE_PORT2", 2, pins_prp2),
};
/*
* Due to compatible reason, the first valid item should start at the third
* position of the array. Please keep the first two items of the table
* no use (dummy).
*/
const struct sppctl_func sppctl_list_funcs[] = {
FNCN("", pinmux_type_fpmx, 0x00, 0, 0),
FNCN("", pinmux_type_fpmx, 0x00, 0, 0),
FNCN("L2SW_CLK_OUT", pinmux_type_fpmx, 0x00, 0, 7),
FNCN("L2SW_MAC_SMI_MDC", pinmux_type_fpmx, 0x00, 8, 7),
FNCN("L2SW_LED_FLASH0", pinmux_type_fpmx, 0x01, 0, 7),