gpio/langwell: convert to use irq_domain
irq_domain already provides a facility to translate from hardware IRQ numbers to Linux IRQ numbers so use that instead of open-coding the logic in the driver. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This commit is contained in:
Mika Westerberg
Grant Likely
parent
7b96c68622
commit
465f2bd459
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@ -404,6 +404,7 @@ config GPIO_BT8XX
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config GPIO_LANGWELL
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bool "Intel Langwell/Penwell GPIO support"
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depends on PCI && X86
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select IRQ_DOMAIN
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help
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Say Y here to support Intel Langwell/Penwell GPIO.
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@ -36,6 +36,7 @@
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#include <linux/gpio.h>
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#include <linux/slab.h>
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#include <linux/pm_runtime.h>
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#include <linux/irqdomain.h>
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/*
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* Langwell chip has 64 pins and thus there are 2 32bit registers to control
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@ -66,8 +67,8 @@ struct lnw_gpio {
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struct gpio_chip chip;
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void *reg_base;
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spinlock_t lock;
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unsigned irq_base;
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struct pci_dev *pdev;
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struct irq_domain *domain;
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};
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static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
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@ -176,13 +177,13 @@ static int lnw_gpio_direction_output(struct gpio_chip *chip,
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static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
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return lnw->irq_base + offset;
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return irq_create_mapping(lnw->domain, offset);
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}
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static int lnw_irq_type(struct irq_data *d, unsigned type)
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{
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struct lnw_gpio *lnw = irq_data_get_irq_chip_data(d);
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u32 gpio = d->irq - lnw->irq_base;
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u32 gpio = irqd_to_hwirq(d);
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unsigned long flags;
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u32 value;
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void __iomem *grer = gpio_reg(&lnw->chip, gpio, GRER);
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@ -256,7 +257,8 @@ static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
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pending &= ~mask;
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/* Clear before handling so we can't lose an edge */
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writel(mask, gedr);
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generic_handle_irq(lnw->irq_base + base + gpio);
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generic_handle_irq(irq_find_mapping(lnw->domain,
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base + gpio));
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}
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}
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@ -281,6 +283,24 @@ static void lnw_irq_init_hw(struct lnw_gpio *lnw)
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}
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}
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static int lnw_gpio_irq_map(struct irq_domain *d, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct lnw_gpio *lnw = d->host_data;
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irq_set_chip_and_handler_name(virq, &lnw_irqchip, handle_simple_irq,
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"demux");
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irq_set_chip_data(virq, lnw);
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irq_set_irq_type(virq, IRQ_TYPE_NONE);
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return 0;
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}
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static const struct irq_domain_ops lnw_gpio_irq_ops = {
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.map = lnw_gpio_irq_map,
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.xlate = irq_domain_xlate_twocell,
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};
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#ifdef CONFIG_PM
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static int lnw_gpio_runtime_resume(struct device *dev)
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{
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@ -318,10 +338,8 @@ static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
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const struct pci_device_id *id)
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{
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void *base;
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int i;
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resource_size_t start, len;
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struct lnw_gpio *lnw;
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u32 irq_base;
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u32 gpio_base;
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int retval = 0;
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int ngpio = id->driver_data;
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@ -335,7 +353,7 @@ static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
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dev_err(&pdev->dev, "error requesting resources\n");
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goto err2;
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}
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/* get the irq_base from bar1 */
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/* get the gpio_base from bar1 */
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start = pci_resource_start(pdev, 1);
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len = pci_resource_len(pdev, 1);
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base = ioremap_nocache(start, len);
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@ -343,7 +361,6 @@ static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
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dev_err(&pdev->dev, "error mapping bar1\n");
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goto err3;
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}
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irq_base = *(u32 *)base;
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gpio_base = *((u32 *)base + 1);
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/* release the IO mapping, since we already get the info from bar1 */
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iounmap(base);
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@ -364,12 +381,10 @@ static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
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goto err3;
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}
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retval = irq_alloc_descs(-1, irq_base, ngpio, 0);
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if (retval < 0) {
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dev_err(&pdev->dev, "can't allocate IRQ descs\n");
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lnw->domain = irq_domain_add_linear(pdev->dev.of_node, ngpio,
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&lnw_gpio_irq_ops, lnw);
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if (!lnw->domain)
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goto err3;
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}
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lnw->irq_base = retval;
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lnw->reg_base = base;
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lnw->chip.label = dev_name(&pdev->dev);
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@ -387,18 +402,13 @@ static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
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retval = gpiochip_add(&lnw->chip);
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if (retval) {
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dev_err(&pdev->dev, "langwell gpiochip_add error %d\n", retval);
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goto err4;
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goto err3;
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}
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lnw_irq_init_hw(lnw);
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irq_set_handler_data(pdev->irq, lnw);
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irq_set_chained_handler(pdev->irq, lnw_irq_handler);
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for (i = 0; i < lnw->chip.ngpio; i++) {
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irq_set_chip_and_handler_name(i + lnw->irq_base, &lnw_irqchip,
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handle_simple_irq, "demux");
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irq_set_chip_data(i + lnw->irq_base, lnw);
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}
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spin_lock_init(&lnw->lock);
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@ -407,8 +417,6 @@ static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
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return 0;
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err4:
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irq_free_descs(lnw->irq_base, ngpio);
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err3:
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pci_release_regions(pdev);
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err2:
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