r8169: add a new chip for RTL8411
Add a new chip for RTL8411 series. Signed-off-by: Hayes Wang <hayeswang@realtek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
hayeswang
David S. Miller
parent
0e00fd4794
commit
45dd95c443
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@ -46,6 +46,7 @@
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#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
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#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
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#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
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#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
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#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
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#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
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#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
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@ -144,6 +145,7 @@ enum mac_version {
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RTL_GIGA_MAC_VER_41,
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RTL_GIGA_MAC_VER_42,
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RTL_GIGA_MAC_VER_43,
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RTL_GIGA_MAC_VER_44,
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RTL_GIGA_MAC_NONE = 0xff,
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};
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@ -276,6 +278,9 @@ static const struct {
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[RTL_GIGA_MAC_VER_43] =
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_R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
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JUMBO_1K, true),
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[RTL_GIGA_MAC_VER_44] =
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_R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
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JUMBO_9K, false),
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};
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#undef _R
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@ -394,6 +399,7 @@ enum rtl8168_8101_registers {
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#define CSIAR_FUNC_CARD 0x00000000
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#define CSIAR_FUNC_SDIO 0x00010000
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#define CSIAR_FUNC_NIC 0x00020000
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#define CSIAR_FUNC_NIC2 0x00010000
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PMCH = 0x6f,
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EPHYAR = 0x80,
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#define EPHYAR_FLAG 0x80000000
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@ -826,6 +832,7 @@ MODULE_FIRMWARE(FIRMWARE_8168F_1);
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MODULE_FIRMWARE(FIRMWARE_8168F_2);
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MODULE_FIRMWARE(FIRMWARE_8402_1);
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MODULE_FIRMWARE(FIRMWARE_8411_1);
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MODULE_FIRMWARE(FIRMWARE_8411_2);
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MODULE_FIRMWARE(FIRMWARE_8106E_1);
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MODULE_FIRMWARE(FIRMWARE_8106E_2);
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MODULE_FIRMWARE(FIRMWARE_8168G_2);
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@ -2051,6 +2058,7 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp,
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int mac_version;
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} mac_info[] = {
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/* 8168G family. */
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{ 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
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{ 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
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{ 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
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{ 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
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@ -3651,6 +3659,7 @@ static void rtl_hw_phy_config(struct net_device *dev)
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break;
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case RTL_GIGA_MAC_VER_42:
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case RTL_GIGA_MAC_VER_43:
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case RTL_GIGA_MAC_VER_44:
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rtl8168g_2_hw_phy_config(tp);
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break;
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@ -3863,6 +3872,7 @@ static void rtl_init_mdio_ops(struct rtl8169_private *tp)
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case RTL_GIGA_MAC_VER_41:
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case RTL_GIGA_MAC_VER_42:
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case RTL_GIGA_MAC_VER_43:
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case RTL_GIGA_MAC_VER_44:
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ops->write = r8168g_mdio_write;
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ops->read = r8168g_mdio_read;
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break;
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@ -3916,6 +3926,7 @@ static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
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case RTL_GIGA_MAC_VER_41:
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case RTL_GIGA_MAC_VER_42:
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case RTL_GIGA_MAC_VER_43:
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case RTL_GIGA_MAC_VER_44:
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RTL_W32(RxConfig, RTL_R32(RxConfig) |
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AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
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break;
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@ -4178,6 +4189,7 @@ static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
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case RTL_GIGA_MAC_VER_40:
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case RTL_GIGA_MAC_VER_41:
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case RTL_GIGA_MAC_VER_42:
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case RTL_GIGA_MAC_VER_44:
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ops->down = r8168_pll_power_down;
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ops->up = r8168_pll_power_up;
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break;
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@ -4224,6 +4236,7 @@ static void rtl_init_rxcfg(struct rtl8169_private *tp)
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case RTL_GIGA_MAC_VER_41:
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case RTL_GIGA_MAC_VER_42:
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case RTL_GIGA_MAC_VER_43:
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case RTL_GIGA_MAC_VER_44:
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RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
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break;
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default:
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@ -4384,6 +4397,7 @@ static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
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case RTL_GIGA_MAC_VER_41:
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case RTL_GIGA_MAC_VER_42:
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case RTL_GIGA_MAC_VER_43:
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case RTL_GIGA_MAC_VER_44:
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default:
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ops->disable = NULL;
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ops->enable = NULL;
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@ -4493,6 +4507,7 @@ static void rtl8169_hw_reset(struct rtl8169_private *tp)
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tp->mac_version == RTL_GIGA_MAC_VER_41 ||
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tp->mac_version == RTL_GIGA_MAC_VER_42 ||
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tp->mac_version == RTL_GIGA_MAC_VER_43 ||
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tp->mac_version == RTL_GIGA_MAC_VER_44 ||
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tp->mac_version == RTL_GIGA_MAC_VER_38) {
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RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
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rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
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@ -4782,6 +4797,29 @@ static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
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RTL_R32(CSIDR) : ~0;
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}
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static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
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{
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void __iomem *ioaddr = tp->mmio_addr;
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RTL_W32(CSIDR, value);
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RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
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CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
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CSIAR_FUNC_NIC2);
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rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
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}
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static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
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{
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void __iomem *ioaddr = tp->mmio_addr;
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RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
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CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
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return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
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RTL_R32(CSIDR) : ~0;
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}
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static void rtl_init_csi_ops(struct rtl8169_private *tp)
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{
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struct csi_ops *ops = &tp->csi_ops;
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@ -4811,6 +4849,11 @@ static void rtl_init_csi_ops(struct rtl8169_private *tp)
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ops->read = r8402_csi_read;
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break;
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case RTL_GIGA_MAC_VER_44:
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ops->write = r8411_csi_write;
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ops->read = r8411_csi_read;
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break;
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default:
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ops->write = r8169_csi_write;
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ops->read = r8169_csi_read;
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@ -5255,6 +5298,25 @@ static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
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rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
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}
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static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
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{
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void __iomem *ioaddr = tp->mmio_addr;
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static const struct ephy_info e_info_8411_2[] = {
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{ 0x00, 0x0000, 0x0008 },
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{ 0x0c, 0x3df0, 0x0200 },
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{ 0x0f, 0xffff, 0x5200 },
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{ 0x19, 0x0020, 0x0000 },
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{ 0x1e, 0x0000, 0x2000 }
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};
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rtl_hw_start_8168g_1(tp);
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/* disable aspm and clock request before access ephy */
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RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
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RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
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rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
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}
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static void rtl_hw_start_8168(struct net_device *dev)
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{
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struct rtl8169_private *tp = netdev_priv(dev);
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@ -5361,6 +5423,10 @@ static void rtl_hw_start_8168(struct net_device *dev)
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rtl_hw_start_8168g_2(tp);
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break;
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case RTL_GIGA_MAC_VER_44:
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rtl_hw_start_8411_2(tp);
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break;
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default:
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printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
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dev->name, tp->mac_version);
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@ -6877,6 +6943,7 @@ static void rtl_hw_initialize(struct rtl8169_private *tp)
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case RTL_GIGA_MAC_VER_41:
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case RTL_GIGA_MAC_VER_42:
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case RTL_GIGA_MAC_VER_43:
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case RTL_GIGA_MAC_VER_44:
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rtl_hw_init_8168g(tp);
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break;
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