[PATCH] skge: make Genesis/Broadcom code work
Rewrite the code for handling the Broadcom PHY to something that works. Remove link polling because Broadcom and Yukon don't need it. When I wrote initial code, didn't have a genesis chipset based board to test, so it was a non-working guess. Signed-off-by: Stephen Hemminger <shemminger@osdl.org>
This commit is contained in:
Stephen Hemminger
Jeff Garzik
parent
31b619c5ab
commit
45bada65c2
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@ -54,7 +54,6 @@
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#define TX_WATCHDOG (5 * HZ)
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#define NAPI_WEIGHT 64
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#define BLINK_HZ (HZ/4)
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#define LINK_POLL_HZ (HZ/10)
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MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
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MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
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@ -96,6 +95,7 @@ static void yukon_init(struct skge_hw *hw, int port);
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static void yukon_reset(struct skge_hw *hw, int port);
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static void genesis_mac_init(struct skge_hw *hw, int port);
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static void genesis_reset(struct skge_hw *hw, int port);
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static void genesis_link_up(struct skge_port *skge);
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static const int txqaddr[] = { Q_XA1, Q_XA2 };
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static const int rxqaddr[] = { Q_R1, Q_R2 };
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@ -950,8 +950,7 @@ static void genesis_init(struct skge_hw *hw)
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static void genesis_reset(struct skge_hw *hw, int port)
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{
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int i;
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u64 zero = 0;
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const u8 zero[8] = { 0 };
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/* reset the statistics module */
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xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
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@ -963,20 +962,100 @@ static void genesis_reset(struct skge_hw *hw, int port)
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/* disable Broadcom PHY IRQ */
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xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
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xm_outhash(hw, port, XM_HSM, (u8 *) &zero);
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for (i = 0; i < 15; i++)
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xm_outaddr(hw, port, XM_EXM(i), (u8 *) &zero);
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xm_outhash(hw, port, XM_SRC_CHK, (u8 *) &zero);
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xm_outhash(hw, port, XM_HSM, zero);
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}
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static void genesis_mac_init(struct skge_hw *hw, int port)
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/* Convert mode to MII values */
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static const u16 phy_pause_map[] = {
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[FLOW_MODE_NONE] = 0,
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[FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
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[FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
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[FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
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};
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/* Check status of Broadcom phy link */
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static void bcom_check_link(struct skge_hw *hw, int port)
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{
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struct skge_port *skge = netdev_priv(hw->dev[port]);
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struct net_device *dev = hw->dev[port];
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struct skge_port *skge = netdev_priv(dev);
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u16 status;
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/* read twice because of latch */
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(void) xm_phy_read(hw, port, PHY_BCOM_STAT);
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status = xm_phy_read(hw, port, PHY_BCOM_STAT);
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pr_debug("bcom_check_link status=0x%x\n", status);
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if ((status & PHY_ST_LSYNC) == 0) {
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u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
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cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
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xm_write16(hw, port, XM_MMU_CMD, cmd);
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/* dummy read to ensure writing */
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(void) xm_read16(hw, port, XM_MMU_CMD);
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if (netif_carrier_ok(dev))
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skge_link_down(skge);
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} else {
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if (skge->autoneg == AUTONEG_ENABLE &&
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(status & PHY_ST_AN_OVER)) {
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u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
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u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
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if (lpa & PHY_B_AN_RF) {
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printk(KERN_NOTICE PFX "%s: remote fault\n",
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dev->name);
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return;
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}
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/* Check Duplex mismatch */
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switch(aux & PHY_B_AS_AN_RES_MSK) {
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case PHY_B_RES_1000FD:
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skge->duplex = DUPLEX_FULL;
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break;
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case PHY_B_RES_1000HD:
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skge->duplex = DUPLEX_HALF;
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break;
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default:
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printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
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dev->name);
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return;
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}
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/* We are using IEEE 802.3z/D5.0 Table 37-4 */
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switch (aux & PHY_B_AS_PAUSE_MSK) {
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case PHY_B_AS_PAUSE_MSK:
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skge->flow_control = FLOW_MODE_SYMMETRIC;
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break;
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case PHY_B_AS_PRR:
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skge->flow_control = FLOW_MODE_REM_SEND;
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break;
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case PHY_B_AS_PRT:
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skge->flow_control = FLOW_MODE_LOC_SEND;
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break;
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default:
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skge->flow_control = FLOW_MODE_NONE;
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}
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skge->speed = SPEED_1000;
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}
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if (!netif_carrier_ok(dev))
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genesis_link_up(skge);
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}
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}
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/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
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* Phy on for 100 or 10Mbit operation
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*/
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static void bcom_phy_init(struct skge_port *skge, int jumbo)
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{
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struct skge_hw *hw = skge->hw;
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int port = skge->port;
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int i;
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u32 r;
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u16 id1;
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u16 ctrl1, ctrl2, ctrl3, ctrl4, ctrl5;
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u16 id1, r, ext, ctl;
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/* magic workaround patterns for Broadcom */
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static const struct {
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@ -992,6 +1071,110 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
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{ 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
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};
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pr_debug("bcom_phy_init\n");
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/* read Id from external PHY (all have the same address) */
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id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
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/* Optimize MDIO transfer by suppressing preamble. */
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r = xm_read16(hw, port, XM_MMU_CMD);
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r |= XM_MMU_NO_PRE;
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xm_write16(hw, port, XM_MMU_CMD,r);
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switch(id1) {
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case PHY_BCOM_ID1_C0:
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/*
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* Workaround BCOM Errata for the C0 type.
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* Write magic patterns to reserved registers.
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*/
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for (i = 0; i < ARRAY_SIZE(C0hack); i++)
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xm_phy_write(hw, port,
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C0hack[i].reg, C0hack[i].val);
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break;
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case PHY_BCOM_ID1_A1:
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/*
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* Workaround BCOM Errata for the A1 type.
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* Write magic patterns to reserved registers.
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*/
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for (i = 0; i < ARRAY_SIZE(A1hack); i++)
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xm_phy_write(hw, port,
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A1hack[i].reg, A1hack[i].val);
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break;
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}
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/*
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* Workaround BCOM Errata (#10523) for all BCom PHYs.
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* Disable Power Management after reset.
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*/
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r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
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r |= PHY_B_AC_DIS_PM;
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xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
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/* Dummy read */
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xm_read16(hw, port, XM_ISRC);
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ext = PHY_B_PEC_EN_LTR; /* enable tx led */
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ctl = PHY_CT_SP1000; /* always 1000mbit */
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if (skge->autoneg == AUTONEG_ENABLE) {
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/*
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* Workaround BCOM Errata #1 for the C5 type.
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* 1000Base-T Link Acquisition Failure in Slave Mode
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* Set Repeater/DTE bit 10 of the 1000Base-T Control Register
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*/
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u16 adv = PHY_B_1000C_RD;
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if (skge->advertising & ADVERTISED_1000baseT_Half)
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adv |= PHY_B_1000C_AHD;
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if (skge->advertising & ADVERTISED_1000baseT_Full)
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adv |= PHY_B_1000C_AFD;
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xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
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ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
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} else {
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if (skge->duplex == DUPLEX_FULL)
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ctl |= PHY_CT_DUP_MD;
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/* Force to slave */
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xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
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}
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/* Set autonegotiation pause parameters */
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xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
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phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
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/* Handle Jumbo frames */
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if (jumbo) {
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xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
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PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
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ext |= PHY_B_PEC_HIGH_LA;
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}
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xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
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xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
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/* Use link status change interrrupt */
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xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
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bcom_check_link(hw, port);
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}
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static void genesis_mac_init(struct skge_hw *hw, int port)
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{
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struct net_device *dev = hw->dev[port];
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struct skge_port *skge = netdev_priv(dev);
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int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
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int i;
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u32 r;
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const u8 zero[6] = { 0 };
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/* Clear MIB counters */
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xm_write16(hw, port, XM_STAT_CMD,
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XM_SC_CLR_RXC | XM_SC_CLR_TXC);
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/* Clear two times according to Errata #3 */
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xm_write16(hw, port, XM_STAT_CMD,
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XM_SC_CLR_RXC | XM_SC_CLR_TXC);
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/* initialize Rx, Tx and Link LED */
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skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
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@ -1009,9 +1192,7 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
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* GMII mode.
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*/
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spin_lock_bh(&hw->phy_lock);
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/* External Phy Handling */
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/* Take PHY out of reset. */
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/* Take external Phy out of reset */
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r = skge_read32(hw, B2_GP_IO);
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if (port == 0)
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r |= GP_DIR_0|GP_IO_0;
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@ -1020,57 +1201,47 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
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skge_write32(hw, B2_GP_IO, r);
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skge_read32(hw, B2_GP_IO);
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spin_unlock_bh(&hw->phy_lock);
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/* Enable GMII mode on the XMAC. */
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/* Enable GMII interfac */
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xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
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id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
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bcom_phy_init(skge, jumbo);
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/* Optimize MDIO transfer by suppressing preamble. */
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xm_write16(hw, port, XM_MMU_CMD,
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xm_read16(hw, port, XM_MMU_CMD)
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| XM_MMU_NO_PRE);
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/* Set Station Address */
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xm_outaddr(hw, port, XM_SA, dev->dev_addr);
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if (id1 == PHY_BCOM_ID1_C0) {
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/*
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* Workaround BCOM Errata for the C0 type.
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* Write magic patterns to reserved registers.
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*/
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for (i = 0; i < ARRAY_SIZE(C0hack); i++)
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xm_phy_write(hw, port,
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C0hack[i].reg, C0hack[i].val);
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/* We don't use match addresses so clear */
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for (i = 1; i < 16; i++)
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xm_outaddr(hw, port, XM_EXM(i), zero);
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} else if (id1 == PHY_BCOM_ID1_A1) {
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/*
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* Workaround BCOM Errata for the A1 type.
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* Write magic patterns to reserved registers.
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*/
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for (i = 0; i < ARRAY_SIZE(A1hack); i++)
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xm_phy_write(hw, port,
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A1hack[i].reg, A1hack[i].val);
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}
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/*
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* Workaround BCOM Errata (#10523) for all BCom PHYs.
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* Disable Power Management after reset.
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*/
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r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
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xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r | PHY_B_AC_DIS_PM);
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/* Dummy read */
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xm_read16(hw, port, XM_ISRC);
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r = xm_read32(hw, port, XM_MODE);
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xm_write32(hw, port, XM_MODE, r|XM_MD_CSA);
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/* configure Rx High Water Mark (XM_RX_HI_WM) */
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xm_write16(hw, port, XM_RX_HI_WM, 1450);
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/* We don't need the FCS appended to the packet. */
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r = xm_read16(hw, port, XM_RX_CMD);
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xm_write16(hw, port, XM_RX_CMD, r | XM_RX_STRIP_FCS);
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r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
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if (jumbo)
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r |= XM_RX_BIG_PK_OK;
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if (skge->duplex == DUPLEX_HALF) {
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/*
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* If in manual half duplex mode the other side might be in
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* full duplex mode, so ignore if a carrier extension is not seen
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* on frames received
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*/
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r |= XM_RX_DIS_CEXT;
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}
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xm_write16(hw, port, XM_RX_CMD, r);
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/* We want short frames padded to 60 bytes. */
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r = xm_read16(hw, port, XM_TX_CMD);
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xm_write16(hw, port, XM_TX_CMD, r | XM_TX_AUTO_PAD);
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xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
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/*
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* Bump up the transmit threshold. This helps hold off transmit
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* underruns when we're blasting traffic from both ports at once.
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*/
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xm_write16(hw, port, XM_TX_THR, 512);
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/*
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* Enable the reception of all error frames. This is is
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@ -1086,19 +1257,22 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
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* case the XMAC will start transfering frames out of the
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* RX FIFO as soon as the FIFO threshold is reached.
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*/
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r = xm_read32(hw, port, XM_MODE);
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xm_write32(hw, port, XM_MODE,
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XM_MD_RX_CRCE|XM_MD_RX_LONG|XM_MD_RX_RUNT|
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XM_MD_RX_ERR|XM_MD_RX_IRLE);
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xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
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xm_outaddr(hw, port, XM_SA, hw->dev[port]->dev_addr);
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xm_outaddr(hw, port, XM_EXM(0), hw->dev[port]->dev_addr);
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/*
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* Bump up the transmit threshold. This helps hold off transmit
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* underruns when we're blasting traffic from both ports at once.
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* Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
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* - Enable all bits excepting 'Octets Rx OK Low CntOv'
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* and 'Octets Rx OK Hi Cnt Ov'.
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*/
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xm_write16(hw, port, XM_TX_THR, 512);
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xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
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/*
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* Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
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* - Enable all bits excepting 'Octets Tx OK Low CntOv'
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* and 'Octets Tx OK Hi Cnt Ov'.
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*/
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xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
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/* Configure MAC arbiter */
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skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
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@ -1124,89 +1298,14 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
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skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
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skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
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if (hw->dev[port]->mtu > ETH_DATA_LEN) {
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if (jumbo) {
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/* Enable frame flushing if jumbo frames used */
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skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
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} else {
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/* enable timeout timers if normal frames */
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skge_write16(hw, B3_PA_CTRL,
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port == 0 ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
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(port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
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}
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r = xm_read16(hw, port, XM_RX_CMD);
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if (hw->dev[port]->mtu > ETH_DATA_LEN)
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xm_write16(hw, port, XM_RX_CMD, r | XM_RX_BIG_PK_OK);
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else
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xm_write16(hw, port, XM_RX_CMD, r & ~(XM_RX_BIG_PK_OK));
|
||||
|
||||
/* Broadcom phy initialization */
|
||||
ctrl1 = PHY_CT_SP1000;
|
||||
ctrl2 = 0;
|
||||
ctrl3 = PHY_AN_CSMA;
|
||||
ctrl4 = PHY_B_PEC_EN_LTR;
|
||||
ctrl5 = PHY_B_AC_TX_TST;
|
||||
|
||||
if (skge->autoneg == AUTONEG_ENABLE) {
|
||||
/*
|
||||
* Workaround BCOM Errata #1 for the C5 type.
|
||||
* 1000Base-T Link Acquisition Failure in Slave Mode
|
||||
* Set Repeater/DTE bit 10 of the 1000Base-T Control Register
|
||||
*/
|
||||
ctrl2 |= PHY_B_1000C_RD;
|
||||
if (skge->advertising & ADVERTISED_1000baseT_Half)
|
||||
ctrl2 |= PHY_B_1000C_AHD;
|
||||
if (skge->advertising & ADVERTISED_1000baseT_Full)
|
||||
ctrl2 |= PHY_B_1000C_AFD;
|
||||
|
||||
/* Set Flow-control capabilities */
|
||||
switch (skge->flow_control) {
|
||||
case FLOW_MODE_NONE:
|
||||
ctrl3 |= PHY_B_P_NO_PAUSE;
|
||||
break;
|
||||
case FLOW_MODE_LOC_SEND:
|
||||
ctrl3 |= PHY_B_P_ASYM_MD;
|
||||
break;
|
||||
case FLOW_MODE_SYMMETRIC:
|
||||
ctrl3 |= PHY_B_P_SYM_MD;
|
||||
break;
|
||||
case FLOW_MODE_REM_SEND:
|
||||
ctrl3 |= PHY_B_P_BOTH_MD;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Restart Auto-negotiation */
|
||||
ctrl1 |= PHY_CT_ANE | PHY_CT_RE_CFG;
|
||||
} else {
|
||||
if (skge->duplex == DUPLEX_FULL)
|
||||
ctrl1 |= PHY_CT_DUP_MD;
|
||||
|
||||
ctrl2 |= PHY_B_1000C_MSE; /* set it to Slave */
|
||||
}
|
||||
|
||||
xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, ctrl2);
|
||||
xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV, ctrl3);
|
||||
|
||||
if (skge->netdev->mtu > ETH_DATA_LEN) {
|
||||
ctrl4 |= PHY_B_PEC_HIGH_LA;
|
||||
ctrl5 |= PHY_B_AC_LONG_PACK;
|
||||
|
||||
xm_phy_write(hw, port,PHY_BCOM_AUX_CTRL, ctrl5);
|
||||
}
|
||||
|
||||
xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ctrl4);
|
||||
xm_phy_write(hw, port, PHY_BCOM_CTRL, ctrl1);
|
||||
spin_unlock_bh(&hw->phy_lock);
|
||||
|
||||
/* Clear MIB counters */
|
||||
xm_write16(hw, port, XM_STAT_CMD,
|
||||
XM_SC_CLR_RXC | XM_SC_CLR_TXC);
|
||||
/* Clear two times according to Errata #3 */
|
||||
xm_write16(hw, port, XM_STAT_CMD,
|
||||
XM_SC_CLR_RXC | XM_SC_CLR_TXC);
|
||||
|
||||
/* Start polling for link status */
|
||||
mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
|
||||
}
|
||||
|
||||
static void genesis_stop(struct skge_port *skge)
|
||||
|
|
@ -1331,23 +1430,6 @@ static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
|
|||
return gma_read16(hw, port, GM_SMI_DATA);
|
||||
}
|
||||
|
||||
static void genesis_link_down(struct skge_port *skge)
|
||||
{
|
||||
struct skge_hw *hw = skge->hw;
|
||||
int port = skge->port;
|
||||
|
||||
pr_debug("genesis_link_down\n");
|
||||
|
||||
xm_write16(hw, port, XM_MMU_CMD,
|
||||
xm_read16(hw, port, XM_MMU_CMD)
|
||||
& ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
|
||||
|
||||
/* dummy read to ensure writing */
|
||||
(void) xm_read16(hw, port, XM_MMU_CMD);
|
||||
|
||||
skge_link_down(skge);
|
||||
}
|
||||
|
||||
static void genesis_link_up(struct skge_port *skge)
|
||||
{
|
||||
struct skge_hw *hw = skge->hw;
|
||||
|
|
@ -1430,18 +1512,23 @@ static void genesis_link_up(struct skge_port *skge)
|
|||
}
|
||||
|
||||
|
||||
static void genesis_bcom_intr(struct skge_port *skge)
|
||||
static inline void bcom_phy_intr(struct skge_port *skge)
|
||||
{
|
||||
struct skge_hw *hw = skge->hw;
|
||||
int port = skge->port;
|
||||
u16 stat = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
|
||||
u16 isrc;
|
||||
|
||||
pr_debug("genesis_bcom intr stat=%x\n", stat);
|
||||
isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
|
||||
pr_debug("bcom_phy_interrupt status=0x%x\n", isrc);
|
||||
|
||||
if (isrc & PHY_B_IS_PSE)
|
||||
printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
|
||||
hw->dev[port]->name);
|
||||
|
||||
/* Workaround BCom Errata:
|
||||
* enable and disable loopback mode if "NO HCD" occurs.
|
||||
*/
|
||||
if (stat & PHY_B_IS_NO_HDCL) {
|
||||
if (isrc & PHY_B_IS_NO_HDCL) {
|
||||
u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
|
||||
xm_phy_write(hw, port, PHY_BCOM_CTRL,
|
||||
ctrl | PHY_CT_LOOP);
|
||||
|
|
@ -1449,57 +1536,9 @@ static void genesis_bcom_intr(struct skge_port *skge)
|
|||
ctrl & ~PHY_CT_LOOP);
|
||||
}
|
||||
|
||||
stat = xm_phy_read(hw, port, PHY_BCOM_STAT);
|
||||
if (stat & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) {
|
||||
u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
|
||||
if ( !(aux & PHY_B_AS_LS) && netif_carrier_ok(skge->netdev))
|
||||
genesis_link_down(skge);
|
||||
if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
|
||||
bcom_check_link(hw, port);
|
||||
|
||||
else if (stat & PHY_B_IS_LST_CHANGE) {
|
||||
if (aux & PHY_B_AS_AN_C) {
|
||||
switch (aux & PHY_B_AS_AN_RES_MSK) {
|
||||
case PHY_B_RES_1000FD:
|
||||
skge->duplex = DUPLEX_FULL;
|
||||
break;
|
||||
case PHY_B_RES_1000HD:
|
||||
skge->duplex = DUPLEX_HALF;
|
||||
break;
|
||||
}
|
||||
|
||||
switch (aux & PHY_B_AS_PAUSE_MSK) {
|
||||
case PHY_B_AS_PAUSE_MSK:
|
||||
skge->flow_control = FLOW_MODE_SYMMETRIC;
|
||||
break;
|
||||
case PHY_B_AS_PRR:
|
||||
skge->flow_control = FLOW_MODE_REM_SEND;
|
||||
break;
|
||||
case PHY_B_AS_PRT:
|
||||
skge->flow_control = FLOW_MODE_LOC_SEND;
|
||||
break;
|
||||
default:
|
||||
skge->flow_control = FLOW_MODE_NONE;
|
||||
}
|
||||
skge->speed = SPEED_1000;
|
||||
}
|
||||
genesis_link_up(skge);
|
||||
}
|
||||
else
|
||||
mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
|
||||
}
|
||||
}
|
||||
|
||||
/* Perodic poll of phy status to check for link transistion */
|
||||
static void skge_link_timer(unsigned long __arg)
|
||||
{
|
||||
struct skge_port *skge = (struct skge_port *) __arg;
|
||||
struct skge_hw *hw = skge->hw;
|
||||
|
||||
if (hw->chip_id != CHIP_ID_GENESIS || !netif_running(skge->netdev))
|
||||
return;
|
||||
|
||||
spin_lock_bh(&hw->phy_lock);
|
||||
genesis_bcom_intr(skge);
|
||||
spin_unlock_bh(&hw->phy_lock);
|
||||
}
|
||||
|
||||
/* Marvell Phy Initailization */
|
||||
|
|
@ -1547,41 +1586,12 @@ static void yukon_init(struct skge_hw *hw, int port)
|
|||
adv |= PHY_M_AN_10_FD;
|
||||
if (skge->advertising & ADVERTISED_10baseT_Half)
|
||||
adv |= PHY_M_AN_10_HD;
|
||||
|
||||
/* Set Flow-control capabilities */
|
||||
switch (skge->flow_control) {
|
||||
case FLOW_MODE_NONE:
|
||||
adv |= PHY_B_P_NO_PAUSE;
|
||||
break;
|
||||
case FLOW_MODE_LOC_SEND:
|
||||
adv |= PHY_B_P_ASYM_MD;
|
||||
break;
|
||||
case FLOW_MODE_SYMMETRIC:
|
||||
adv |= PHY_B_P_SYM_MD;
|
||||
break;
|
||||
case FLOW_MODE_REM_SEND:
|
||||
adv |= PHY_B_P_BOTH_MD;
|
||||
break;
|
||||
}
|
||||
} else { /* special defines for FIBER (88E1011S only) */
|
||||
} else /* special defines for FIBER (88E1011S only) */
|
||||
adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
|
||||
|
||||
/* Set Flow-control capabilities */
|
||||
switch (skge->flow_control) {
|
||||
case FLOW_MODE_NONE:
|
||||
adv |= PHY_M_P_NO_PAUSE_X;
|
||||
break;
|
||||
case FLOW_MODE_LOC_SEND:
|
||||
adv |= PHY_M_P_ASYM_MD_X;
|
||||
break;
|
||||
case FLOW_MODE_SYMMETRIC:
|
||||
adv |= PHY_M_P_SYM_MD_X;
|
||||
break;
|
||||
case FLOW_MODE_REM_SEND:
|
||||
adv |= PHY_M_P_BOTH_MD_X;
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* Set Flow-control capabilities */
|
||||
adv |= phy_pause_map[skge->flow_control];
|
||||
|
||||
/* Restart Auto-negotiation */
|
||||
ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
|
||||
} else {
|
||||
|
|
@ -2090,7 +2100,6 @@ static int skge_down(struct net_device *dev)
|
|||
netif_stop_queue(dev);
|
||||
|
||||
del_timer_sync(&skge->led_blink);
|
||||
del_timer_sync(&skge->link_check);
|
||||
|
||||
/* Stop transmitter */
|
||||
skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
|
||||
|
|
@ -2325,6 +2334,8 @@ static void genesis_set_multicast(struct net_device *dev)
|
|||
u32 mode;
|
||||
u8 filter[8];
|
||||
|
||||
pr_debug("genesis_set_multicast flags=%x count=%d\n", dev->flags, dev->mc_count);
|
||||
|
||||
mode = xm_read32(hw, port, XM_MODE);
|
||||
mode |= XM_MD_ENA_HASH;
|
||||
if (dev->flags & IFF_PROMISC)
|
||||
|
|
@ -2337,16 +2348,15 @@ static void genesis_set_multicast(struct net_device *dev)
|
|||
else {
|
||||
memset(filter, 0, sizeof(filter));
|
||||
for (i = 0; list && i < count; i++, list = list->next) {
|
||||
u32 crc = crc32_le(~0, list->dmi_addr, ETH_ALEN);
|
||||
u8 bit = 63 - (crc & 63);
|
||||
|
||||
u32 crc, bit;
|
||||
crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
|
||||
bit = ~crc & 0x3f;
|
||||
filter[bit/8] |= 1 << (bit%8);
|
||||
}
|
||||
}
|
||||
|
||||
xm_outhash(hw, port, XM_HSM, filter);
|
||||
|
||||
xm_write32(hw, port, XM_MODE, mode);
|
||||
xm_outhash(hw, port, XM_HSM, filter);
|
||||
}
|
||||
|
||||
static void yukon_set_multicast(struct net_device *dev)
|
||||
|
|
@ -2667,7 +2677,7 @@ static void skge_extirq(unsigned long data)
|
|||
if (hw->chip_id != CHIP_ID_GENESIS)
|
||||
yukon_phy_intr(skge);
|
||||
else
|
||||
genesis_bcom_intr(skge);
|
||||
bcom_phy_intr(skge);
|
||||
}
|
||||
}
|
||||
spin_unlock(&hw->phy_lock);
|
||||
|
|
@ -2986,10 +2996,6 @@ static struct net_device *skge_devinit(struct skge_hw *hw, int port,
|
|||
|
||||
spin_lock_init(&skge->tx_lock);
|
||||
|
||||
init_timer(&skge->link_check);
|
||||
skge->link_check.function = skge_link_timer;
|
||||
skge->link_check.data = (unsigned long) skge;
|
||||
|
||||
init_timer(&skge->led_blink);
|
||||
skge->led_blink.function = skge_blink_timer;
|
||||
skge->led_blink.data = (unsigned long) skge;
|
||||
|
|
|
|||
|
|
@ -1225,6 +1225,16 @@ enum {
|
|||
PHY_B_PES_MLT3_ER = 1<<0, /* Bit 0: MLT3 code Error */
|
||||
};
|
||||
|
||||
/* PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
|
||||
/* PHY_BCOM_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
|
||||
enum {
|
||||
PHY_B_AN_RF = 1<<13, /* Bit 13: Remote Fault */
|
||||
|
||||
PHY_B_AN_ASP = 1<<11, /* Bit 11: Asymmetric Pause */
|
||||
PHY_B_AN_PC = 1<<10, /* Bit 10: Pause Capable */
|
||||
};
|
||||
|
||||
|
||||
/***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/
|
||||
enum {
|
||||
PHY_B_FC_CTR = 0xff, /* Bit 7..0: False Carrier Counter */
|
||||
|
|
@ -1285,7 +1295,9 @@ enum {
|
|||
PHY_B_IS_LST_CHANGE = 1<<1, /* Bit 1: Link Status Changed */
|
||||
PHY_B_IS_CRC_ER = 1<<0, /* Bit 0: CRC Error */
|
||||
};
|
||||
#define PHY_B_DEF_MSK (~(PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
|
||||
#define PHY_B_DEF_MSK \
|
||||
(~(PHY_B_IS_PSE | PHY_B_IS_AN_PR | PHY_B_IS_DUP_CHANGE | \
|
||||
PHY_B_IS_LSP_CHANGE | PHY_B_IS_LST_CHANGE))
|
||||
|
||||
/* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */
|
||||
enum {
|
||||
|
|
@ -2489,7 +2501,6 @@ struct skge_port {
|
|||
dma_addr_t dma;
|
||||
unsigned long mem_size;
|
||||
|
||||
struct timer_list link_check;
|
||||
struct timer_list led_blink;
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue