usb: musb: general cleanup to musbhsdma.c
Basically getting rid of CaMeLcAsE, but also adding missing lines and spaces. Signed-off-by: Felipe Balbi <felipe.balbi@nokia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Felipe Balbi
Greg Kroah-Hartman
parent
c767c1c6f1
commit
458e6a511f
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@ -45,8 +45,8 @@
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#define MUSB_HSDMA_ADDRESS 0x8
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#define MUSB_HSDMA_COUNT 0xc
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#define MUSB_HSDMA_CHANNEL_OFFSET(_bChannel, _offset) \
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(MUSB_HSDMA_BASE + (_bChannel << 4) + _offset)
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#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
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(MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
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/* control register (16-bit): */
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#define MUSB_HSDMA_ENABLE_SHIFT 0
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@ -67,23 +67,23 @@
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struct musb_dma_controller;
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struct musb_dma_channel {
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struct dma_channel Channel;
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struct dma_channel channel;
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struct musb_dma_controller *controller;
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u32 dwStartAddress;
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u32 start_addr;
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u32 len;
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u16 wMaxPacketSize;
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u8 bIndex;
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u16 max_packet_sz;
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u8 idx;
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u8 epnum;
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u8 transmit;
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};
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struct musb_dma_controller {
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struct dma_controller Controller;
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struct musb_dma_channel aChannel[MUSB_HSDMA_CHANNELS];
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void *pDmaPrivate;
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void __iomem *pCoreBase;
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u8 bChannelCount;
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u8 bmUsedChannels;
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struct dma_controller controller;
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struct musb_dma_channel channel[MUSB_HSDMA_CHANNELS];
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void *private_data;
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void __iomem *base;
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u8 channel_count;
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u8 used_channels;
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u8 irq;
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};
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@ -93,91 +93,91 @@ static int dma_controller_start(struct dma_controller *c)
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return 0;
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}
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static void dma_channel_release(struct dma_channel *pChannel);
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static void dma_channel_release(struct dma_channel *channel);
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static int dma_controller_stop(struct dma_controller *c)
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{
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struct musb_dma_controller *controller =
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container_of(c, struct musb_dma_controller, Controller);
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struct musb *musb = (struct musb *) controller->pDmaPrivate;
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struct dma_channel *pChannel;
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u8 bBit;
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struct musb_dma_controller *controller = container_of(c,
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struct musb_dma_controller, controller);
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struct musb *musb = controller->private_data;
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struct dma_channel *channel;
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u8 bit;
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if (controller->bmUsedChannels != 0) {
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if (controller->used_channels != 0) {
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dev_err(musb->controller,
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"Stopping DMA controller while channel active\n");
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for (bBit = 0; bBit < MUSB_HSDMA_CHANNELS; bBit++) {
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if (controller->bmUsedChannels & (1 << bBit)) {
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pChannel = &controller->aChannel[bBit].Channel;
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dma_channel_release(pChannel);
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for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
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if (controller->used_channels & (1 << bit)) {
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channel = &controller->channel[bit].channel;
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dma_channel_release(channel);
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if (!controller->bmUsedChannels)
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if (!controller->used_channels)
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break;
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}
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}
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}
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return 0;
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}
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static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
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struct musb_hw_ep *hw_ep, u8 transmit)
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{
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u8 bBit;
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struct dma_channel *pChannel = NULL;
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struct musb_dma_channel *pImplChannel = NULL;
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struct musb_dma_controller *controller =
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container_of(c, struct musb_dma_controller, Controller);
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struct musb_dma_controller *controller = container_of(c,
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struct musb_dma_controller, controller);
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struct musb_dma_channel *musb_channel = NULL;
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struct dma_channel *channel = NULL;
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u8 bit;
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for (bBit = 0; bBit < MUSB_HSDMA_CHANNELS; bBit++) {
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if (!(controller->bmUsedChannels & (1 << bBit))) {
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controller->bmUsedChannels |= (1 << bBit);
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pImplChannel = &(controller->aChannel[bBit]);
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pImplChannel->controller = controller;
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pImplChannel->bIndex = bBit;
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pImplChannel->epnum = hw_ep->epnum;
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pImplChannel->transmit = transmit;
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pChannel = &(pImplChannel->Channel);
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pChannel->private_data = pImplChannel;
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pChannel->status = MUSB_DMA_STATUS_FREE;
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pChannel->max_len = 0x10000;
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for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
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if (!(controller->used_channels & (1 << bit))) {
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controller->used_channels |= (1 << bit);
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musb_channel = &(controller->channel[bit]);
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musb_channel->controller = controller;
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musb_channel->idx = bit;
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musb_channel->epnum = hw_ep->epnum;
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musb_channel->transmit = transmit;
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channel = &(musb_channel->channel);
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channel->private_data = musb_channel;
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channel->status = MUSB_DMA_STATUS_FREE;
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channel->max_len = 0x10000;
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/* Tx => mode 1; Rx => mode 0 */
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pChannel->desired_mode = transmit;
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pChannel->actual_len = 0;
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channel->desired_mode = transmit;
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channel->actual_len = 0;
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break;
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}
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}
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return pChannel;
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return channel;
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}
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static void dma_channel_release(struct dma_channel *pChannel)
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static void dma_channel_release(struct dma_channel *channel)
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{
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struct musb_dma_channel *pImplChannel =
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(struct musb_dma_channel *) pChannel->private_data;
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struct musb_dma_channel *musb_channel = channel->private_data;
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pChannel->actual_len = 0;
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pImplChannel->dwStartAddress = 0;
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pImplChannel->len = 0;
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channel->actual_len = 0;
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musb_channel->start_addr = 0;
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musb_channel->len = 0;
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pImplChannel->controller->bmUsedChannels &=
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~(1 << pImplChannel->bIndex);
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musb_channel->controller->used_channels &=
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~(1 << musb_channel->idx);
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pChannel->status = MUSB_DMA_STATUS_UNKNOWN;
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channel->status = MUSB_DMA_STATUS_UNKNOWN;
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}
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static void configure_channel(struct dma_channel *pChannel,
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static void configure_channel(struct dma_channel *channel,
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u16 packet_sz, u8 mode,
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dma_addr_t dma_addr, u32 len)
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{
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struct musb_dma_channel *pImplChannel =
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(struct musb_dma_channel *) pChannel->private_data;
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struct musb_dma_controller *controller = pImplChannel->controller;
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void __iomem *mbase = controller->pCoreBase;
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u8 bChannel = pImplChannel->bIndex;
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struct musb_dma_channel *musb_channel = channel->private_data;
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struct musb_dma_controller *controller = musb_channel->controller;
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void __iomem *mbase = controller->base;
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u8 bchannel = musb_channel->idx;
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u16 csr = 0;
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DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
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pChannel, packet_sz, dma_addr, len, mode);
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channel, packet_sz, dma_addr, len, mode);
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if (mode) {
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csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
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@ -195,180 +195,183 @@ static void configure_channel(struct dma_channel *pChannel,
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}
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}
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csr |= (pImplChannel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
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csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
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| (1 << MUSB_HSDMA_ENABLE_SHIFT)
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| (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
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| (pImplChannel->transmit
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| (musb_channel->transmit
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? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
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: 0);
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/* address/count */
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musb_writel(mbase,
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MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_ADDRESS),
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS),
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dma_addr);
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musb_writel(mbase,
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MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_COUNT),
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT),
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len);
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/* control (this should start things) */
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musb_writew(mbase,
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MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_CONTROL),
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
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csr);
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}
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static int dma_channel_program(struct dma_channel *pChannel,
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static int dma_channel_program(struct dma_channel *channel,
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u16 packet_sz, u8 mode,
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dma_addr_t dma_addr, u32 len)
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{
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struct musb_dma_channel *pImplChannel =
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(struct musb_dma_channel *) pChannel->private_data;
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struct musb_dma_channel *musb_channel = channel->private_data;
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DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
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pImplChannel->epnum,
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pImplChannel->transmit ? "Tx" : "Rx",
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musb_channel->epnum,
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musb_channel->transmit ? "Tx" : "Rx",
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packet_sz, dma_addr, len, mode);
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BUG_ON(pChannel->status == MUSB_DMA_STATUS_UNKNOWN ||
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pChannel->status == MUSB_DMA_STATUS_BUSY);
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BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
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channel->status == MUSB_DMA_STATUS_BUSY);
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pChannel->actual_len = 0;
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pImplChannel->dwStartAddress = dma_addr;
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pImplChannel->len = len;
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pImplChannel->wMaxPacketSize = packet_sz;
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pChannel->status = MUSB_DMA_STATUS_BUSY;
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channel->actual_len = 0;
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musb_channel->start_addr = dma_addr;
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musb_channel->len = len;
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musb_channel->max_packet_sz = packet_sz;
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channel->status = MUSB_DMA_STATUS_BUSY;
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if ((mode == 1) && (len >= packet_sz))
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configure_channel(pChannel, packet_sz, 1, dma_addr, len);
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configure_channel(channel, packet_sz, 1, dma_addr, len);
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else
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configure_channel(pChannel, packet_sz, 0, dma_addr, len);
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configure_channel(channel, packet_sz, 0, dma_addr, len);
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return true;
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}
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static int dma_channel_abort(struct dma_channel *pChannel)
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static int dma_channel_abort(struct dma_channel *channel)
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{
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struct musb_dma_channel *pImplChannel =
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(struct musb_dma_channel *) pChannel->private_data;
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u8 bChannel = pImplChannel->bIndex;
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void __iomem *mbase = pImplChannel->controller->pCoreBase;
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struct musb_dma_channel *musb_channel = channel->private_data;
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void __iomem *mbase = musb_channel->controller->base;
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u8 bchannel = musb_channel->idx;
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u16 csr;
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if (pChannel->status == MUSB_DMA_STATUS_BUSY) {
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if (pImplChannel->transmit) {
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if (channel->status == MUSB_DMA_STATUS_BUSY) {
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if (musb_channel->transmit) {
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csr = musb_readw(mbase,
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MUSB_EP_OFFSET(pImplChannel->epnum,
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MUSB_EP_OFFSET(musb_channel->epnum,
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MUSB_TXCSR));
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csr &= ~(MUSB_TXCSR_AUTOSET |
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MUSB_TXCSR_DMAENAB |
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MUSB_TXCSR_DMAMODE);
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musb_writew(mbase,
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MUSB_EP_OFFSET(pImplChannel->epnum,
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MUSB_TXCSR),
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MUSB_EP_OFFSET(musb_channel->epnum, MUSB_TXCSR),
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csr);
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} else {
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csr = musb_readw(mbase,
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MUSB_EP_OFFSET(pImplChannel->epnum,
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MUSB_EP_OFFSET(musb_channel->epnum,
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MUSB_RXCSR));
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csr &= ~(MUSB_RXCSR_AUTOCLEAR |
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MUSB_RXCSR_DMAENAB |
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MUSB_RXCSR_DMAMODE);
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musb_writew(mbase,
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MUSB_EP_OFFSET(pImplChannel->epnum,
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MUSB_RXCSR),
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MUSB_EP_OFFSET(musb_channel->epnum, MUSB_RXCSR),
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csr);
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}
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musb_writew(mbase,
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MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_CONTROL),
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
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0);
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musb_writel(mbase,
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MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_ADDRESS),
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS),
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0);
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musb_writel(mbase,
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MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_COUNT),
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT),
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0);
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pChannel->status = MUSB_DMA_STATUS_FREE;
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channel->status = MUSB_DMA_STATUS_FREE;
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}
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return 0;
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}
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static irqreturn_t dma_controller_irq(int irq, void *private_data)
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{
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struct musb_dma_controller *controller =
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(struct musb_dma_controller *)private_data;
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struct musb_dma_channel *pImplChannel;
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struct musb *musb = controller->pDmaPrivate;
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void __iomem *mbase = controller->pCoreBase;
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struct dma_channel *pChannel;
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u8 bChannel;
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u16 csr;
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u32 dwAddress;
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u8 int_hsdma;
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struct musb_dma_controller *controller = private_data;
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struct musb *musb = controller->private_data;
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struct musb_dma_channel *musb_channel;
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struct dma_channel *channel;
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void __iomem *mbase = controller->base;
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irqreturn_t retval = IRQ_NONE;
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unsigned long flags;
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u8 bchannel;
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u8 int_hsdma;
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u32 addr;
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u16 csr;
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spin_lock_irqsave(&musb->lock, flags);
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int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
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if (!int_hsdma)
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goto done;
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for (bChannel = 0; bChannel < MUSB_HSDMA_CHANNELS; bChannel++) {
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if (int_hsdma & (1 << bChannel)) {
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pImplChannel = (struct musb_dma_channel *)
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&(controller->aChannel[bChannel]);
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pChannel = &pImplChannel->Channel;
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for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
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if (int_hsdma & (1 << bchannel)) {
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musb_channel = (struct musb_dma_channel *)
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&(controller->channel[bchannel]);
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channel = &musb_channel->channel;
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csr = musb_readw(mbase,
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MUSB_HSDMA_CHANNEL_OFFSET(bChannel,
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
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MUSB_HSDMA_CONTROL));
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if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT))
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pImplChannel->Channel.status =
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if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
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musb_channel->channel.status =
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MUSB_DMA_STATUS_BUS_ABORT;
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else {
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} else {
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u8 devctl;
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dwAddress = musb_readl(mbase,
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addr = musb_readl(mbase,
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MUSB_HSDMA_CHANNEL_OFFSET(
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bChannel,
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bchannel,
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MUSB_HSDMA_ADDRESS));
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pChannel->actual_len = dwAddress
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- pImplChannel->dwStartAddress;
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channel->actual_len = addr
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- musb_channel->start_addr;
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DBG(2, "ch %p, 0x%x -> 0x%x (%d / %d) %s\n",
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pChannel, pImplChannel->dwStartAddress,
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dwAddress, pChannel->actual_len,
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pImplChannel->len,
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(pChannel->actual_len
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< pImplChannel->len) ?
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channel, musb_channel->start_addr,
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addr, channel->actual_len,
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musb_channel->len,
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(channel->actual_len
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< musb_channel->len) ?
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"=> reconfig 0" : "=> complete");
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devctl = musb_readb(mbase, MUSB_DEVCTL);
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pChannel->status = MUSB_DMA_STATUS_FREE;
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channel->status = MUSB_DMA_STATUS_FREE;
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/* completed */
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if ((devctl & MUSB_DEVCTL_HM)
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&& (pImplChannel->transmit)
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&& ((pChannel->desired_mode == 0)
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|| (pChannel->actual_len &
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(pImplChannel->wMaxPacketSize - 1)))
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&& (musb_channel->transmit)
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&& ((channel->desired_mode == 0)
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|| (channel->actual_len &
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(musb_channel->max_packet_sz - 1)))
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) {
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/* Send out the packet */
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musb_ep_select(mbase,
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pImplChannel->epnum);
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musb_channel->epnum);
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musb_writew(mbase, MUSB_EP_OFFSET(
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pImplChannel->epnum,
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musb_channel->epnum,
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MUSB_TXCSR),
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MUSB_TXCSR_TXPKTRDY);
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} else
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} else {
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musb_dma_completion(
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musb,
|
||||
pImplChannel->epnum,
|
||||
pImplChannel->transmit);
|
||||
musb_channel->epnum,
|
||||
musb_channel->transmit);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -380,9 +383,9 @@ done:
|
|||
|
||||
void dma_controller_destroy(struct dma_controller *c)
|
||||
{
|
||||
struct musb_dma_controller *controller;
|
||||
struct musb_dma_controller *controller = container_of(c,
|
||||
struct musb_dma_controller, controller);
|
||||
|
||||
controller = container_of(c, struct musb_dma_controller, Controller);
|
||||
if (!controller)
|
||||
return;
|
||||
|
||||
|
|
@ -393,7 +396,7 @@ void dma_controller_destroy(struct dma_controller *c)
|
|||
}
|
||||
|
||||
struct dma_controller *__init
|
||||
dma_controller_create(struct musb *musb, void __iomem *pCoreBase)
|
||||
dma_controller_create(struct musb *musb, void __iomem *base)
|
||||
{
|
||||
struct musb_dma_controller *controller;
|
||||
struct device *dev = musb->controller;
|
||||
|
|
@ -405,29 +408,30 @@ dma_controller_create(struct musb *musb, void __iomem *pCoreBase)
|
|||
return NULL;
|
||||
}
|
||||
|
||||
controller = kzalloc(sizeof(struct musb_dma_controller), GFP_KERNEL);
|
||||
controller = kzalloc(sizeof(*controller), GFP_KERNEL);
|
||||
if (!controller)
|
||||
return NULL;
|
||||
|
||||
controller->bChannelCount = MUSB_HSDMA_CHANNELS;
|
||||
controller->pDmaPrivate = musb;
|
||||
controller->pCoreBase = pCoreBase;
|
||||
controller->channel_count = MUSB_HSDMA_CHANNELS;
|
||||
controller->private_data = musb;
|
||||
controller->base = base;
|
||||
|
||||
controller->Controller.start = dma_controller_start;
|
||||
controller->Controller.stop = dma_controller_stop;
|
||||
controller->Controller.channel_alloc = dma_channel_allocate;
|
||||
controller->Controller.channel_release = dma_channel_release;
|
||||
controller->Controller.channel_program = dma_channel_program;
|
||||
controller->Controller.channel_abort = dma_channel_abort;
|
||||
controller->controller.start = dma_controller_start;
|
||||
controller->controller.stop = dma_controller_stop;
|
||||
controller->controller.channel_alloc = dma_channel_allocate;
|
||||
controller->controller.channel_release = dma_channel_release;
|
||||
controller->controller.channel_program = dma_channel_program;
|
||||
controller->controller.channel_abort = dma_channel_abort;
|
||||
|
||||
if (request_irq(irq, dma_controller_irq, IRQF_DISABLED,
|
||||
musb->controller->bus_id, &controller->Controller)) {
|
||||
musb->controller->bus_id, &controller->controller)) {
|
||||
dev_err(dev, "request_irq %d failed!\n", irq);
|
||||
dma_controller_destroy(&controller->Controller);
|
||||
dma_controller_destroy(&controller->controller);
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
controller->irq = irq;
|
||||
|
||||
return &controller->Controller;
|
||||
return &controller->controller;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue