x86/asm: Fix MWAITX C-state hint value
As per "AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions", MWAITX EAX[7:4]+1 specifies the optional hint of the optimized C-state. For C0 state, EAX[7:4] should be set to 0xf. Currently, a value of 0xf is set for EAX[3:0] instead of EAX[7:4]. Fix this by changing MWAITX_DISABLE_CSTATES from 0xf to 0xf0. This hasn't had any implications so far because setting reserved bits in EAX is simply ignored by the CPU. [ bp: Fixup comment in delay_mwaitx() and massage. ] Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Frederic Weisbecker <frederic@kernel.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: "x86@kernel.org" <x86@kernel.org> Cc: Zhenzhong Duan <zhenzhong.duan@oracle.com> Cc: <stable@vger.kernel.org> Link: https://lkml.kernel.org/r/20191007190011.4859-1-Janakarajan.Natarajan@amd.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -21,7 +21,7 @@
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#define MWAIT_ECX_INTERRUPT_BREAK 0x1
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#define MWAITX_ECX_TIMER_ENABLE BIT(1)
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#define MWAITX_MAX_LOOPS ((u32)-1)
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#define MWAITX_DISABLE_CSTATES 0xf
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#define MWAITX_DISABLE_CSTATES 0xf0
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static inline void __monitor(const void *eax, unsigned long ecx,
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unsigned long edx)
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@ -113,8 +113,8 @@ static void delay_mwaitx(unsigned long __loops)
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__monitorx(raw_cpu_ptr(&cpu_tss_rw), 0, 0);
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/*
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* AMD, like Intel, supports the EAX hint and EAX=0xf
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* means, do not enter any deep C-state and we use it
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* AMD, like Intel's MWAIT version, supports the EAX hint and
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* EAX=0xf0 means, do not enter any deep C-state and we use it
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* here in delay() to minimize wakeup latency.
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*/
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__mwaitx(MWAITX_DISABLE_CSTATES, delay, MWAITX_ECX_TIMER_ENABLE);
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