hollalinux
/
linux-sg2042
mirror of https://github.com/sophgo/linux-riscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

[PATCH] ARM: 2792/1: IXP4xx iomap API implementation 

Patch from Deepak Saxena

This patch implements the iomap API for Intel IXP4xx NPU systems.
We need to implement our own version of the API functions b/c of the
PCI hostbridge does not provide the capability to map PCI I/O space
into the CPU's physical memory space. In addition, if a system has
more than 64M of PCI memory mapped BARs, PCI memory must also be
accessed indirectly.  This patch changes the assignment of PCI I/O
resources to fall into to 0x0000:0xffff range so that we can trap
I/O areas in our ioread/iowrite macros.

Signed-off-by: Deepak Saxena
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Deepak Saxena 2005-07-06 23:06:05 +01:00 committed by Russell King
parent 7bc7fc50ce
commit 450008b5a6
2 changed files with 177 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/mach-ixp4xx/common-pci.c
View File

@ -453,8 +453,8 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys)
local_write_config(PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
res[0].name = "PCI I/O Space";
res[0].start = 0x00001000;
res[0].end = 0xffff0000;
res[0].start = 0x00000000;
res[0].end = 0x0000ffff;
res[0].flags = IORESOURCE_IO;
res[1].name = "PCI Memory Space";

176
include/asm-arm/arch-ixp4xx/io.h
View File

@ -3,7 +3,7 @@
*
* Author: Deepak Saxena <dsaxena@plexity.net>
*
* Copyright (C) 2002-2004 MontaVista Software, Inc.
* Copyright (C) 2002-2005 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -383,6 +383,180 @@ __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
*vaddr++ = inl(io_addr);
}
#define __is_io_address(p) (((unsigned long)p >= 0x0) && \
((unsigned long)p <= 0x0000ffff))
static inline unsigned int
__ixp4xx_ioread8(void __iomem *port)
{
if (__is_io_address(port))
return (unsigned int)__ixp4xx_inb((unsigned int)port);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
return (unsigned int)__raw_readb((u32)port);
#else
return (unsigned int)__ixp4xx_readb((u32)port);
#endif
}
static inline void
__ixp4xx_ioread8_rep(u32 port, u8 *vaddr, u32 count)
{
if (__is_io_address(port))
__ixp4xx_insb(port, vaddr, count);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_readsb((void __iomem *)port, vaddr, count);
#else
__ixp4xx_readsb(port, vaddr, count);
#endif
}
static inline unsigned int
__ixp4xx_ioread16(void __iomem *port)
{
if (__is_io_address(port))
return (unsigned int)__ixp4xx_inw((unsigned int)port);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
return le16_to_cpu(__raw_readw((u32)port));
#else
return (unsigned int)__ixp4xx_readw((u32)port);
#endif
}
static inline void
__ixp4xx_ioread16_rep(u32 port, u16 *vaddr, u32 count)
{
if (__is_io_address(port))
__ixp4xx_insw(port, vaddr, count);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_readsw((void __iomem *)port, vaddr, count);
#else
__ixp4xx_readsw(port, vaddr, count);
#endif
}
static inline unsigned int
__ixp4xx_ioread32(void __iomem *port)
{
if (__is_io_address(port))
return (unsigned int)__ixp4xx_inl((unsigned int)port);
else {
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
return le32_to_cpu(__raw_readl((u32)port));
#else
return (unsigned int)__ixp4xx_readl((u32)port);
#endif
}
}
static inline void
__ixp4xx_ioread32_rep(u32 port, u32 *vaddr, u32 count)
{
if (__is_io_address(port))
__ixp4xx_insl(port, vaddr, count);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_readsl((void __iomem *)port, vaddr, count);
#else
__ixp4xx_readsl(port, vaddr, count);
#endif
}
static inline void
__ixp4xx_iowrite8(u8 value, void __iomem *port)
{
if (__is_io_address(port))
__ixp4xx_outb(value, (unsigned int)port);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_writeb(value, (u32)port);
#else
__ixp4xx_writeb(value, (u32)port);
#endif
}
static inline void
__ixp4xx_iowrite8_rep(u32 port, u8 *vaddr, u32 count)
{
if (__is_io_address(port))
__ixp4xx_outsb(port, vaddr, count);
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_writesb((void __iomem *)port, vaddr, count);
#else
__ixp4xx_writesb(port, vaddr, count);
#endif
}
static inline void
__ixp4xx_iowrite16(u16 value, void __iomem *port)
{
if (__is_io_address(port))
__ixp4xx_outw(value, (unsigned int)port);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_writew(cpu_to_le16(value), (u32)port);
#else
__ixp4xx_writew(value, (u32)port);
#endif
}
static inline void
__ixp4xx_iowrite16_rep(u32 port, u16 *vaddr, u32 count)
{
if (__is_io_address(port))
__ixp4xx_outsw(port, vaddr, count);
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_readsw((void __iomem *)port, vaddr, count);
#else
__ixp4xx_writesw(port, vaddr, count);
#endif
}
static inline void
__ixp4xx_iowrite32(u32 value, void __iomem *port)
{
if (__is_io_address(port))
__ixp4xx_outl(value, (unsigned int)port);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_writel(cpu_to_le32(value), (u32)port);
#else
__ixp4xx_writel(value, (u32)port);
#endif
}
static inline void
__ixp4xx_iowrite32_rep(u32 port, u32 *vaddr, u32 count)
{
if (__is_io_address(port))
__ixp4xx_outsl(port, vaddr, count);
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_readsl((void __iomem *)port, vaddr, count);
#else
__ixp4xx_outsl(port, vaddr, count);
#endif
}
#define ioread8(p) __ixp4xx_ioread8(p)
#define ioread16(p) __ixp4xx_ioread16(p)
#define ioread32(p) __ixp4xx_ioread32(p)
#define ioread8_rep(p, v, c) __ixp4xx_ioread8_rep(p, v, c)
#define ioread16_rep(p, v, c) __ixp4xx_ioread16_rep(p, v, c)
#define ioread32_rep(p, v, c) __ixp4xx_ioread32_rep(p, v, c)
#define iowrite8(v,p) __ixp4xx_iowrite8(v,p)
#define iowrite16(v,p) __ixp4xx_iowrite16(v,p)
#define iowrite32(v,p) __ixp4xx_iowrite32(v,p)
#define iowrite8_rep(p, v, c) __ixp4xx_iowrite8_rep(p, v, c)
#define iowrite16_rep(p, v, c) __ixp4xx_iowrite16_rep(p, v, c)
#define iowrite32_rep(p, v, c) __ixp4xx_iowrite32_rep(p, v, c)
#define ioport_map(port, nr) ((void __iomem*)port)
#define ioport_unmap(addr)
#endif // __ASM_ARM_ARCH_IO_H