dt-bindings: Changes for v4.21-rc1
This contains a few cleanups of and additions to existing device tree bindings, such as XUSB, EMC, PMC and thermal. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAlwKfkQTHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoapRD/0dpJfxARsf0gH8vzO2MSQrUFaXFxPF 9C86G5RzoVGTbEXwLQoOH9k73Cup+eyjnlMcMXHHTkuINJhi5Bil+6lyztCa/P/n 4z5mZeMfv7LZaHq+/nUHSD0qjzSkz5ZaKdEXTZNijb4hjQE7x5zphOrYd4OLNrOF 1nfhHkLjmTW77cJCkG+70OQ4MP+hBQg8sHcbDrfTD5bweVb3ZcD7Bp81w4gKLrdk K4/DYxHBfzL2Y6JCgVtvHfgrWkw3cfOzznnfuHkC37OvYSVFdgkpkSNr6V+a+dQ1 AcCJ5RIyZsSSVatQT9j/QexE/eLYQUvCN/hM1VG1hZv3QFnGpTgTuF1zEw3v4rjF dN7a8OC2jkmaueQIFFHPiUgpq16FL4Tixu8DKDrU+KHmM9JJZC4PgP+5N+NdVGmq VAEjHUIgbKSToyePdic24MCuJ8TCWB75IWVw9zPLmcmQiJMTzWVwLuiEnd3/dYuW pqgrj31e30BJQ6Sgs1nKKrg6MRS0RNjaelTXhJP07P7IMgtec7xEhDlZQY6SQssV Us8M2IYSRiUocynykJCeNCkve22X2Cmtc2q68jsWhKDf/HZM8fgjbatetNDJNfFz Zr48QSyIGcp0Uba+M0LpeIHDDasgtE/YUjkNOOHc7cap2yK45L0/5E/iosXA3H1m VAI1vmcNJFTmcw== =3PUd -----END PGP SIGNATURE----- Merge tag 'tegra-for-4.21-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt dt-bindings: Changes for v4.21-rc1 This contains a few cleanups of and additions to existing device tree bindings, such as XUSB, EMC, PMC and thermal. * tag 'tegra-for-4.21-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: tegra186-pmc: Add interrupt controller properties dt-bindings: thermal: tegra-bpmp: Add Tegra194 support dt: bindings: Move tegra20-emc binding to memory-controllers directory dt: bindings: tegra20-emc: Document clock property dt: bindings: tegra20-emc: Document interrupt property dt-bindings: usb: xhci-tegra: Add power-domain details Signed-off-by: Olof Johansson <olof@lixom.net>
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@ -15,6 +15,9 @@ Required properties:
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Optional properties:
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- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal.
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- interrupt-controller: Identifies the node as an interrupt controller.
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- #interrupt-cells: Specifies the number of cells needed to encode an
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interrupt source. The value must be 2.
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Example:
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@ -10,6 +10,8 @@ Properties:
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and chosen using the ramcode board selector. If omitted, only one
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set of tables can be present and said tables will be used
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irrespective of ram-code configuration.
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- interrupts : Should contain EMC General interrupt.
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- clocks : Should contain EMC clock.
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Child device nodes describe the memory settings for different configurations and clock rates.
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@ -20,6 +22,8 @@ Example:
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#size-cells = < 0 >;
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compatible = "nvidia,tegra20-emc";
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reg = <0x7000f4000 0x200>;
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interrupts = <0 78 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_EMC>;
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}
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@ -15,7 +15,8 @@ Required properties:
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- compatible:
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Array of strings.
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One of:
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- "nvidia,tegra186-bpmp-thermal".
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- "nvidia,tegra186-bpmp-thermal"
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- "nvidia,tegra194-bpmp-thermal"
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- #thermal-sensor-cells: Cell for sensor index.
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Single-cell integer.
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Must be <1>.
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@ -59,6 +59,14 @@ For Tegra210:
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- avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
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- dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
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- hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V.
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- power-domains: A list of PM domain specifiers that reference each power-domain
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used by the xHCI controller. This list must comprise of a specifier for the
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XUSBA and XUSBC power-domains. See ../power/power_domain.txt and
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../arm/tegra/nvidia,tegra20-pmc.txt for details.
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- power-domain-names: A list of names that represent each of the specifiers in
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the 'power-domains' property. Must include 'xusb_ss' and 'xusb_host' which
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represent the power-domains XUSBA and XUSBC, respectively. See
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../power/power_domain.txt for details.
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Optional properties:
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--------------------
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@ -0,0 +1,15 @@
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/*
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* This header provides constants for binding nvidia,tegra194-bpmp-thermal.
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*/
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#ifndef _DT_BINDINGS_THERMAL_TEGRA194_BPMP_THERMAL_H
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#define _DT_BINDINGS_THERMAL_TEGRA194_BPMP_THERMAL_H
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#define TEGRA194_BPMP_THERMAL_ZONE_CPU 2
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#define TEGRA194_BPMP_THERMAL_ZONE_GPU 3
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#define TEGRA194_BPMP_THERMAL_ZONE_AUX 4
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#define TEGRA194_BPMP_THERMAL_ZONE_PLLX 5
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#define TEGRA194_BPMP_THERMAL_ZONE_AO 6
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#define TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX 7
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#endif
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