drm/radeon: split r6xx and r7xx copy_dma functions
- r6xx actually uses a slightly different packet format, although both formats seem to work ok. - r7xx doesn't have the count multiple of 2 limitation. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2646,7 +2646,7 @@ int r600_copy_blit(struct radeon_device *rdev,
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* @num_gpu_pages: number of GPU pages to xfer
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* @num_gpu_pages: number of GPU pages to xfer
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* @fence: radeon fence object
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* @fence: radeon fence object
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*
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*
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* Copy GPU paging using the DMA engine (r6xx-r7xx).
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* Copy GPU paging using the DMA engine (r6xx).
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* Used by the radeon ttm implementation to move pages if
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* Used by the radeon ttm implementation to move pages if
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* registered as the asic copy callback.
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* registered as the asic copy callback.
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*/
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*/
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@ -2669,8 +2669,8 @@ int r600_copy_dma(struct radeon_device *rdev,
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}
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}
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size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
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size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
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num_loops = DIV_ROUND_UP(size_in_dw, 0xffff);
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num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFE);
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r = radeon_ring_lock(rdev, ring, num_loops * 5 + 8);
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r = radeon_ring_lock(rdev, ring, num_loops * 4 + 8);
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if (r) {
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if (r) {
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DRM_ERROR("radeon: moving bo (%d).\n", r);
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DRM_ERROR("radeon: moving bo (%d).\n", r);
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radeon_semaphore_free(rdev, &sem, NULL);
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radeon_semaphore_free(rdev, &sem, NULL);
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@ -2693,8 +2693,8 @@ int r600_copy_dma(struct radeon_device *rdev,
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
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radeon_ring_write(ring, dst_offset & 0xfffffffc);
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radeon_ring_write(ring, dst_offset & 0xfffffffc);
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radeon_ring_write(ring, src_offset & 0xfffffffc);
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radeon_ring_write(ring, src_offset & 0xfffffffc);
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radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
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radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) |
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radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
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(upper_32_bits(src_offset) & 0xff)));
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src_offset += cur_size_in_dw * 4;
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src_offset += cur_size_in_dw * 4;
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dst_offset += cur_size_in_dw * 4;
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dst_offset += cur_size_in_dw * 4;
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}
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}
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@ -1140,9 +1140,9 @@ static struct radeon_asic rv770_asic = {
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.copy = {
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.copy = {
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.blit = &r600_copy_blit,
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.blit = &r600_copy_blit,
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.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
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.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
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.dma = &r600_copy_dma,
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.dma = &rv770_copy_dma,
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.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
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.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
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.copy = &r600_copy_dma,
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.copy = &rv770_copy_dma,
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.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
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.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
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},
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},
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.surface = {
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.surface = {
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@ -403,6 +403,10 @@ u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
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void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
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void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
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void r700_cp_stop(struct radeon_device *rdev);
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void r700_cp_stop(struct radeon_device *rdev);
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void r700_cp_fini(struct radeon_device *rdev);
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void r700_cp_fini(struct radeon_device *rdev);
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int rv770_copy_dma(struct radeon_device *rdev,
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uint64_t src_offset, uint64_t dst_offset,
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unsigned num_gpu_pages,
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struct radeon_fence **fence);
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/*
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/*
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* evergreen
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* evergreen
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@ -887,6 +887,80 @@ static int rv770_mc_init(struct radeon_device *rdev)
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return 0;
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return 0;
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}
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}
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/**
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* rv770_copy_dma - copy pages using the DMA engine
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*
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* @rdev: radeon_device pointer
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* @src_offset: src GPU address
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* @dst_offset: dst GPU address
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* @num_gpu_pages: number of GPU pages to xfer
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* @fence: radeon fence object
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*
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* Copy GPU paging using the DMA engine (r7xx).
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* Used by the radeon ttm implementation to move pages if
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* registered as the asic copy callback.
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*/
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int rv770_copy_dma(struct radeon_device *rdev,
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uint64_t src_offset, uint64_t dst_offset,
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unsigned num_gpu_pages,
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struct radeon_fence **fence)
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{
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struct radeon_semaphore *sem = NULL;
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int ring_index = rdev->asic->copy.dma_ring_index;
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struct radeon_ring *ring = &rdev->ring[ring_index];
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u32 size_in_dw, cur_size_in_dw;
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int i, num_loops;
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int r = 0;
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r = radeon_semaphore_create(rdev, &sem);
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if (r) {
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DRM_ERROR("radeon: moving bo (%d).\n", r);
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return r;
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}
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size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
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num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFF);
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r = radeon_ring_lock(rdev, ring, num_loops * 5 + 8);
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if (r) {
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DRM_ERROR("radeon: moving bo (%d).\n", r);
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radeon_semaphore_free(rdev, &sem, NULL);
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return r;
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}
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if (radeon_fence_need_sync(*fence, ring->idx)) {
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radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
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ring->idx);
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radeon_fence_note_sync(*fence, ring->idx);
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} else {
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radeon_semaphore_free(rdev, &sem, NULL);
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}
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for (i = 0; i < num_loops; i++) {
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cur_size_in_dw = size_in_dw;
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if (cur_size_in_dw > 0xFFFF)
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cur_size_in_dw = 0xFFFF;
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size_in_dw -= cur_size_in_dw;
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
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radeon_ring_write(ring, dst_offset & 0xfffffffc);
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radeon_ring_write(ring, src_offset & 0xfffffffc);
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radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
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radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
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src_offset += cur_size_in_dw * 4;
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dst_offset += cur_size_in_dw * 4;
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}
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r = radeon_fence_emit(rdev, fence, ring->idx);
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if (r) {
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radeon_ring_unlock_undo(rdev, ring);
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return r;
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}
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radeon_ring_unlock_commit(rdev, ring);
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radeon_semaphore_free(rdev, &sem, *fence);
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return r;
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}
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static int rv770_startup(struct radeon_device *rdev)
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static int rv770_startup(struct radeon_device *rdev)
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{
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{
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struct radeon_ring *ring;
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struct radeon_ring *ring;
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