CRISv32: add irq domains support
Add support for IRQ domains to the CRISv32 interrupt controller. Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
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@ -53,6 +53,7 @@ config CRIS
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select OLD_SIGSUSPEND
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select OLD_SIGSUSPEND
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select OLD_SIGACTION
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select OLD_SIGACTION
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select ARCH_REQUIRE_GPIOLIB
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select ARCH_REQUIRE_GPIOLIB
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select IRQ_DOMAIN if ETRAX_ARCH_V32
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config HZ
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config HZ
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int
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int
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@ -10,6 +10,8 @@
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#include <linux/errno.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/init.h>
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#include <linux/profile.h>
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#include <linux/profile.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/proc_fs.h>
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#include <linux/proc_fs.h>
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#include <linux/seq_file.h>
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#include <linux/seq_file.h>
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#include <linux/threads.h>
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#include <linux/threads.h>
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@ -431,6 +433,19 @@ crisv32_do_multiple(struct pt_regs* regs)
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irq_exit();
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irq_exit();
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}
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}
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static int crisv32_irq_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw_irq_num)
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{
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irq_set_chip_and_handler(virq, &crisv32_irq_type, handle_simple_irq);
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return 0;
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}
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static struct irq_domain_ops crisv32_irq_ops = {
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.map = crisv32_irq_map,
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.xlate = irq_domain_xlate_onecell,
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};
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/*
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/*
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* This is called by start_kernel. It fixes the IRQ masks and setup the
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* This is called by start_kernel. It fixes the IRQ masks and setup the
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* interrupt vector table to point to bad_interrupt pointers.
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* interrupt vector table to point to bad_interrupt pointers.
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@ -441,6 +456,8 @@ init_IRQ(void)
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int i;
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int i;
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int j;
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int j;
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reg_intr_vect_rw_mask vect_mask = {0};
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reg_intr_vect_rw_mask vect_mask = {0};
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struct device_node *np;
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struct irq_domain *domain;
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/* Clear all interrupts masks. */
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/* Clear all interrupts masks. */
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for (i = 0; i < NBR_REGS; i++)
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for (i = 0; i < NBR_REGS; i++)
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@ -449,10 +466,15 @@ init_IRQ(void)
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for (i = 0; i < 256; i++)
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for (i = 0; i < 256; i++)
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etrax_irv->v[i] = weird_irq;
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etrax_irv->v[i] = weird_irq;
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/* Point all IRQ's to bad handlers. */
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np = of_find_compatible_node(NULL, NULL, "axis,crisv32-intc");
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domain = irq_domain_add_legacy(np, NR_IRQS - FIRST_IRQ,
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FIRST_IRQ, FIRST_IRQ,
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&crisv32_irq_ops, NULL);
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BUG_ON(!domain);
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irq_set_default_host(domain);
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of_node_put(np);
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for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) {
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for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) {
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irq_set_chip_and_handler(j, &crisv32_irq_type,
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handle_simple_irq);
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set_exception_vector(i, interrupt[j]);
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set_exception_vector(i, interrupt[j]);
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}
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}
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