Merge branch 'aquantia-fixes'
Igor Russkikh says: ==================== net: aquantia: Atlantic driver 10/2017 updates This patchset fixes various issues in driver, improves parameters for better performance on 10Gbit link ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
commit
43ebf97fa4
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@ -22,8 +22,12 @@
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#define AQ_CFG_FORCE_LEGACY_INT 0U
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#define AQ_CFG_IS_INTERRUPT_MODERATION_DEF 1U
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#define AQ_CFG_INTERRUPT_MODERATION_RATE_DEF 0xFFFFU
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#define AQ_CFG_INTERRUPT_MODERATION_OFF 0
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#define AQ_CFG_INTERRUPT_MODERATION_ON 1
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#define AQ_CFG_INTERRUPT_MODERATION_AUTO 0xFFFFU
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#define AQ_CFG_INTERRUPT_MODERATION_USEC_MAX (0x1FF * 2)
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#define AQ_CFG_IRQ_MASK 0x1FFU
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#define AQ_CFG_VECS_MAX 8U
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@ -56,10 +56,6 @@ aq_ethtool_set_link_ksettings(struct net_device *ndev,
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return aq_nic_set_link_ksettings(aq_nic, cmd);
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}
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/* there "5U" is number of queue[#] stats lines (InPackets+...+InErrors) */
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static const unsigned int aq_ethtool_stat_queue_lines = 5U;
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static const unsigned int aq_ethtool_stat_queue_chars =
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5U * ETH_GSTRING_LEN;
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static const char aq_ethtool_stat_names[][ETH_GSTRING_LEN] = {
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"InPackets",
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"InUCast",
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@ -83,56 +79,26 @@ static const char aq_ethtool_stat_names[][ETH_GSTRING_LEN] = {
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"InOctetsDma",
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"OutOctetsDma",
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"InDroppedDma",
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"Queue[0] InPackets",
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"Queue[0] OutPackets",
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"Queue[0] InJumboPackets",
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"Queue[0] InLroPackets",
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"Queue[0] InErrors",
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"Queue[1] InPackets",
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"Queue[1] OutPackets",
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"Queue[1] InJumboPackets",
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"Queue[1] InLroPackets",
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"Queue[1] InErrors",
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"Queue[2] InPackets",
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"Queue[2] OutPackets",
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"Queue[2] InJumboPackets",
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"Queue[2] InLroPackets",
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"Queue[2] InErrors",
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"Queue[3] InPackets",
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"Queue[3] OutPackets",
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"Queue[3] InJumboPackets",
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"Queue[3] InLroPackets",
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"Queue[3] InErrors",
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"Queue[4] InPackets",
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"Queue[4] OutPackets",
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"Queue[4] InJumboPackets",
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"Queue[4] InLroPackets",
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"Queue[4] InErrors",
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"Queue[5] InPackets",
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"Queue[5] OutPackets",
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"Queue[5] InJumboPackets",
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"Queue[5] InLroPackets",
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"Queue[5] InErrors",
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"Queue[6] InPackets",
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"Queue[6] OutPackets",
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"Queue[6] InJumboPackets",
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"Queue[6] InLroPackets",
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"Queue[6] InErrors",
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"Queue[7] InPackets",
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"Queue[7] OutPackets",
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"Queue[7] InJumboPackets",
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"Queue[7] InLroPackets",
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"Queue[7] InErrors",
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};
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static const char aq_ethtool_queue_stat_names[][ETH_GSTRING_LEN] = {
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"Queue[%d] InPackets",
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"Queue[%d] OutPackets",
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"Queue[%d] Restarts",
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"Queue[%d] InJumboPackets",
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"Queue[%d] InLroPackets",
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"Queue[%d] InErrors",
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};
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static void aq_ethtool_stats(struct net_device *ndev,
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struct ethtool_stats *stats, u64 *data)
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{
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struct aq_nic_s *aq_nic = netdev_priv(ndev);
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struct aq_nic_cfg_s *cfg = aq_nic_get_cfg(aq_nic);
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/* ASSERT: Need add lines to aq_ethtool_stat_names if AQ_CFG_VECS_MAX > 8 */
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BUILD_BUG_ON(AQ_CFG_VECS_MAX > 8);
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memset(data, 0, ARRAY_SIZE(aq_ethtool_stat_names) * sizeof(u64));
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memset(data, 0, (ARRAY_SIZE(aq_ethtool_stat_names) +
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ARRAY_SIZE(aq_ethtool_queue_stat_names) *
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cfg->vecs) * sizeof(u64));
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aq_nic_get_stats(aq_nic, data);
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}
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@ -154,8 +120,8 @@ static void aq_ethtool_get_drvinfo(struct net_device *ndev,
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strlcpy(drvinfo->bus_info, pdev ? pci_name(pdev) : "",
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sizeof(drvinfo->bus_info));
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drvinfo->n_stats = ARRAY_SIZE(aq_ethtool_stat_names) -
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(AQ_CFG_VECS_MAX - cfg->vecs) * aq_ethtool_stat_queue_lines;
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drvinfo->n_stats = ARRAY_SIZE(aq_ethtool_stat_names) +
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cfg->vecs * ARRAY_SIZE(aq_ethtool_queue_stat_names);
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drvinfo->testinfo_len = 0;
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drvinfo->regdump_len = regs_count;
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drvinfo->eedump_len = 0;
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@ -164,14 +130,25 @@ static void aq_ethtool_get_drvinfo(struct net_device *ndev,
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static void aq_ethtool_get_strings(struct net_device *ndev,
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u32 stringset, u8 *data)
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{
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int i, si;
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struct aq_nic_s *aq_nic = netdev_priv(ndev);
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struct aq_nic_cfg_s *cfg = aq_nic_get_cfg(aq_nic);
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u8 *p = data;
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if (stringset == ETH_SS_STATS)
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memcpy(data, *aq_ethtool_stat_names,
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sizeof(aq_ethtool_stat_names) -
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(AQ_CFG_VECS_MAX - cfg->vecs) *
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aq_ethtool_stat_queue_chars);
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if (stringset == ETH_SS_STATS) {
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memcpy(p, *aq_ethtool_stat_names,
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sizeof(aq_ethtool_stat_names));
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p = p + sizeof(aq_ethtool_stat_names);
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for (i = 0; i < cfg->vecs; i++) {
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for (si = 0;
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si < ARRAY_SIZE(aq_ethtool_queue_stat_names);
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si++) {
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snprintf(p, ETH_GSTRING_LEN,
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aq_ethtool_queue_stat_names[si], i);
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p += ETH_GSTRING_LEN;
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}
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}
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}
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}
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static int aq_ethtool_get_sset_count(struct net_device *ndev, int stringset)
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@ -182,9 +159,8 @@ static int aq_ethtool_get_sset_count(struct net_device *ndev, int stringset)
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switch (stringset) {
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case ETH_SS_STATS:
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ret = ARRAY_SIZE(aq_ethtool_stat_names) -
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(AQ_CFG_VECS_MAX - cfg->vecs) *
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aq_ethtool_stat_queue_lines;
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ret = ARRAY_SIZE(aq_ethtool_stat_names) +
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cfg->vecs * ARRAY_SIZE(aq_ethtool_queue_stat_names);
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break;
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default:
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ret = -EOPNOTSUPP;
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@ -245,6 +221,69 @@ static int aq_ethtool_get_rxnfc(struct net_device *ndev,
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return err;
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}
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int aq_ethtool_get_coalesce(struct net_device *ndev,
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struct ethtool_coalesce *coal)
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{
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struct aq_nic_s *aq_nic = netdev_priv(ndev);
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struct aq_nic_cfg_s *cfg = aq_nic_get_cfg(aq_nic);
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if (cfg->itr == AQ_CFG_INTERRUPT_MODERATION_ON ||
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cfg->itr == AQ_CFG_INTERRUPT_MODERATION_AUTO) {
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coal->rx_coalesce_usecs = cfg->rx_itr;
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coal->tx_coalesce_usecs = cfg->tx_itr;
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coal->rx_max_coalesced_frames = 0;
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coal->tx_max_coalesced_frames = 0;
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} else {
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coal->rx_coalesce_usecs = 0;
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coal->tx_coalesce_usecs = 0;
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coal->rx_max_coalesced_frames = 1;
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coal->tx_max_coalesced_frames = 1;
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}
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return 0;
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}
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int aq_ethtool_set_coalesce(struct net_device *ndev,
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struct ethtool_coalesce *coal)
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{
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struct aq_nic_s *aq_nic = netdev_priv(ndev);
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struct aq_nic_cfg_s *cfg = aq_nic_get_cfg(aq_nic);
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/* This is not yet supported
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*/
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if (coal->use_adaptive_rx_coalesce || coal->use_adaptive_tx_coalesce)
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return -EOPNOTSUPP;
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/* Atlantic only supports timing based coalescing
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*/
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if (coal->rx_max_coalesced_frames > 1 ||
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coal->rx_coalesce_usecs_irq ||
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coal->rx_max_coalesced_frames_irq)
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return -EOPNOTSUPP;
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if (coal->tx_max_coalesced_frames > 1 ||
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coal->tx_coalesce_usecs_irq ||
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coal->tx_max_coalesced_frames_irq)
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return -EOPNOTSUPP;
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/* We do not support frame counting. Check this
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*/
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if (!(coal->rx_max_coalesced_frames == !coal->rx_coalesce_usecs))
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return -EOPNOTSUPP;
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if (!(coal->tx_max_coalesced_frames == !coal->tx_coalesce_usecs))
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return -EOPNOTSUPP;
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if (coal->rx_coalesce_usecs > AQ_CFG_INTERRUPT_MODERATION_USEC_MAX ||
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coal->tx_coalesce_usecs > AQ_CFG_INTERRUPT_MODERATION_USEC_MAX)
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return -EINVAL;
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cfg->itr = AQ_CFG_INTERRUPT_MODERATION_ON;
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cfg->rx_itr = coal->rx_coalesce_usecs;
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cfg->tx_itr = coal->tx_coalesce_usecs;
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return aq_nic_update_interrupt_moderation_settings(aq_nic);
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}
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const struct ethtool_ops aq_ethtool_ops = {
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.get_link = aq_ethtool_get_link,
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.get_regs_len = aq_ethtool_get_regs_len,
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@ -259,4 +298,6 @@ const struct ethtool_ops aq_ethtool_ops = {
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.get_ethtool_stats = aq_ethtool_stats,
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.get_link_ksettings = aq_ethtool_get_link_ksettings,
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.set_link_ksettings = aq_ethtool_set_link_ksettings,
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.get_coalesce = aq_ethtool_get_coalesce,
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.set_coalesce = aq_ethtool_set_coalesce,
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};
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@ -151,8 +151,7 @@ struct aq_hw_ops {
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[ETH_ALEN],
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u32 count);
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int (*hw_interrupt_moderation_set)(struct aq_hw_s *self,
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bool itr_enabled);
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int (*hw_interrupt_moderation_set)(struct aq_hw_s *self);
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int (*hw_rss_set)(struct aq_hw_s *self,
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struct aq_rss_parameters *rss_params);
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@ -163,6 +162,8 @@ struct aq_hw_ops {
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int (*hw_get_regs)(struct aq_hw_s *self,
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struct aq_hw_caps_s *aq_hw_caps, u32 *regs_buff);
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int (*hw_update_stats)(struct aq_hw_s *self);
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int (*hw_get_hw_stats)(struct aq_hw_s *self, u64 *data,
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unsigned int *p_count);
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@ -16,6 +16,7 @@
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#include "aq_pci_func.h"
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#include "aq_nic_internal.h"
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#include <linux/moduleparam.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/timer.h>
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@ -24,6 +25,18 @@
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#include <linux/tcp.h>
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#include <net/ip.h>
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static unsigned int aq_itr = AQ_CFG_INTERRUPT_MODERATION_AUTO;
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module_param_named(aq_itr, aq_itr, uint, 0644);
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MODULE_PARM_DESC(aq_itr, "Interrupt throttling mode");
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static unsigned int aq_itr_tx;
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module_param_named(aq_itr_tx, aq_itr_tx, uint, 0644);
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MODULE_PARM_DESC(aq_itr_tx, "TX interrupt throttle rate");
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static unsigned int aq_itr_rx;
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module_param_named(aq_itr_rx, aq_itr_rx, uint, 0644);
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MODULE_PARM_DESC(aq_itr_rx, "RX interrupt throttle rate");
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static void aq_nic_rss_init(struct aq_nic_s *self, unsigned int num_rss_queues)
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{
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struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg;
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@ -61,9 +74,9 @@ static void aq_nic_cfg_init_defaults(struct aq_nic_s *self)
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cfg->is_polling = AQ_CFG_IS_POLLING_DEF;
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cfg->is_interrupt_moderation = AQ_CFG_IS_INTERRUPT_MODERATION_DEF;
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cfg->itr = cfg->is_interrupt_moderation ?
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AQ_CFG_INTERRUPT_MODERATION_RATE_DEF : 0U;
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cfg->itr = aq_itr;
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cfg->tx_itr = aq_itr_tx;
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cfg->rx_itr = aq_itr_rx;
|
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|
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cfg->is_rss = AQ_CFG_IS_RSS_DEF;
|
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cfg->num_rss_queues = AQ_CFG_NUM_RSS_QUEUES_DEF;
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|
@ -126,10 +139,12 @@ static int aq_nic_update_link_status(struct aq_nic_s *self)
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if (err)
|
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return err;
|
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|
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if (self->link_status.mbps != self->aq_hw->aq_link_status.mbps)
|
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if (self->link_status.mbps != self->aq_hw->aq_link_status.mbps) {
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pr_info("%s: link change old %d new %d\n",
|
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AQ_CFG_DRV_NAME, self->link_status.mbps,
|
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self->aq_hw->aq_link_status.mbps);
|
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aq_nic_update_interrupt_moderation_settings(self);
|
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}
|
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|
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self->link_status = self->aq_hw->aq_link_status;
|
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if (!netif_carrier_ok(self->ndev) && self->link_status.mbps) {
|
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|
@ -164,8 +179,8 @@ static void aq_nic_service_timer_cb(unsigned long param)
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if (err)
|
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goto err_exit;
|
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|
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self->aq_hw_ops.hw_interrupt_moderation_set(self->aq_hw,
|
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self->aq_nic_cfg.is_interrupt_moderation);
|
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if (self->aq_hw_ops.hw_update_stats)
|
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self->aq_hw_ops.hw_update_stats(self->aq_hw);
|
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|
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memset(&stats_rx, 0U, sizeof(struct aq_ring_stats_rx_s));
|
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memset(&stats_tx, 0U, sizeof(struct aq_ring_stats_tx_s));
|
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|
@ -334,6 +349,7 @@ struct aq_nic_s *aq_nic_alloc_hot(struct net_device *ndev)
|
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}
|
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if (netif_running(ndev))
|
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netif_tx_disable(ndev);
|
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netif_carrier_off(self->ndev);
|
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|
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for (self->aq_vecs = 0; self->aq_vecs < self->aq_nic_cfg.vecs;
|
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self->aq_vecs++) {
|
||||
|
@ -421,9 +437,8 @@ int aq_nic_start(struct aq_nic_s *self)
|
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if (err < 0)
|
||||
goto err_exit;
|
||||
|
||||
err = self->aq_hw_ops.hw_interrupt_moderation_set(self->aq_hw,
|
||||
self->aq_nic_cfg.is_interrupt_moderation);
|
||||
if (err < 0)
|
||||
err = aq_nic_update_interrupt_moderation_settings(self);
|
||||
if (err)
|
||||
goto err_exit;
|
||||
setup_timer(&self->service_timer, &aq_nic_service_timer_cb,
|
||||
(unsigned long)self);
|
||||
|
@ -645,6 +660,11 @@ err_exit:
|
|||
return err;
|
||||
}
|
||||
|
||||
int aq_nic_update_interrupt_moderation_settings(struct aq_nic_s *self)
|
||||
{
|
||||
return self->aq_hw_ops.hw_interrupt_moderation_set(self->aq_hw);
|
||||
}
|
||||
|
||||
int aq_nic_set_packet_filter(struct aq_nic_s *self, unsigned int flags)
|
||||
{
|
||||
int err = 0;
|
||||
|
@ -899,6 +919,7 @@ int aq_nic_stop(struct aq_nic_s *self)
|
|||
unsigned int i = 0U;
|
||||
|
||||
netif_tx_disable(self->ndev);
|
||||
netif_carrier_off(self->ndev);
|
||||
|
||||
del_timer_sync(&self->service_timer);
|
||||
|
||||
|
|
|
@ -40,6 +40,8 @@ struct aq_nic_cfg_s {
|
|||
u32 vecs; /* vecs==allocated irqs */
|
||||
u32 irq_type;
|
||||
u32 itr;
|
||||
u16 rx_itr;
|
||||
u16 tx_itr;
|
||||
u32 num_rss_queues;
|
||||
u32 mtu;
|
||||
u32 ucp_0x364;
|
||||
|
@ -49,7 +51,6 @@ struct aq_nic_cfg_s {
|
|||
u16 is_mc_list_enabled;
|
||||
u16 mc_list_count;
|
||||
bool is_autoneg;
|
||||
bool is_interrupt_moderation;
|
||||
bool is_polling;
|
||||
bool is_rss;
|
||||
bool is_lro;
|
||||
|
@ -104,5 +105,6 @@ int aq_nic_set_link_ksettings(struct aq_nic_s *self,
|
|||
struct aq_nic_cfg_s *aq_nic_get_cfg(struct aq_nic_s *self);
|
||||
u32 aq_nic_get_fw_version(struct aq_nic_s *self);
|
||||
int aq_nic_change_pm_state(struct aq_nic_s *self, pm_message_t *pm_msg);
|
||||
int aq_nic_update_interrupt_moderation_settings(struct aq_nic_s *self);
|
||||
|
||||
#endif /* AQ_NIC_H */
|
||||
|
|
|
@ -85,6 +85,7 @@ int aq_pci_func_init(struct aq_pci_func_s *self)
|
|||
int err = 0;
|
||||
unsigned int bar = 0U;
|
||||
unsigned int port = 0U;
|
||||
unsigned int numvecs = 0U;
|
||||
|
||||
err = pci_enable_device(self->pdev);
|
||||
if (err < 0)
|
||||
|
@ -142,10 +143,12 @@ int aq_pci_func_init(struct aq_pci_func_s *self)
|
|||
}
|
||||
}
|
||||
|
||||
/*enable interrupts */
|
||||
numvecs = min((u8)AQ_CFG_VECS_DEF, self->aq_hw_caps.msix_irqs);
|
||||
numvecs = min(numvecs, num_online_cpus());
|
||||
|
||||
/* enable interrupts */
|
||||
#if !AQ_CFG_FORCE_LEGACY_INT
|
||||
err = pci_alloc_irq_vectors(self->pdev, self->aq_hw_caps.msix_irqs,
|
||||
self->aq_hw_caps.msix_irqs, PCI_IRQ_MSIX);
|
||||
err = pci_alloc_irq_vectors(self->pdev, numvecs, numvecs, PCI_IRQ_MSIX);
|
||||
|
||||
if (err < 0) {
|
||||
err = pci_alloc_irq_vectors(self->pdev, 1, 1,
|
||||
|
@ -153,7 +156,7 @@ int aq_pci_func_init(struct aq_pci_func_s *self)
|
|||
if (err < 0)
|
||||
goto err_exit;
|
||||
}
|
||||
#endif
|
||||
#endif /* AQ_CFG_FORCE_LEGACY_INT */
|
||||
|
||||
/* net device init */
|
||||
for (port = 0; port < self->ports; ++port) {
|
||||
|
@ -265,6 +268,9 @@ void aq_pci_func_free(struct aq_pci_func_s *self)
|
|||
aq_nic_ndev_free(self->port[port]);
|
||||
}
|
||||
|
||||
if (self->mmio)
|
||||
iounmap(self->mmio);
|
||||
|
||||
kfree(self);
|
||||
|
||||
err_exit:;
|
||||
|
|
|
@ -373,8 +373,11 @@ int aq_vec_get_sw_stats(struct aq_vec_s *self, u64 *data, unsigned int *p_count)
|
|||
memset(&stats_tx, 0U, sizeof(struct aq_ring_stats_tx_s));
|
||||
aq_vec_add_stats(self, &stats_rx, &stats_tx);
|
||||
|
||||
/* This data should mimic aq_ethtool_queue_stat_names structure
|
||||
*/
|
||||
data[count] += stats_rx.packets;
|
||||
data[++count] += stats_tx.packets;
|
||||
data[++count] += stats_tx.queue_restarts;
|
||||
data[++count] += stats_rx.jumbo_packets;
|
||||
data[++count] += stats_rx.lro_packets;
|
||||
data[++count] += stats_rx.errors;
|
||||
|
|
|
@ -765,24 +765,23 @@ err_exit:
|
|||
return err;
|
||||
}
|
||||
|
||||
static int hw_atl_a0_hw_interrupt_moderation_set(struct aq_hw_s *self,
|
||||
bool itr_enabled)
|
||||
static int hw_atl_a0_hw_interrupt_moderation_set(struct aq_hw_s *self)
|
||||
{
|
||||
unsigned int i = 0U;
|
||||
u32 itr_rx;
|
||||
|
||||
if (itr_enabled && self->aq_nic_cfg->itr) {
|
||||
if (self->aq_nic_cfg->itr != 0xFFFFU) {
|
||||
if (self->aq_nic_cfg->itr) {
|
||||
if (self->aq_nic_cfg->itr != AQ_CFG_INTERRUPT_MODERATION_AUTO) {
|
||||
u32 itr_ = (self->aq_nic_cfg->itr >> 1);
|
||||
|
||||
itr_ = min(AQ_CFG_IRQ_MASK, itr_);
|
||||
|
||||
PHAL_ATLANTIC_A0->itr_rx = 0x80000000U |
|
||||
(itr_ << 0x10);
|
||||
itr_rx = 0x80000000U | (itr_ << 0x10);
|
||||
} else {
|
||||
u32 n = 0xFFFFU & aq_hw_read_reg(self, 0x00002A00U);
|
||||
|
||||
if (n < self->aq_link_status.mbps) {
|
||||
PHAL_ATLANTIC_A0->itr_rx = 0U;
|
||||
itr_rx = 0U;
|
||||
} else {
|
||||
static unsigned int hw_timers_tbl_[] = {
|
||||
0x01CU, /* 10Gbit */
|
||||
|
@ -797,8 +796,7 @@ static int hw_atl_a0_hw_interrupt_moderation_set(struct aq_hw_s *self,
|
|||
hw_atl_utils_mbps_2_speed_index(
|
||||
self->aq_link_status.mbps);
|
||||
|
||||
PHAL_ATLANTIC_A0->itr_rx =
|
||||
0x80000000U |
|
||||
itr_rx = 0x80000000U |
|
||||
(hw_timers_tbl_[speed_index] << 0x10U);
|
||||
}
|
||||
|
||||
|
@ -806,11 +804,11 @@ static int hw_atl_a0_hw_interrupt_moderation_set(struct aq_hw_s *self,
|
|||
aq_hw_write_reg(self, 0x00002A00U, 0x8D000000U);
|
||||
}
|
||||
} else {
|
||||
PHAL_ATLANTIC_A0->itr_rx = 0U;
|
||||
itr_rx = 0U;
|
||||
}
|
||||
|
||||
for (i = HW_ATL_A0_RINGS_MAX; i--;)
|
||||
reg_irq_thr_set(self, PHAL_ATLANTIC_A0->itr_rx, i);
|
||||
reg_irq_thr_set(self, itr_rx, i);
|
||||
|
||||
return aq_hw_err_from_flags(self);
|
||||
}
|
||||
|
@ -885,6 +883,7 @@ static struct aq_hw_ops hw_atl_ops_ = {
|
|||
.hw_rss_set = hw_atl_a0_hw_rss_set,
|
||||
.hw_rss_hash_set = hw_atl_a0_hw_rss_hash_set,
|
||||
.hw_get_regs = hw_atl_utils_hw_get_regs,
|
||||
.hw_update_stats = hw_atl_utils_update_stats,
|
||||
.hw_get_hw_stats = hw_atl_utils_get_hw_stats,
|
||||
.hw_get_fw_version = hw_atl_utils_get_fw_version,
|
||||
};
|
||||
|
|
|
@ -788,39 +788,45 @@ err_exit:
|
|||
return err;
|
||||
}
|
||||
|
||||
static int hw_atl_b0_hw_interrupt_moderation_set(struct aq_hw_s *self,
|
||||
bool itr_enabled)
|
||||
static int hw_atl_b0_hw_interrupt_moderation_set(struct aq_hw_s *self)
|
||||
{
|
||||
unsigned int i = 0U;
|
||||
u32 itr_tx = 2U;
|
||||
u32 itr_rx = 2U;
|
||||
|
||||
if (itr_enabled && self->aq_nic_cfg->itr) {
|
||||
switch (self->aq_nic_cfg->itr) {
|
||||
case AQ_CFG_INTERRUPT_MODERATION_ON:
|
||||
case AQ_CFG_INTERRUPT_MODERATION_AUTO:
|
||||
tdm_tx_desc_wr_wb_irq_en_set(self, 0U);
|
||||
tdm_tdm_intr_moder_en_set(self, 1U);
|
||||
rdm_rx_desc_wr_wb_irq_en_set(self, 0U);
|
||||
rdm_rdm_intr_moder_en_set(self, 1U);
|
||||
|
||||
PHAL_ATLANTIC_B0->itr_tx = 2U;
|
||||
PHAL_ATLANTIC_B0->itr_rx = 2U;
|
||||
if (self->aq_nic_cfg->itr == AQ_CFG_INTERRUPT_MODERATION_ON) {
|
||||
/* HW timers are in 2us units */
|
||||
int tx_max_timer = self->aq_nic_cfg->tx_itr / 2;
|
||||
int tx_min_timer = tx_max_timer / 2;
|
||||
|
||||
if (self->aq_nic_cfg->itr != 0xFFFFU) {
|
||||
unsigned int max_timer = self->aq_nic_cfg->itr / 2U;
|
||||
unsigned int min_timer = self->aq_nic_cfg->itr / 32U;
|
||||
int rx_max_timer = self->aq_nic_cfg->rx_itr / 2;
|
||||
int rx_min_timer = rx_max_timer / 2;
|
||||
|
||||
max_timer = min(0x1FFU, max_timer);
|
||||
min_timer = min(0xFFU, min_timer);
|
||||
tx_max_timer = min(HW_ATL_INTR_MODER_MAX, tx_max_timer);
|
||||
tx_min_timer = min(HW_ATL_INTR_MODER_MIN, tx_min_timer);
|
||||
rx_max_timer = min(HW_ATL_INTR_MODER_MAX, rx_max_timer);
|
||||
rx_min_timer = min(HW_ATL_INTR_MODER_MIN, rx_min_timer);
|
||||
|
||||
PHAL_ATLANTIC_B0->itr_tx |= min_timer << 0x8U;
|
||||
PHAL_ATLANTIC_B0->itr_tx |= max_timer << 0x10U;
|
||||
PHAL_ATLANTIC_B0->itr_rx |= min_timer << 0x8U;
|
||||
PHAL_ATLANTIC_B0->itr_rx |= max_timer << 0x10U;
|
||||
itr_tx |= tx_min_timer << 0x8U;
|
||||
itr_tx |= tx_max_timer << 0x10U;
|
||||
itr_rx |= rx_min_timer << 0x8U;
|
||||
itr_rx |= rx_max_timer << 0x10U;
|
||||
} else {
|
||||
static unsigned int hw_atl_b0_timers_table_tx_[][2] = {
|
||||
{0xffU, 0xffU}, /* 10Gbit */
|
||||
{0xffU, 0x1ffU}, /* 5Gbit */
|
||||
{0xffU, 0x1ffU}, /* 5Gbit 5GS */
|
||||
{0xffU, 0x1ffU}, /* 2.5Gbit */
|
||||
{0xffU, 0x1ffU}, /* 1Gbit */
|
||||
{0xffU, 0x1ffU}, /* 100Mbit */
|
||||
{0xfU, 0xffU}, /* 10Gbit */
|
||||
{0xfU, 0x1ffU}, /* 5Gbit */
|
||||
{0xfU, 0x1ffU}, /* 5Gbit 5GS */
|
||||
{0xfU, 0x1ffU}, /* 2.5Gbit */
|
||||
{0xfU, 0x1ffU}, /* 1Gbit */
|
||||
{0xfU, 0x1ffU}, /* 100Mbit */
|
||||
};
|
||||
|
||||
static unsigned int hw_atl_b0_timers_table_rx_[][2] = {
|
||||
|
@ -836,34 +842,36 @@ static int hw_atl_b0_hw_interrupt_moderation_set(struct aq_hw_s *self,
|
|||
hw_atl_utils_mbps_2_speed_index(
|
||||
self->aq_link_status.mbps);
|
||||
|
||||
PHAL_ATLANTIC_B0->itr_tx |=
|
||||
hw_atl_b0_timers_table_tx_[speed_index]
|
||||
[0] << 0x8U; /* set min timer value */
|
||||
PHAL_ATLANTIC_B0->itr_tx |=
|
||||
hw_atl_b0_timers_table_tx_[speed_index]
|
||||
[1] << 0x10U; /* set max timer value */
|
||||
/* Update user visible ITR settings */
|
||||
self->aq_nic_cfg->tx_itr = hw_atl_b0_timers_table_tx_
|
||||
[speed_index][1] * 2;
|
||||
self->aq_nic_cfg->rx_itr = hw_atl_b0_timers_table_rx_
|
||||
[speed_index][1] * 2;
|
||||
|
||||
PHAL_ATLANTIC_B0->itr_rx |=
|
||||
hw_atl_b0_timers_table_rx_[speed_index]
|
||||
[0] << 0x8U; /* set min timer value */
|
||||
PHAL_ATLANTIC_B0->itr_rx |=
|
||||
hw_atl_b0_timers_table_rx_[speed_index]
|
||||
[1] << 0x10U; /* set max timer value */
|
||||
itr_tx |= hw_atl_b0_timers_table_tx_
|
||||
[speed_index][0] << 0x8U;
|
||||
itr_tx |= hw_atl_b0_timers_table_tx_
|
||||
[speed_index][1] << 0x10U;
|
||||
|
||||
itr_rx |= hw_atl_b0_timers_table_rx_
|
||||
[speed_index][0] << 0x8U;
|
||||
itr_rx |= hw_atl_b0_timers_table_rx_
|
||||
[speed_index][1] << 0x10U;
|
||||
}
|
||||
} else {
|
||||
break;
|
||||
case AQ_CFG_INTERRUPT_MODERATION_OFF:
|
||||
tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
|
||||
tdm_tdm_intr_moder_en_set(self, 0U);
|
||||
rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
|
||||
rdm_rdm_intr_moder_en_set(self, 0U);
|
||||
PHAL_ATLANTIC_B0->itr_tx = 0U;
|
||||
PHAL_ATLANTIC_B0->itr_rx = 0U;
|
||||
itr_tx = 0U;
|
||||
itr_rx = 0U;
|
||||
break;
|
||||
}
|
||||
|
||||
for (i = HW_ATL_B0_RINGS_MAX; i--;) {
|
||||
reg_tx_intr_moder_ctrl_set(self,
|
||||
PHAL_ATLANTIC_B0->itr_tx, i);
|
||||
reg_rx_intr_moder_ctrl_set(self,
|
||||
PHAL_ATLANTIC_B0->itr_rx, i);
|
||||
reg_tx_intr_moder_ctrl_set(self, itr_tx, i);
|
||||
reg_rx_intr_moder_ctrl_set(self, itr_rx, i);
|
||||
}
|
||||
|
||||
return aq_hw_err_from_flags(self);
|
||||
|
@ -939,6 +947,7 @@ static struct aq_hw_ops hw_atl_ops_ = {
|
|||
.hw_rss_set = hw_atl_b0_hw_rss_set,
|
||||
.hw_rss_hash_set = hw_atl_b0_hw_rss_hash_set,
|
||||
.hw_get_regs = hw_atl_utils_hw_get_regs,
|
||||
.hw_update_stats = hw_atl_utils_update_stats,
|
||||
.hw_get_hw_stats = hw_atl_utils_get_hw_stats,
|
||||
.hw_get_fw_version = hw_atl_utils_get_fw_version,
|
||||
};
|
||||
|
|
|
@ -139,6 +139,9 @@
|
|||
|
||||
#define HW_ATL_B0_FW_VER_EXPECTED 0x01050006U
|
||||
|
||||
#define HW_ATL_INTR_MODER_MAX 0x1FF
|
||||
#define HW_ATL_INTR_MODER_MIN 0xFF
|
||||
|
||||
/* Hardware tx descriptor */
|
||||
struct __packed hw_atl_txd_s {
|
||||
u64 buf_addr;
|
||||
|
|
|
@ -255,6 +255,15 @@ err_exit:
|
|||
return err;
|
||||
}
|
||||
|
||||
int hw_atl_utils_mpi_read_mbox(struct aq_hw_s *self,
|
||||
struct hw_aq_atl_utils_mbox_header *pmbox)
|
||||
{
|
||||
return hw_atl_utils_fw_downld_dwords(self,
|
||||
PHAL_ATLANTIC->mbox_addr,
|
||||
(u32 *)(void *)pmbox,
|
||||
sizeof(*pmbox) / sizeof(u32));
|
||||
}
|
||||
|
||||
void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self,
|
||||
struct hw_aq_atl_utils_mbox *pmbox)
|
||||
{
|
||||
|
@ -267,9 +276,6 @@ void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self,
|
|||
if (err < 0)
|
||||
goto err_exit;
|
||||
|
||||
if (pmbox != &PHAL_ATLANTIC->mbox)
|
||||
memcpy(pmbox, &PHAL_ATLANTIC->mbox, sizeof(*pmbox));
|
||||
|
||||
if (IS_CHIP_FEATURE(REVISION_A0)) {
|
||||
unsigned int mtu = self->aq_nic_cfg ?
|
||||
self->aq_nic_cfg->mtu : 1514U;
|
||||
|
@ -299,17 +305,17 @@ void hw_atl_utils_mpi_set(struct aq_hw_s *self,
|
|||
{
|
||||
int err = 0;
|
||||
u32 transaction_id = 0;
|
||||
struct hw_aq_atl_utils_mbox_header mbox;
|
||||
|
||||
if (state == MPI_RESET) {
|
||||
hw_atl_utils_mpi_read_stats(self, &PHAL_ATLANTIC->mbox);
|
||||
hw_atl_utils_mpi_read_mbox(self, &mbox);
|
||||
|
||||
transaction_id = PHAL_ATLANTIC->mbox.transaction_id;
|
||||
transaction_id = mbox.transaction_id;
|
||||
|
||||
AQ_HW_WAIT_FOR(transaction_id !=
|
||||
(hw_atl_utils_mpi_read_stats
|
||||
(self, &PHAL_ATLANTIC->mbox),
|
||||
PHAL_ATLANTIC->mbox.transaction_id),
|
||||
1000U, 100U);
|
||||
(hw_atl_utils_mpi_read_mbox(self, &mbox),
|
||||
mbox.transaction_id),
|
||||
1000U, 100U);
|
||||
if (err < 0)
|
||||
goto err_exit;
|
||||
}
|
||||
|
@ -492,16 +498,51 @@ int hw_atl_utils_hw_set_power(struct aq_hw_s *self,
|
|||
return 0;
|
||||
}
|
||||
|
||||
int hw_atl_utils_update_stats(struct aq_hw_s *self)
|
||||
{
|
||||
struct hw_atl_s *hw_self = PHAL_ATLANTIC;
|
||||
struct hw_aq_atl_utils_mbox mbox;
|
||||
|
||||
if (!self->aq_link_status.mbps)
|
||||
return 0;
|
||||
|
||||
hw_atl_utils_mpi_read_stats(self, &mbox);
|
||||
|
||||
#define AQ_SDELTA(_N_) (hw_self->curr_stats._N_ += \
|
||||
mbox.stats._N_ - hw_self->last_stats._N_)
|
||||
|
||||
AQ_SDELTA(uprc);
|
||||
AQ_SDELTA(mprc);
|
||||
AQ_SDELTA(bprc);
|
||||
AQ_SDELTA(erpt);
|
||||
|
||||
AQ_SDELTA(uptc);
|
||||
AQ_SDELTA(mptc);
|
||||
AQ_SDELTA(bptc);
|
||||
AQ_SDELTA(erpr);
|
||||
|
||||
AQ_SDELTA(ubrc);
|
||||
AQ_SDELTA(ubtc);
|
||||
AQ_SDELTA(mbrc);
|
||||
AQ_SDELTA(mbtc);
|
||||
AQ_SDELTA(bbrc);
|
||||
AQ_SDELTA(bbtc);
|
||||
AQ_SDELTA(dpc);
|
||||
|
||||
#undef AQ_SDELTA
|
||||
|
||||
memcpy(&hw_self->last_stats, &mbox.stats, sizeof(mbox.stats));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int hw_atl_utils_get_hw_stats(struct aq_hw_s *self,
|
||||
u64 *data, unsigned int *p_count)
|
||||
{
|
||||
struct hw_atl_stats_s *stats = NULL;
|
||||
struct hw_atl_s *hw_self = PHAL_ATLANTIC;
|
||||
struct hw_atl_stats_s *stats = &hw_self->curr_stats;
|
||||
int i = 0;
|
||||
|
||||
hw_atl_utils_mpi_read_stats(self, &PHAL_ATLANTIC->mbox);
|
||||
|
||||
stats = &PHAL_ATLANTIC->mbox.stats;
|
||||
|
||||
data[i] = stats->uprc + stats->mprc + stats->bprc;
|
||||
data[++i] = stats->uprc;
|
||||
data[++i] = stats->mprc;
|
||||
|
|
|
@ -115,19 +115,22 @@ struct __packed hw_aq_atl_utils_fw_rpc {
|
|||
};
|
||||
};
|
||||
|
||||
struct __packed hw_aq_atl_utils_mbox {
|
||||
struct __packed hw_aq_atl_utils_mbox_header {
|
||||
u32 version;
|
||||
u32 transaction_id;
|
||||
int error;
|
||||
u32 error;
|
||||
};
|
||||
|
||||
struct __packed hw_aq_atl_utils_mbox {
|
||||
struct hw_aq_atl_utils_mbox_header header;
|
||||
struct hw_atl_stats_s stats;
|
||||
};
|
||||
|
||||
struct __packed hw_atl_s {
|
||||
struct aq_hw_s base;
|
||||
struct hw_aq_atl_utils_mbox mbox;
|
||||
struct hw_atl_stats_s last_stats;
|
||||
struct hw_atl_stats_s curr_stats;
|
||||
u64 speed;
|
||||
u32 itr_tx;
|
||||
u32 itr_rx;
|
||||
unsigned int chip_features;
|
||||
u32 fw_ver_actual;
|
||||
atomic_t dpc;
|
||||
|
@ -170,6 +173,9 @@ enum hal_atl_utils_fw_state_e {
|
|||
|
||||
void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p);
|
||||
|
||||
int hw_atl_utils_mpi_read_mbox(struct aq_hw_s *self,
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struct hw_aq_atl_utils_mbox_header *pmbox);
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void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self,
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struct hw_aq_atl_utils_mbox *pmbox);
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@ -199,6 +205,8 @@ int hw_atl_utils_hw_deinit(struct aq_hw_s *self);
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int hw_atl_utils_get_fw_version(struct aq_hw_s *self, u32 *fw_version);
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||||
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int hw_atl_utils_update_stats(struct aq_hw_s *self);
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||||
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int hw_atl_utils_get_hw_stats(struct aq_hw_s *self,
|
||||
u64 *data,
|
||||
unsigned int *p_count);
|
||||
|
|
Loading…
Reference in New Issue