mxc: changes to common plat-mxc code to add support for i.MX5
Prepare for i.MX5 SoC code by adding the relevant macros to common plat-mxc code. Signed-off-by: Amit Kucheria <amit.kucheria@canonical.com>
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@ -45,6 +45,15 @@
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#define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
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#define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
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#endif
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#endif
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#ifdef CONFIG_ARCH_MX5
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#ifdef UART_PADDR
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#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
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#endif
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#include <mach/mx51.h>
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#define UART_PADDR MX51_UART1_BASE_ADDR
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#define UART_VADDR MX51_AIPS1_IO_ADDRESS(MX51_UART1_BASE_ADDR)
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#endif
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#ifdef CONFIG_ARCH_MXC91231
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#ifdef CONFIG_ARCH_MXC91231
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#ifdef UART_PADDR
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#ifdef UART_PADDR
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#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
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#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
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@ -27,6 +27,10 @@
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(((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\
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(((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\
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(addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0))
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(addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0))
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#ifdef CONFIG_ARCH_MX5
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#include <mach/mx51.h>
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#endif
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#ifdef CONFIG_ARCH_MX3
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#ifdef CONFIG_ARCH_MX3
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#include <mach/mx3x.h>
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#include <mach/mx3x.h>
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#include <mach/mx31.h>
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#include <mach/mx31.h>
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@ -30,6 +30,8 @@
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#define MXC_GPIO_IRQS (32 * 3)
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#define MXC_GPIO_IRQS (32 * 3)
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#elif defined CONFIG_ARCH_MX25
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#elif defined CONFIG_ARCH_MX25
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#define MXC_GPIO_IRQS (32 * 4)
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#define MXC_GPIO_IRQS (32 * 4)
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#elif defined CONFIG_ARCH_MX5
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#define MXC_GPIO_IRQS (32 * 4)
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#elif defined CONFIG_ARCH_MXC91231
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#elif defined CONFIG_ARCH_MXC91231
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#define MXC_GPIO_IRQS (32 * 4)
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#define MXC_GPIO_IRQS (32 * 4)
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#endif
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#endif
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@ -55,6 +57,7 @@
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#else
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#else
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#define MX3_IPU_IRQS 0
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#define MX3_IPU_IRQS 0
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#endif
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#endif
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/* REVISIT: Add IPU irqs on IMX51 */
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#define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS)
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#define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS)
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@ -16,6 +16,7 @@
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#define MX25_PHYS_OFFSET UL(0x80000000)
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#define MX25_PHYS_OFFSET UL(0x80000000)
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#define MX27_PHYS_OFFSET UL(0xa0000000)
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#define MX27_PHYS_OFFSET UL(0xa0000000)
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#define MX3x_PHYS_OFFSET UL(0x80000000)
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#define MX3x_PHYS_OFFSET UL(0x80000000)
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#define MX51_PHYS_OFFSET UL(0x90000000)
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#define MXC91231_PHYS_OFFSET UL(0x90000000)
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#define MXC91231_PHYS_OFFSET UL(0x90000000)
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#if !defined(CONFIG_RUNTIME_PHYS_OFFSET)
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#if !defined(CONFIG_RUNTIME_PHYS_OFFSET)
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@ -31,6 +32,8 @@
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# define PHYS_OFFSET MX3x_PHYS_OFFSET
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# define PHYS_OFFSET MX3x_PHYS_OFFSET
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# elif defined CONFIG_ARCH_MXC91231
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# elif defined CONFIG_ARCH_MXC91231
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# define PHYS_OFFSET MXC91231_PHYS_OFFSET
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# define PHYS_OFFSET MXC91231_PHYS_OFFSET
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# elif defined CONFIG_ARCH_MX5
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# define PHYS_OFFSET MX51_PHYS_OFFSET
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# endif
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# endif
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#endif
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#endif
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@ -30,6 +30,7 @@
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#define MXC_CPU_MX27 27
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#define MXC_CPU_MX27 27
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#define MXC_CPU_MX31 31
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#define MXC_CPU_MX31 31
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#define MXC_CPU_MX35 35
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#define MXC_CPU_MX35 35
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#define MXC_CPU_MX51 51
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#define MXC_CPU_MXC91231 91231
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#define MXC_CPU_MXC91231 91231
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLY__
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@ -108,6 +109,18 @@ extern unsigned int __mxc_cpu_type;
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# define cpu_is_mx35() (0)
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# define cpu_is_mx35() (0)
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#endif
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#endif
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#ifdef CONFIG_ARCH_MX5
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# ifdef mxc_cpu_type
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# undef mxc_cpu_type
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# define mxc_cpu_type __mxc_cpu_type
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# else
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# define mxc_cpu_type MXC_CPU_MX51
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# endif
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# define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51)
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#else
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# define cpu_is_mx51() (0)
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#endif
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#ifdef CONFIG_ARCH_MXC91231
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#ifdef CONFIG_ARCH_MXC91231
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# ifdef mxc_cpu_type
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# ifdef mxc_cpu_type
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# undef mxc_cpu_type
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# undef mxc_cpu_type
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@ -28,6 +28,8 @@
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#define CLOCK_TICK_RATE 16625000
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#define CLOCK_TICK_RATE 16625000
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#elif defined CONFIG_ARCH_MX25
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#elif defined CONFIG_ARCH_MX25
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#define CLOCK_TICK_RATE 16000000
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#define CLOCK_TICK_RATE 16000000
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#elif defined CONFIG_ARCH_MX5
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#define CLOCK_TICK_RATE 8000000
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#elif defined CONFIG_ARCH_MXC91231
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#elif defined CONFIG_ARCH_MXC91231
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#define CLOCK_TICK_RATE 13000000
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#define CLOCK_TICK_RATE 13000000
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#endif
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#endif
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