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fbdev updates for 3.4 

It includes:
 - drivers for Samsung Exynos MIPI DSI and display port
 - i740fb to support those old Intel chips
 - large updates to OMAP, viafb and sh_mobile_lcdcfb
 - some updates to s3c-fb and udlfb, few patches to others
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Merge tag 'fbdev-updates-for-3.4' of git://github.com/schandinat/linux-2.6

Pull fbdev updates for 3.4 from Florian Tobias Schandinat:
 - drivers for Samsung Exynos MIPI DSI and display port
 - i740fb to support those old Intel chips
 - large updates to OMAP, viafb and sh_mobile_lcdcfb
 - some updates to s3c-fb and udlfb, few patches to others

Fix up conflicts in drivers/video/udlfb.c due to Key Sievers' fix making
it in twice.

* tag 'fbdev-updates-for-3.4' of git://github.com/schandinat/linux-2.6: (156 commits)
  Revert "video:uvesafb: Fix oops that uvesafb try to execute NX-protected page"
  OMAPDSS: register dss drivers in module init
  video: pxafb: add clk_prepare/clk_unprepare calls
  fbdev: bfin_adv7393fb: Drop needless include
  fbdev: sh_mipi_dsi: add extra phyctrl for sh_mipi_dsi_info
  fbdev: remove dependency of FB_SH_MOBILE_MERAM from FB_SH_MOBILE_LCDC
  Revert "MAINTAINERS: add entry for exynos mipi display drivers"
  fbdev: da8xx: add support for SP10Q010 display
  fbdev: da8xx:: fix reporting of the display timing info
  drivers/video/pvr2fb.c: ensure arguments to request_irq and free_irq are compatible
  OMAPDSS: APPLY: fix clearing shadow dirty flag with manual update
  fbdev: sh_mobile_meram: Implement system suspend/resume
  fbdev: sh_mobile_meram: Remove unneeded sanity checks
  fbdev: sh_mobile_meram: Don't perform update in register operation
  arm: mach-shmobile: Constify sh_mobile_meram_cfg structures
  fbdev: sh_mobile_lcdc: Don't store copy of platform data
  fbdev: sh_mobile_meram: Remove unused sh_mobile_meram_icb_cfg fields
  arm: mach-shmobile: Don't set MERAM ICB numbers in platform data
  fbdev: sh_mobile_meram: Allocate ICBs automatically
  fbdev: sh_mobile_meram: Use genalloc to manage MERAM allocation
  ...
This commit is contained in:
Linus Torvalds 2012-03-22 20:43:40 -07:00
parent 9586c959bf 6bff98b455
commit 437538267b
146 changed files with 12364 additions and 8245 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

33
MAINTAINERS
View File

@ -2257,6 +2257,15 @@ F: Documentation/filesystems/quota.txt
F: fs/quota/
F: include/linux/quota*.h
DISPLAYLINK USB 2.0 FRAMEBUFFER DRIVER (UDLFB)
M: Bernie Thompson <bernie@plugable.com>
L: linux-fbdev@vger.kernel.org
S: Maintained
W: http://plugable.com/category/projects/udlfb/
F: drivers/video/udlfb.c
F: include/video/udlfb.h
F: Documentation/fb/udlfb.txt
DISTRIBUTED LOCK MANAGER (DLM)
M: Christine Caulfield <ccaulfie@redhat.com>
M: David Teigland <teigland@redhat.com>
@ -2378,15 +2387,6 @@ S: Supported
F: drivers/gpu/drm/exynos
F: include/drm/exynos*
EXYNOS MIPI DISPLAY DRIVERS
M: Inki Dae <inki.dae@samsung.com>
M: Donghwa Lee <dh09.lee@samsung.com>
M: Kyungmin Park <kyungmin.park@samsung.com>
L: linux-fbdev@vger.kernel.org
S: Maintained
F: drivers/video/exynos/exynos_mipi*
F: include/video/exynos_mipi*
DSCC4 DRIVER
M: Francois Romieu <romieu@fr.zoreil.com>
L: netdev@vger.kernel.org
@ -2667,6 +2667,21 @@ M: Mimi Zohar <zohar@us.ibm.com>
S: Supported
F: security/integrity/evm/
EXYNOS DP DRIVER
M: Jingoo Han <jg1.han@samsung.com>
L: linux-fbdev@vger.kernel.org
S: Maintained
F: drivers/video/exynos/exynos_dp*
EXYNOS MIPI DISPLAY DRIVERS
M: Inki Dae <inki.dae@samsung.com>
M: Donghwa Lee <dh09.lee@samsung.com>
M: Kyungmin Park <kyungmin.park@samsung.com>
L: linux-fbdev@vger.kernel.org
S: Maintained
F: drivers/video/exynos/exynos_mipi*
F: include/video/exynos_mipi*
F71805F HARDWARE MONITORING DRIVER
M: Jean Delvare <khali@linux-fr.org>
L: lm-sensors@lm-sensors.org

9
arch/arm/mach-omap1/board-ams-delta.c
View File

@ -20,6 +20,7 @@
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/export.h>
#include <linux/omapfb.h>
#include <media/soc_camera.h>
@ -169,10 +170,6 @@ static struct omap_usb_config ams_delta_usb_config __initdata = {
.pins[0] = 2,
};
static struct omap_board_config_kernel ams_delta_config[] __initdata = {
{ OMAP_TAG_LCD, &ams_delta_lcd_config },
};
static struct resource ams_delta_nand_resources[] = {
[0] = {
.start = OMAP1_MPUIO_BASE,
@ -302,8 +299,6 @@ static void __init ams_delta_init(void)
omap_cfg_reg(J19_1610_CAM_D6);
omap_cfg_reg(J18_1610_CAM_D7);
omap_board_config = ams_delta_config;
omap_board_config_size = ARRAY_SIZE(ams_delta_config);
omap_serial_init();
omap_register_i2c_bus(1, 100, NULL, 0);
@ -321,6 +316,8 @@ static void __init ams_delta_init(void)
ams_delta_init_fiq();
omap_writew(omap_readw(ARM_RSTCT1) | 0x0004, ARM_RSTCT1);
omapfb_set_lcd_config(&ams_delta_lcd_config);
}
static struct plat_serial8250_port ams_delta_modem_ports[] = {

15
arch/arm/mach-omap1/board-fsample.c
View File

@ -21,6 +21,7 @@
#include <linux/mtd/physmap.h>
#include <linux/input.h>
#include <linux/smc91x.h>
#include <linux/omapfb.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
@ -273,27 +274,17 @@ static struct platform_device kp_device = {
.resource = kp_resources,
};
static struct platform_device lcd_device = {
.name = "lcd_p2",
.id = -1,
};
static struct platform_device *devices[] __initdata = {
&nor_device,
&nand_device,
&smc91x_device,
&kp_device,
&lcd_device,
};
static struct omap_lcd_config fsample_lcd_config = {
.ctrl_name = "internal",
};
static struct omap_board_config_kernel fsample_config[] __initdata = {
{ OMAP_TAG_LCD, &fsample_lcd_config },
};
static void __init omap_fsample_init(void)
{
/* Early, board-dependent init */
@ -352,10 +343,10 @@ static void __init omap_fsample_init(void)
platform_add_devices(devices, ARRAY_SIZE(devices));
omap_board_config = fsample_config;
omap_board_config_size = ARRAY_SIZE(fsample_config);
omap_serial_init();
omap_register_i2c_bus(1, 100, NULL, 0);
omapfb_set_lcd_config(&fsample_lcd_config);
}
/* Only FPGA needs to be mapped here. All others are done with ioremap */

15
arch/arm/mach-omap1/board-h2.c
View File

@ -30,6 +30,7 @@
#include <linux/input.h>
#include <linux/i2c/tps65010.h>
#include <linux/smc91x.h>
#include <linux/omapfb.h>
#include <mach/hardware.h>
@ -325,18 +326,12 @@ static struct platform_device h2_irda_device = {
.resource = h2_irda_resources,
};
static struct platform_device h2_lcd_device = {
.name = "lcd_h2",
.id = -1,
};
static struct platform_device *h2_devices[] __initdata = {
&h2_nor_device,
&h2_nand_device,
&h2_smc91x_device,
&h2_irda_device,
&h2_kp_device,
&h2_lcd_device,
};
static void __init h2_init_smc91x(void)
@ -391,10 +386,6 @@ static struct omap_lcd_config h2_lcd_config __initdata = {
.ctrl_name = "internal",
};
static struct omap_board_config_kernel h2_config[] __initdata = {
{ OMAP_TAG_LCD, &h2_lcd_config },
};
static void __init h2_init(void)
{
h2_init_smc91x();
@ -438,13 +429,13 @@ static void __init h2_init(void)
omap_cfg_reg(N19_1610_KBR5);
platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices));
omap_board_config = h2_config;
omap_board_config_size = ARRAY_SIZE(h2_config);
omap_serial_init();
omap_register_i2c_bus(1, 100, h2_i2c_board_info,
ARRAY_SIZE(h2_i2c_board_info));
omap1_usb_init(&h2_usb_config);
h2_mmc_init();
omapfb_set_lcd_config(&h2_lcd_config);
}
MACHINE_START(OMAP_H2, "TI-H2")

9
arch/arm/mach-omap1/board-h3.c
View File

@ -30,6 +30,7 @@
#include <linux/spi/spi.h>
#include <linux/i2c/tps65010.h>
#include <linux/smc91x.h>
#include <linux/omapfb.h>
#include <asm/setup.h>
#include <asm/page.h>
@ -370,10 +371,6 @@ static struct omap_lcd_config h3_lcd_config __initdata = {
.ctrl_name = "internal",
};
static struct omap_board_config_kernel h3_config[] __initdata = {
{ OMAP_TAG_LCD, &h3_lcd_config },
};
static struct i2c_board_info __initdata h3_i2c_board_info[] = {
{
I2C_BOARD_INFO("tps65013", 0x48),
@ -426,13 +423,13 @@ static void __init h3_init(void)
platform_add_devices(devices, ARRAY_SIZE(devices));
spi_register_board_info(h3_spi_board_info,
ARRAY_SIZE(h3_spi_board_info));
omap_board_config = h3_config;
omap_board_config_size = ARRAY_SIZE(h3_config);
omap_serial_init();
omap_register_i2c_bus(1, 100, h3_i2c_board_info,
ARRAY_SIZE(h3_i2c_board_info));
omap1_usb_init(&h3_usb_config);
h3_mmc_init();
omapfb_set_lcd_config(&h3_lcd_config);
}
MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")

9
arch/arm/mach-omap1/board-htcherald.c
View File

@ -36,6 +36,7 @@
#include <linux/leds.h>
#include <linux/spi/spi.h>
#include <linux/spi/ads7846.h>
#include <linux/omapfb.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@ -398,10 +399,6 @@ static struct omap_lcd_config htcherald_lcd_config __initdata = {
.ctrl_name = "internal",
};
static struct omap_board_config_kernel htcherald_config[] __initdata = {
{ OMAP_TAG_LCD, &htcherald_lcd_config },
};
static struct platform_device lcd_device = {
.name = "lcd_htcherald",
.id = -1,
@ -580,8 +577,6 @@ static void __init htcherald_init(void)
printk(KERN_INFO "HTC Herald init.\n");
/* Do board initialization before we register all the devices */
omap_board_config = htcherald_config;
omap_board_config_size = ARRAY_SIZE(htcherald_config);
platform_add_devices(devices, ARRAY_SIZE(devices));
htcherald_disable_watchdog();
@ -598,6 +593,8 @@ static void __init htcherald_init(void)
htc_mmc_data[0] = &htc_mmc1_data;
omap1_init_mmc(htc_mmc_data, 1);
#endif
omapfb_set_lcd_config(&htcherald_lcd_config);
}
MACHINE_START(HERALD, "HTC Herald")

11
arch/arm/mach-omap1/board-innovator.c
View File

@ -25,6 +25,7 @@
#include <linux/mtd/physmap.h>
#include <linux/input.h>
#include <linux/smc91x.h>
#include <linux/omapfb.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
@ -370,10 +371,6 @@ static inline void innovator_mmc_init(void)
}
#endif
static struct omap_board_config_kernel innovator_config[] = {
{ OMAP_TAG_LCD, NULL },
};
static void __init innovator_init(void)
{
if (cpu_is_omap1510())
@ -416,17 +413,15 @@ static void __init innovator_init(void)
#ifdef CONFIG_ARCH_OMAP15XX
if (cpu_is_omap1510()) {
omap1_usb_init(&innovator1510_usb_config);
innovator_config[0].data = &innovator1510_lcd_config;
omapfb_set_lcd_config(&innovator1510_lcd_config);
}
#endif
#ifdef CONFIG_ARCH_OMAP16XX
if (cpu_is_omap1610()) {
omap1_usb_init(&h2_usb_config);
innovator_config[0].data = &innovator1610_lcd_config;
omapfb_set_lcd_config(&innovator1610_lcd_config);
}
#endif
omap_board_config = innovator_config;
omap_board_config_size = ARRAY_SIZE(innovator_config);
omap_serial_init();
omap_register_i2c_bus(1, 100, NULL, 0);
innovator_mmc_init();

19
arch/arm/mach-omap1/board-nokia770.c
View File

@ -31,7 +31,6 @@
#include <plat/board.h>
#include <plat/keypad.h>
#include "common.h"
#include <plat/hwa742.h>
#include <plat/lcd_mipid.h>
#include <plat/mmc.h>
#include <plat/clock.h>
@ -99,15 +98,16 @@ static struct mipid_platform_data nokia770_mipid_platform_data = {
.shutdown = mipid_shutdown,
};
static struct omap_lcd_config nokia770_lcd_config __initdata = {
.ctrl_name = "hwa742",
};
static void __init mipid_dev_init(void)
{
const struct omap_lcd_config *conf;
nokia770_mipid_platform_data.nreset_gpio = 13;
nokia770_mipid_platform_data.data_lines = 16;
conf = omap_get_config(OMAP_TAG_LCD, struct omap_lcd_config);
if (conf != NULL) {
nokia770_mipid_platform_data.nreset_gpio = conf->nreset_gpio;
nokia770_mipid_platform_data.data_lines = conf->data_lines;
}
omapfb_set_lcd_config(&nokia770_lcd_config);
}
static void __init ads7846_dev_init(void)
@ -150,14 +150,9 @@ static struct spi_board_info nokia770_spi_board_info[] __initdata = {
},
};
static struct hwa742_platform_data nokia770_hwa742_platform_data = {
.te_connected = 1,
};
static void __init hwa742_dev_init(void)
{
clk_add_alias("hwa_sys_ck", NULL, "bclk", NULL);
omapfb_set_ctrl_platform_data(&nokia770_hwa742_platform_data);
}
/* assume no Mini-AB port */

14
arch/arm/mach-omap1/board-osk.c
View File

@ -34,6 +34,7 @@
#include <linux/i2c.h>
#include <linux/leds.h>
#include <linux/smc91x.h>
#include <linux/omapfb.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
@ -300,12 +301,6 @@ static struct omap_lcd_config osk_lcd_config __initdata = {
};
#endif
static struct omap_board_config_kernel osk_config[] __initdata = {
#ifdef CONFIG_OMAP_OSK_MISTRAL
{ OMAP_TAG_LCD, &osk_lcd_config },
#endif
};
#ifdef CONFIG_OMAP_OSK_MISTRAL
#include <linux/input.h>
@ -549,8 +544,6 @@ static void __init osk_init(void)
osk_flash_resource.end = osk_flash_resource.start = omap_cs3_phys();
osk_flash_resource.end += SZ_32M - 1;
platform_add_devices(osk5912_devices, ARRAY_SIZE(osk5912_devices));
omap_board_config = osk_config;
omap_board_config_size = ARRAY_SIZE(osk_config);
l = omap_readl(USB_TRANSCEIVER_CTRL);
l |= (3 << 1);
@ -567,6 +560,11 @@ static void __init osk_init(void)
omap_register_i2c_bus(1, 400, osk_i2c_board_info,
ARRAY_SIZE(osk_i2c_board_info));
osk_mistral_init();
#ifdef CONFIG_OMAP_OSK_MISTRAL
omapfb_set_lcd_config(&osk_lcd_config);
#endif
}
MACHINE_START(OMAP_OSK, "TI-OSK")

10
arch/arm/mach-omap1/board-palmte.c
View File

@ -27,6 +27,7 @@
#include <linux/spi/spi.h>
#include <linux/interrupt.h>
#include <linux/apm-emulation.h>
#include <linux/omapfb.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
@ -209,10 +210,6 @@ static struct omap_lcd_config palmte_lcd_config __initdata = {
.ctrl_name = "internal",
};
static struct omap_board_config_kernel palmte_config[] __initdata = {
{ OMAP_TAG_LCD, &palmte_lcd_config },
};
static struct spi_board_info palmte_spi_info[] __initdata = {
{
.modalias = "tsc2102",
@ -250,9 +247,6 @@ static void __init omap_palmte_init(void)
omap_cfg_reg(UART3_TX);
omap_cfg_reg(UART3_RX);
omap_board_config = palmte_config;
omap_board_config_size = ARRAY_SIZE(palmte_config);
platform_add_devices(palmte_devices, ARRAY_SIZE(palmte_devices));
spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info));
@ -260,6 +254,8 @@ static void __init omap_palmte_init(void)
omap_serial_init();
omap1_usb_init(&palmte_usb_config);
omap_register_i2c_bus(1, 100, NULL, 0);
omapfb_set_lcd_config(&palmte_lcd_config);
}
MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")

10
arch/arm/mach-omap1/board-palmtt.c
View File

@ -24,6 +24,7 @@
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/leds.h>
#include <linux/omapfb.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
@ -273,10 +274,6 @@ static struct omap_lcd_config palmtt_lcd_config __initdata = {
.ctrl_name = "internal",
};
static struct omap_board_config_kernel palmtt_config[] __initdata = {
{ OMAP_TAG_LCD, &palmtt_lcd_config },
};
static void __init omap_mpu_wdt_mode(int mode) {
if (mode)
omap_writew(0x8000, OMAP_WDT_TIMER_MODE);
@ -298,15 +295,14 @@ static void __init omap_palmtt_init(void)
omap_mpu_wdt_mode(0);
omap_board_config = palmtt_config;
omap_board_config_size = ARRAY_SIZE(palmtt_config);
platform_add_devices(palmtt_devices, ARRAY_SIZE(palmtt_devices));
spi_register_board_info(palmtt_boardinfo,ARRAY_SIZE(palmtt_boardinfo));
omap_serial_init();
omap1_usb_init(&palmtt_usb_config);
omap_register_i2c_bus(1, 100, NULL, 0);
omapfb_set_lcd_config(&palmtt_lcd_config);
}
MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T")

10
arch/arm/mach-omap1/board-palmz71.c
View File

@ -27,6 +27,7 @@
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/omapfb.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
@ -239,10 +240,6 @@ static struct omap_lcd_config palmz71_lcd_config __initdata = {
.ctrl_name = "internal",
};
static struct omap_board_config_kernel palmz71_config[] __initdata = {
{OMAP_TAG_LCD, &palmz71_lcd_config},
};
static irqreturn_t
palmz71_powercable(int irq, void *dev_id)
{
@ -313,9 +310,6 @@ omap_palmz71_init(void)
palmz71_gpio_setup(1);
omap_mpu_wdt_mode(0);
omap_board_config = palmz71_config;
omap_board_config_size = ARRAY_SIZE(palmz71_config);
platform_add_devices(devices, ARRAY_SIZE(devices));
spi_register_board_info(palmz71_boardinfo,
@ -324,6 +318,8 @@ omap_palmz71_init(void)
omap_serial_init();
omap_register_i2c_bus(1, 100, NULL, 0);
palmz71_gpio_setup(0);
omapfb_set_lcd_config(&palmz71_lcd_config);
}
MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71")

15
arch/arm/mach-omap1/board-perseus2.c
View File

@ -21,6 +21,7 @@
#include <linux/mtd/physmap.h>
#include <linux/input.h>
#include <linux/smc91x.h>
#include <linux/omapfb.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
@ -232,27 +233,17 @@ static struct platform_device kp_device = {
.resource = kp_resources,
};
static struct platform_device lcd_device = {
.name = "lcd_p2",
.id = -1,
};
static struct platform_device *devices[] __initdata = {
&nor_device,
&nand_device,
&smc91x_device,
&kp_device,
&lcd_device,
};
static struct omap_lcd_config perseus2_lcd_config __initdata = {
.ctrl_name = "internal",
};
static struct omap_board_config_kernel perseus2_config[] __initdata = {
{ OMAP_TAG_LCD, &perseus2_lcd_config },
};
static void __init perseus2_init_smc91x(void)
{
fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
@ -320,10 +311,10 @@ static void __init omap_perseus2_init(void)
platform_add_devices(devices, ARRAY_SIZE(devices));
omap_board_config = perseus2_config;
omap_board_config_size = ARRAY_SIZE(perseus2_config);
omap_serial_init();
omap_register_i2c_bus(1, 100, NULL, 0);
omapfb_set_lcd_config(&perseus2_lcd_config);
}
/* Only FPGA needs to be mapped here. All others are done with ioremap */

16
arch/arm/mach-omap1/board-sx1.c
View File

@ -27,6 +27,7 @@
#include <linux/i2c.h>
#include <linux/errno.h>
#include <linux/export.h>
#include <linux/omapfb.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
@ -355,11 +356,6 @@ static struct omap_usb_config sx1_usb_config __initdata = {
/*----------- LCD -------------------------*/
static struct platform_device sx1_lcd_device = {
.name = "lcd_sx1",
.id = -1,
};
static struct omap_lcd_config sx1_lcd_config __initdata = {
.ctrl_name = "internal",
};
@ -368,14 +364,8 @@ static struct omap_lcd_config sx1_lcd_config __initdata = {
static struct platform_device *sx1_devices[] __initdata = {
&sx1_flash_device,
&sx1_kp_device,
&sx1_lcd_device,
&sx1_irda_device,
};
/*-----------------------------------------*/
static struct omap_board_config_kernel sx1_config[] __initdata = {
{ OMAP_TAG_LCD, &sx1_lcd_config },
};
/*-----------------------------------------*/
@ -391,8 +381,6 @@ static void __init omap_sx1_init(void)
platform_add_devices(sx1_devices, ARRAY_SIZE(sx1_devices));
omap_board_config = sx1_config;
omap_board_config_size = ARRAY_SIZE(sx1_config);
omap_serial_init();
omap_register_i2c_bus(1, 100, NULL, 0);
omap1_usb_init(&sx1_usb_config);
@ -406,6 +394,8 @@ static void __init omap_sx1_init(void)
gpio_direction_output(1, 1); /*A_IRDA_OFF = 1 */
gpio_direction_output(11, 0); /*A_SWITCH = 0 */
gpio_direction_output(15, 0); /*A_USB_ON = 0 */
omapfb_set_lcd_config(&sx1_lcd_config);
}
MACHINE_START(SX1, "OMAP310 based Siemens SX1")

1
arch/arm/mach-omap2/io.c
View File

@ -21,7 +21,6 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/omapfb.h>
#include <asm/tlb.h>

24
arch/arm/mach-shmobile/board-ag5evm.c
View File

@ -230,16 +230,6 @@ static void lcd_backlight_reset(void)
gpio_set_value(GPIO_PORT235, 1);
}
static void lcd_on(void *board_data, struct fb_info *info)
{
lcd_backlight_on();
}
static void lcd_off(void *board_data)
{
lcd_backlight_reset();
}
/* LCDC0 */
static const struct fb_videomode lcdc0_modes[] = {
{
@ -263,14 +253,14 @@ static struct sh_mobile_lcdc_info lcdc0_info = {
.interface_type = RGB24,
.clock_divider = 1,
.flags = LCDC_FLAGS_DWPOL,
.lcd_size_cfg.width = 44,
.lcd_size_cfg.height = 79,
.fourcc = V4L2_PIX_FMT_RGB565,
.lcd_cfg = lcdc0_modes,
.num_cfg = ARRAY_SIZE(lcdc0_modes),
.board_cfg = {
.display_on = lcd_on,
.display_off = lcd_off,
.lcd_modes = lcdc0_modes,
.num_modes = ARRAY_SIZE(lcdc0_modes),
.panel_cfg = {
.width = 44,
.height = 79,
.display_on = lcd_backlight_on,
.display_off = lcd_backlight_reset,
},
}
};

302
arch/arm/mach-shmobile/board-ap4evb.c
View File

@ -258,10 +258,16 @@ static struct sh_mobile_meram_info meram_info = {
static struct resource meram_resources[] = {
[0] = {
.name = "MERAM",
.start = 0xe8000000,
.end = 0xe81fffff,
.flags = IORESOURCE_MEM,
.name = "regs",
.start = 0xe8000000,
.end = 0xe807ffff,
.flags = IORESOURCE_MEM,
},
[1] = {
.name = "meram",
.start = 0xe8080000,
.end = 0xe81fffff,
.flags = IORESOURCE_MEM,
},
};
@ -437,82 +443,6 @@ static struct platform_device usb1_host_device = {
.resource = usb1_host_resources,
};
static const struct fb_videomode ap4evb_lcdc_modes[] = {
{
#ifdef CONFIG_AP4EVB_QHD
.name = "R63302(QHD)",
.xres = 544,
.yres = 961,
.left_margin = 72,
.right_margin = 600,
.hsync_len = 16,
.upper_margin = 8,
.lower_margin = 8,
.vsync_len = 2,
.sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
#else
.name = "WVGA Panel",
.xres = 800,
.yres = 480,
.left_margin = 220,
.right_margin = 110,
.hsync_len = 70,
.upper_margin = 20,
.lower_margin = 5,
.vsync_len = 5,
.sync = 0,
#endif
},
};
static struct sh_mobile_meram_cfg lcd_meram_cfg = {
.icb[0] = {
.marker_icb = 28,
.cache_icb = 24,
.meram_offset = 0x0,
.meram_size = 0x40,
},
.icb[1] = {
.marker_icb = 29,
.cache_icb = 25,
.meram_offset = 0x40,
.meram_size = 0x40,
},
};
static struct sh_mobile_lcdc_info lcdc_info = {
.meram_dev = &meram_info,
.ch[0] = {
.chan = LCDC_CHAN_MAINLCD,
.fourcc = V4L2_PIX_FMT_RGB565,
.lcd_cfg = ap4evb_lcdc_modes,
.num_cfg = ARRAY_SIZE(ap4evb_lcdc_modes),
.meram_cfg = &lcd_meram_cfg,
}
};
static struct resource lcdc_resources[] = {
[0] = {
.name = "LCDC",
.start = 0xfe940000, /* P4-only space */
.end = 0xfe943fff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = intcs_evt2irq(0x580),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device lcdc_device = {
.name = "sh_mobile_lcdc_fb",
.num_resources = ARRAY_SIZE(lcdc_resources),
.resource = lcdc_resources,
.dev = {
.platform_data = &lcdc_info,
.coherent_dma_mask = ~0,
},
};
/*
* QHD display
*/
@ -556,20 +486,25 @@ static struct platform_device keysc_device = {
};
/* MIPI-DSI */
#define PHYCTRL 0x0070
static int sh_mipi_set_dot_clock(struct platform_device *pdev,
void __iomem *base,
int enable)
{
struct clk *pck = clk_get(&pdev->dev, "dsip_clk");
void __iomem *phy = base + PHYCTRL;
if (IS_ERR(pck))
return PTR_ERR(pck);
if (enable) {
/*
* DSIPCLK = 24MHz
* D-PHY = DSIPCLK * ((0x6*2)+1) = 312MHz (see .phyctrl)
* HsByteCLK = D-PHY/8 = 39MHz
*
* X * Y * FPS =
* (544+72+600+16) * (961+8+8+2) * 30 = 36.1MHz
*/
clk_set_rate(pck, clk_round_rate(pck, 24000000));
iowrite32(ioread32(phy) | (0xb << 8), phy);
clk_enable(pck);
} else {
clk_disable(pck);
@ -593,11 +528,14 @@ static struct resource mipidsi0_resources[] = {
},
};
static struct sh_mobile_lcdc_info lcdc_info;
static struct sh_mipi_dsi_info mipidsi0_info = {
.data_format = MIPI_RGB888,
.lcd_chan = &lcdc_info.ch[0],
.lane = 2,
.vsynw_offset = 17,
.phyctrl = 0x6 << 8,
.flags = SH_MIPI_DSI_SYNC_PULSES_MODE |
SH_MIPI_DSI_HSbyteCLK,
.set_dot_clock = sh_mipi_set_dot_clock,
@ -619,6 +557,81 @@ static struct platform_device *qhd_devices[] __initdata = {
};
#endif /* CONFIG_AP4EVB_QHD */
/* LCDC0 */
static const struct fb_videomode ap4evb_lcdc_modes[] = {
{
#ifdef CONFIG_AP4EVB_QHD
.name = "R63302(QHD)",
.xres = 544,
.yres = 961,
.left_margin = 72,
.right_margin = 600,
.hsync_len = 16,
.upper_margin = 8,
.lower_margin = 8,
.vsync_len = 2,
.sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
#else
.name = "WVGA Panel",
.xres = 800,
.yres = 480,
.left_margin = 220,
.right_margin = 110,
.hsync_len = 70,
.upper_margin = 20,
.lower_margin = 5,
.vsync_len = 5,
.sync = 0,
#endif
},
};
static const struct sh_mobile_meram_cfg lcd_meram_cfg = {
.icb[0] = {
.meram_size = 0x40,
},
.icb[1] = {
.meram_size = 0x40,
},
};
static struct sh_mobile_lcdc_info lcdc_info = {
.meram_dev = &meram_info,
.ch[0] = {
.chan = LCDC_CHAN_MAINLCD,
.fourcc = V4L2_PIX_FMT_RGB565,
.lcd_modes = ap4evb_lcdc_modes,
.num_modes = ARRAY_SIZE(ap4evb_lcdc_modes),
.meram_cfg = &lcd_meram_cfg,
#ifdef CONFIG_AP4EVB_QHD
.tx_dev = &mipidsi0_device,
#endif
}
};
static struct resource lcdc_resources[] = {
[0] = {
.name = "LCDC",
.start = 0xfe940000, /* P4-only space */
.end = 0xfe943fff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = intcs_evt2irq(0x580),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device lcdc_device = {
.name = "sh_mobile_lcdc_fb",
.num_resources = ARRAY_SIZE(lcdc_resources),
.resource = lcdc_resources,
.dev = {
.platform_data = &lcdc_info,
.coherent_dma_mask = ~0,
},
};
/* FSI */
#define IRQ_FSI evt2irq(0x1840)
static int __fsi_set_rate(struct clk *clk, long rate, int enable)
@ -790,65 +803,11 @@ static struct platform_device fsi_ak4643_device = {
},
};
static struct sh_mobile_meram_cfg hdmi_meram_cfg = {
.icb[0] = {
.marker_icb = 30,
.cache_icb = 26,
.meram_offset = 0x80,
.meram_size = 0x100,
},
.icb[1] = {
.marker_icb = 31,
.cache_icb = 27,
.meram_offset = 0x180,
.meram_size = 0x100,
},
};
static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = {
.clock_source = LCDC_CLK_EXTERNAL,
.meram_dev = &meram_info,
.ch[0] = {
.chan = LCDC_CHAN_MAINLCD,
.fourcc = V4L2_PIX_FMT_RGB565,
.interface_type = RGB24,
.clock_divider = 1,
.flags = LCDC_FLAGS_DWPOL,
.meram_cfg = &hdmi_meram_cfg,
}
};
static struct resource lcdc1_resources[] = {
[0] = {
.name = "LCDC1",
.start = 0xfe944000,
.end = 0xfe947fff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = intcs_evt2irq(0x1780),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device lcdc1_device = {
.name = "sh_mobile_lcdc_fb",
.num_resources = ARRAY_SIZE(lcdc1_resources),
.resource = lcdc1_resources,
.id = 1,
.dev = {
.platform_data = &sh_mobile_lcdc1_info,
.coherent_dma_mask = ~0,
},
};
/* LCDC1 */
static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
unsigned long *parent_freq);
static struct sh_mobile_hdmi_info hdmi_info = {
.lcd_chan = &sh_mobile_lcdc1_info.ch[0],
.lcd_dev = &lcdc1_device.dev,
.flags = HDMI_SND_SRC_SPDIF,
.clk_optimize_parent = ap4evb_clk_optimize,
};
@ -877,10 +836,6 @@ static struct platform_device hdmi_device = {
},
};
static struct platform_device fsi_hdmi_device = {
.name = "sh_fsi2_b_hdmi",
};
static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
unsigned long *parent_freq)
{
@ -900,6 +855,57 @@ static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
return error;
}
static const struct sh_mobile_meram_cfg hdmi_meram_cfg = {
.icb[0] = {
.meram_size = 0x100,
},
.icb[1] = {
.meram_size = 0x100,
},
};
static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = {
.clock_source = LCDC_CLK_EXTERNAL,
.meram_dev = &meram_info,
.ch[0] = {
.chan = LCDC_CHAN_MAINLCD,
.fourcc = V4L2_PIX_FMT_RGB565,
.interface_type = RGB24,
.clock_divider = 1,
.flags = LCDC_FLAGS_DWPOL,
.meram_cfg = &hdmi_meram_cfg,
.tx_dev = &hdmi_device,
}
};
static struct resource lcdc1_resources[] = {
[0] = {
.name = "LCDC1",
.start = 0xfe944000,
.end = 0xfe947fff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = intcs_evt2irq(0x1780),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device lcdc1_device = {
.name = "sh_mobile_lcdc_fb",
.num_resources = ARRAY_SIZE(lcdc1_resources),
.resource = lcdc1_resources,
.id = 1,
.dev = {
.platform_data = &sh_mobile_lcdc1_info,
.coherent_dma_mask = ~0,
},
};
static struct platform_device fsi_hdmi_device = {
.name = "sh_fsi2_b_hdmi",
};
static struct gpio_led ap4evb_leds[] = {
{
.name = "led4",
@ -1034,9 +1040,9 @@ static struct platform_device *ap4evb_devices[] __initdata = {
&fsi_ak4643_device,
&fsi_hdmi_device,
&sh_mmcif_device,
&lcdc1_device,
&lcdc_device,
&hdmi_device,
&lcdc_device,
&lcdc1_device,
&ceu_device,
&ap4evb_camera,
&meram_device,
@ -1347,8 +1353,8 @@ static void __init ap4evb_init(void)
lcdc_info.ch[0].interface_type = RGB24;
lcdc_info.ch[0].clock_divider = 1;
lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL;
lcdc_info.ch[0].lcd_size_cfg.width = 44;
lcdc_info.ch[0].lcd_size_cfg.height = 79;
lcdc_info.ch[0].panel_cfg.width = 44;
lcdc_info.ch[0].panel_cfg.height = 79;
platform_add_devices(qhd_devices, ARRAY_SIZE(qhd_devices));
@ -1389,8 +1395,8 @@ static void __init ap4evb_init(void)
lcdc_info.ch[0].interface_type = RGB18;
lcdc_info.ch[0].clock_divider = 3;
lcdc_info.ch[0].flags = 0;
lcdc_info.ch[0].lcd_size_cfg.width = 152;
lcdc_info.ch[0].lcd_size_cfg.height = 91;
lcdc_info.ch[0].panel_cfg.width = 152;
lcdc_info.ch[0].panel_cfg.height = 91;
/* enable TouchScreen */
irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);

6
arch/arm/mach-shmobile/board-bonito.c
View File

@ -246,9 +246,9 @@ static struct sh_mobile_lcdc_info lcdc0_info = {
.interface_type = RGB24,
.clock_divider = 5,
.flags = 0,
.lcd_cfg = &lcdc0_mode,
.num_cfg = 1,
.lcd_size_cfg = {
.lcd_modes = &lcdc0_mode,
.num_modes = 1,
.panel_cfg = {
.width = 152,
.height = 91,
},

136
arch/arm/mach-shmobile/board-mackerel.c
View File

@ -318,8 +318,14 @@ static struct sh_mobile_meram_info mackerel_meram_info = {
static struct resource meram_resources[] = {
[0] = {
.name = "MERAM",
.name = "regs",
.start = 0xe8000000,
.end = 0xe807ffff,
.flags = IORESOURCE_MEM,
},
[1] = {
.name = "meram",
.start = 0xe8080000,
.end = 0xe81fffff,
.flags = IORESOURCE_MEM,
},
@ -351,29 +357,23 @@ static struct fb_videomode mackerel_lcdc_modes[] = {
},
};
static int mackerel_set_brightness(void *board_data, int brightness)
static int mackerel_set_brightness(int brightness)
{
gpio_set_value(GPIO_PORT31, brightness);
return 0;
}
static int mackerel_get_brightness(void *board_data)
static int mackerel_get_brightness(void)
{
return gpio_get_value(GPIO_PORT31);
}
static struct sh_mobile_meram_cfg lcd_meram_cfg = {
static const struct sh_mobile_meram_cfg lcd_meram_cfg = {
.icb[0] = {
.marker_icb = 28,
.cache_icb = 24,
.meram_offset = 0x0,
.meram_size = 0x40,
},
.icb[1] = {
.marker_icb = 29,
.cache_icb = 25,
.meram_offset = 0x40,
.meram_size = 0x40,
},
};
@ -384,20 +384,20 @@ static struct sh_mobile_lcdc_info lcdc_info = {
.ch[0] = {
.chan = LCDC_CHAN_MAINLCD,
.fourcc = V4L2_PIX_FMT_RGB565,
.lcd_cfg = mackerel_lcdc_modes,
.num_cfg = ARRAY_SIZE(mackerel_lcdc_modes),
.lcd_modes = mackerel_lcdc_modes,
.num_modes = ARRAY_SIZE(mackerel_lcdc_modes),
.interface_type = RGB24,
.clock_divider = 3,
.flags = 0,
.lcd_size_cfg.width = 152,
.lcd_size_cfg.height = 91,
.board_cfg = {
.set_brightness = mackerel_set_brightness,
.get_brightness = mackerel_get_brightness,
.panel_cfg = {
.width = 152,
.height = 91,
},
.bl_info = {
.name = "sh_mobile_lcdc_bl",
.max_brightness = 1,
.set_brightness = mackerel_set_brightness,
.get_brightness = mackerel_get_brightness,
},
.meram_cfg = &lcd_meram_cfg,
}
@ -426,61 +426,8 @@ static struct platform_device lcdc_device = {
},
};
static struct sh_mobile_meram_cfg hdmi_meram_cfg = {
.icb[0] = {
.marker_icb = 30,
.cache_icb = 26,
.meram_offset = 0x80,
.meram_size = 0x100,
},
.icb[1] = {
.marker_icb = 31,
.cache_icb = 27,
.meram_offset = 0x180,
.meram_size = 0x100,
},
};
/* HDMI */
static struct sh_mobile_lcdc_info hdmi_lcdc_info = {
.meram_dev = &mackerel_meram_info,
.clock_source = LCDC_CLK_EXTERNAL,
.ch[0] = {
.chan = LCDC_CHAN_MAINLCD,
.fourcc = V4L2_PIX_FMT_RGB565,
.interface_type = RGB24,
.clock_divider = 1,
.flags = LCDC_FLAGS_DWPOL,
.meram_cfg = &hdmi_meram_cfg,
}
};
static struct resource hdmi_lcdc_resources[] = {
[0] = {
.name = "LCDC1",
.start = 0xfe944000,
.end = 0xfe947fff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = intcs_evt2irq(0x1780),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device hdmi_lcdc_device = {
.name = "sh_mobile_lcdc_fb",
.num_resources = ARRAY_SIZE(hdmi_lcdc_resources),
.resource = hdmi_lcdc_resources,
.id = 1,
.dev = {
.platform_data = &hdmi_lcdc_info,
.coherent_dma_mask = ~0,
},
};
static struct sh_mobile_hdmi_info hdmi_info = {
.lcd_chan = &hdmi_lcdc_info.ch[0],
.lcd_dev = &hdmi_lcdc_device.dev,
.flags = HDMI_SND_SRC_SPDIF,
};
@ -508,6 +455,53 @@ static struct platform_device hdmi_device = {
},
};
static const struct sh_mobile_meram_cfg hdmi_meram_cfg = {
.icb[0] = {
.meram_size = 0x100,
},
.icb[1] = {
.meram_size = 0x100,
},
};
static struct sh_mobile_lcdc_info hdmi_lcdc_info = {
.meram_dev = &mackerel_meram_info,
.clock_source = LCDC_CLK_EXTERNAL,
.ch[0] = {
.chan = LCDC_CHAN_MAINLCD,
.fourcc = V4L2_PIX_FMT_RGB565,
.interface_type = RGB24,
.clock_divider = 1,
.flags = LCDC_FLAGS_DWPOL,
.meram_cfg = &hdmi_meram_cfg,
.tx_dev = &hdmi_device,
}
};
static struct resource hdmi_lcdc_resources[] = {
[0] = {
.name = "LCDC1",
.start = 0xfe944000,
.end = 0xfe947fff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = intcs_evt2irq(0x1780),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device hdmi_lcdc_device = {
.name = "sh_mobile_lcdc_fb",
.num_resources = ARRAY_SIZE(hdmi_lcdc_resources),
.resource = hdmi_lcdc_resources,
.id = 1,
.dev = {
.platform_data = &hdmi_lcdc_info,
.coherent_dma_mask = ~0,
},
};
static struct platform_device fsi_hdmi_device = {
.name = "sh_fsi2_b_hdmi",
};
@ -1274,8 +1268,8 @@ static struct platform_device *mackerel_devices[] __initdata = {
&sh_mmcif_device,
&ceu_device,
&mackerel_camera,
&hdmi_lcdc_device,
&hdmi_device,
&hdmi_lcdc_device,
&meram_device,
};

2
arch/arm/plat-omap/common.c
View File

@ -15,7 +15,6 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/dma-mapping.h>
#include <linux/omapfb.h>
#include <plat/common.h>
#include <plat/board.h>
@ -65,7 +64,6 @@ const void *__init omap_get_var_config(u16 tag, size_t *len)
void __init omap_reserve(void)
{
omapfb_reserve_sdram_memblock();
omap_vram_reserve_sdram_memblock();
omap_dsp_reserve_sdram_memblock();
omap_secure_ram_reserve_memblock();

336
arch/arm/plat-omap/fb.c
View File

@ -34,15 +34,11 @@
#include <asm/mach/map.h>
#include <plat/board.h>
#include <plat/sram.h>
#include "fb.h"
#if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
static bool omapfb_lcd_configured;
static struct omapfb_platform_data omapfb_config;
static int config_invalid;
static int configured_regions;
static u64 omap_fb_dma_mask = ~(u32)0;
@ -57,301 +53,20 @@ static struct platform_device omap_fb_device = {
.num_resources = 0,
};
void omapfb_set_platform_data(struct omapfb_platform_data *data)
void __init omapfb_set_lcd_config(const struct omap_lcd_config *config)
{
}
static inline int ranges_overlap(unsigned long start1, unsigned long size1,
unsigned long start2, unsigned long size2)
{
return (start1 >= start2 && start1 < start2 + size2) ||
(start2 >= start1 && start2 < start1 + size1);
}
static inline int range_included(unsigned long start1, unsigned long size1,
unsigned long start2, unsigned long size2)
{
return start1 >= start2 && start1 + size1 <= start2 + size2;
}
/* Check if there is an overlapping region. */
static int fbmem_region_reserved(unsigned long start, size_t size)
{
struct omapfb_mem_region *rg;
int i;
rg = &omapfb_config.mem_desc.region[0];
for (i = 0; i < OMAPFB_PLANE_NUM; i++, rg++) {
if (!rg->paddr)
/* Empty slot. */
continue;
if (ranges_overlap(start, size, rg->paddr, rg->size))
return 1;
}
return 0;
}
/*
* Get the region_idx`th region from board config/ATAG and convert it to
* our internal format.
*/
static int __init get_fbmem_region(int region_idx, struct omapfb_mem_region *rg)
{
const struct omap_fbmem_config *conf;
u32 paddr;
conf = omap_get_nr_config(OMAP_TAG_FBMEM,
struct omap_fbmem_config, region_idx);
if (conf == NULL)
return -ENOENT;
paddr = conf->start;
/*
* Low bits encode the page allocation mode, if high bits
* are zero. Otherwise we need a page aligned fixed
* address.
*/
memset(rg, 0, sizeof(*rg));
rg->type = paddr & ~PAGE_MASK;
rg->paddr = paddr & PAGE_MASK;
rg->size = PAGE_ALIGN(conf->size);
return 0;
}
static int set_fbmem_region_type(struct omapfb_mem_region *rg, int mem_type,
unsigned long mem_start,
unsigned long mem_size)
{
/*
* Check if the configuration specifies the type explicitly.
* type = 0 && paddr = 0, a default don't care case maps to
* the SDRAM type.
*/
if (rg->type || !rg->paddr)
return 0;
if (ranges_overlap(rg->paddr, rg->size, mem_start, mem_size)) {
rg->type = mem_type;
return 0;
}
/* Can't determine it. */
return -1;
}
static int check_fbmem_region(int region_idx, struct omapfb_mem_region *rg,
unsigned long start_avail, unsigned size_avail)
{
unsigned long paddr = rg->paddr;
size_t size = rg->size;
if (rg->type > OMAPFB_MEMTYPE_MAX) {
printk(KERN_ERR
"Invalid start address for FB region %d\n", region_idx);
return -EINVAL;
}
if (!rg->size) {
printk(KERN_ERR "Zero size for FB region %d\n", region_idx);
return -EINVAL;
}
if (!paddr)
/* Allocate this dynamically, leave paddr 0 for now. */
return 0;
/*
* Fixed region for the given RAM range. Check if it's already
* reserved by the FB code or someone else.
*/
if (fbmem_region_reserved(paddr, size) ||
!range_included(paddr, size, start_avail, size_avail)) {
printk(KERN_ERR "Trying to use reserved memory "
"for FB region %d\n", region_idx);
return -EINVAL;
}
return 0;
}
static int valid_sdram(unsigned long addr, unsigned long size)
{
return memblock_is_region_memory(addr, size);
}
static int reserve_sdram(unsigned long addr, unsigned long size)
{
if (memblock_is_region_reserved(addr, size))
return -EBUSY;
if (memblock_reserve(addr, size))
return -ENOMEM;
return 0;
}
/*
* Called from map_io. We need to call to this early enough so that we
* can reserve the fixed SDRAM regions before VM could get hold of them.
*/
void __init omapfb_reserve_sdram_memblock(void)
{
unsigned long reserved = 0;
int i;
if (config_invalid)
return;
for (i = 0; ; i++) {
struct omapfb_mem_region rg;
if (get_fbmem_region(i, &rg) < 0)
break;
if (i == OMAPFB_PLANE_NUM) {
pr_err("Extraneous FB mem configuration entries\n");
config_invalid = 1;
return;
}
/* Check if it's our memory type. */
if (rg.type != OMAPFB_MEMTYPE_SDRAM)
continue;
/* Check if the region falls within SDRAM */
if (rg.paddr && !valid_sdram(rg.paddr, rg.size))
continue;
if (rg.size == 0) {
pr_err("Zero size for FB region %d\n", i);
config_invalid = 1;
return;
}
if (rg.paddr) {
if (reserve_sdram(rg.paddr, rg.size)) {
pr_err("Trying to use reserved memory for FB region %d\n",
i);
config_invalid = 1;
return;
}
reserved += rg.size;
}
if (omapfb_config.mem_desc.region[i].size) {
pr_err("FB region %d already set\n", i);
config_invalid = 1;
return;
}
omapfb_config.mem_desc.region[i] = rg;
configured_regions++;
}
omapfb_config.mem_desc.region_cnt = i;
if (reserved)
pr_info("Reserving %lu bytes SDRAM for frame buffer\n",
reserved);
}
/*
* Called at sram init time, before anything is pushed to the SRAM stack.
* Because of the stack scheme, we will allocate everything from the
* start of the lowest address region to the end of SRAM. This will also
* include padding for page alignment and possible holes between regions.
*
* As opposed to the SDRAM case, we'll also do any dynamic allocations at
* this point, since the driver built as a module would have problem with
* freeing / reallocating the regions.
*/
unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart,
unsigned long sram_vstart,
unsigned long sram_size,
unsigned long pstart_avail,
unsigned long size_avail)
{
struct omapfb_mem_region rg;
unsigned long pend_avail;
unsigned long reserved;
int i;
if (config_invalid)
return 0;
reserved = 0;
pend_avail = pstart_avail + size_avail;
for (i = 0; ; i++) {
if (get_fbmem_region(i, &rg) < 0)
break;
if (i == OMAPFB_PLANE_NUM) {
printk(KERN_ERR
"Extraneous FB mem configuration entries\n");
config_invalid = 1;
return 0;
}
/* Check if it's our memory type. */
if (set_fbmem_region_type(&rg, OMAPFB_MEMTYPE_SRAM,
sram_pstart, sram_size) < 0 ||
(rg.type != OMAPFB_MEMTYPE_SRAM))
continue;
BUG_ON(omapfb_config.mem_desc.region[i].size);
if (check_fbmem_region(i, &rg, pstart_avail, size_avail) < 0) {
config_invalid = 1;
return 0;
}
if (!rg.paddr) {
/* Dynamic allocation */
if ((size_avail & PAGE_MASK) < rg.size) {
printk("Not enough SRAM for FB region %d\n",
i);
config_invalid = 1;
return 0;
}
size_avail = (size_avail - rg.size) & PAGE_MASK;
rg.paddr = pstart_avail + size_avail;
}
/* Reserve everything above the start of the region. */
if (pend_avail - rg.paddr > reserved)
reserved = pend_avail - rg.paddr;
size_avail = pend_avail - reserved - pstart_avail;
/*
* We have a kernel mapping for this already, so the
* driver won't have to make one.
*/
rg.vaddr = (void *)(sram_vstart + rg.paddr - sram_pstart);
omapfb_config.mem_desc.region[i] = rg;
configured_regions++;
}
omapfb_config.mem_desc.region_cnt = i;
if (reserved)
pr_info("Reserving %lu bytes SRAM for frame buffer\n",
reserved);
return reserved;
}
void omapfb_set_ctrl_platform_data(void *data)
{
omapfb_config.ctrl_platform_data = data;
omapfb_config.lcd = *config;
omapfb_lcd_configured = true;
}
static int __init omap_init_fb(void)
{
const struct omap_lcd_config *conf;
if (config_invalid)
/*
* If the board file has not set the lcd config with
* omapfb_set_lcd_config(), don't bother registering the omapfb device
*/
if (!omapfb_lcd_configured)
return 0;
if (configured_regions != omapfb_config.mem_desc.region_cnt) {
printk(KERN_ERR "Invalid FB mem configuration entries\n");
return 0;
}
conf = omap_get_config(OMAP_TAG_LCD, struct omap_lcd_config);
if (conf == NULL) {
if (configured_regions)
/* FB mem config, but no LCD config? */
printk(KERN_ERR "Missing LCD configuration\n");
return 0;
}
omapfb_config.lcd = *conf;
return platform_device_register(&omap_fb_device);
}
@ -374,11 +89,6 @@ static struct platform_device omap_fb_device = {
.num_resources = 0,
};
void omapfb_set_platform_data(struct omapfb_platform_data *data)
{
omapfb_config = *data;
}
static int __init omap_init_fb(void)
{
return platform_device_register(&omap_fb_device);
@ -386,36 +96,10 @@ static int __init omap_init_fb(void)
arch_initcall(omap_init_fb);
void omapfb_reserve_sdram_memblock(void)
{
}
unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart,
unsigned long sram_vstart,
unsigned long sram_size,
unsigned long start_avail,
unsigned long size_avail)
{
return 0;
}
#else
void omapfb_set_platform_data(struct omapfb_platform_data *data)
void __init omapfb_set_lcd_config(const struct omap_lcd_config *config)
{
}
void omapfb_reserve_sdram_memblock(void)
{
}
unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart,
unsigned long sram_vstart,
unsigned long sram_size,
unsigned long start_avail,
unsigned long size_avail)
{
return 0;
}
#endif

10
arch/arm/plat-omap/fb.h
View File

@ -1,10 +0,0 @@
#ifndef __PLAT_OMAP_FB_H__
#define __PLAT_OMAP_FB_H__
extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
unsigned long sram_vstart,
unsigned long sram_size,
unsigned long pstart_avail,
unsigned long size_avail);
#endif /* __PLAT_OMAP_FB_H__ */

12
arch/arm/plat-omap/include/plat/blizzard.h
View File

@ -1,12 +0,0 @@
#ifndef _BLIZZARD_H
#define _BLIZZARD_H
struct blizzard_platform_data {
void (*power_up)(struct device *dev);
void (*power_down)(struct device *dev);
unsigned long (*get_clock_rate)(struct device *dev);
unsigned te_connected:1;
};
#endif

2
arch/arm/plat-omap/include/plat/board.h
View File

@ -28,9 +28,7 @@ enum {
/* Different peripheral ids */
#define OMAP_TAG_CLOCK 0x4f01
#define OMAP_TAG_LCD 0x4f05
#define OMAP_TAG_GPIO_SWITCH 0x4f06
#define OMAP_TAG_FBMEM 0x4f08
#define OMAP_TAG_STI_CONSOLE 0x4f09
#define OMAP_TAG_CAMERA_SENSOR 0x4f0a

8
arch/arm/plat-omap/include/plat/hwa742.h
View File

@ -1,8 +0,0 @@
#ifndef _HWA742_H
#define _HWA742_H
struct hwa742_platform_data {
unsigned te_connected:1;
};
#endif

21
arch/arm/plat-omap/include/plat/vram.h
View File

@ -23,40 +23,21 @@
#include <linux/types.h>
#define OMAP_VRAM_MEMTYPE_SDRAM 0
#define OMAP_VRAM_MEMTYPE_SRAM 1
#define OMAP_VRAM_MEMTYPE_MAX 1
extern int omap_vram_add_region(unsigned long paddr, size_t size);
extern int omap_vram_free(unsigned long paddr, size_t size);
extern int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr);
extern int omap_vram_alloc(size_t size, unsigned long *paddr);
extern int omap_vram_reserve(unsigned long paddr, size_t size);
extern void omap_vram_get_info(unsigned long *vram, unsigned long *free_vram,
unsigned long *largest_free_block);
#ifdef CONFIG_OMAP2_VRAM
extern void omap_vram_set_sdram_vram(u32 size, u32 start);
extern void omap_vram_set_sram_vram(u32 size, u32 start);
extern void omap_vram_reserve_sdram_memblock(void);
extern unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
unsigned long sram_vstart,
unsigned long sram_size,
unsigned long pstart_avail,
unsigned long size_avail);
#else
static inline void omap_vram_set_sdram_vram(u32 size, u32 start) { }
static inline void omap_vram_set_sram_vram(u32 size, u32 start) { }
static inline void omap_vram_reserve_sdram_memblock(void) { }
static inline unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
unsigned long sram_vstart,
unsigned long sram_size,
unsigned long pstart_avail,
unsigned long size_avail)
{
return 0;
}
#endif
#endif

33
arch/arm/plat-samsung/include/plat/regs-fb.h
View File

@ -91,6 +91,9 @@
#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)
#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13)
#define VIDCON1_VCLK_MASK (0x3 << 9)
#define VIDCON1_VCLK_HOLD (0x0 << 9)
#define VIDCON1_VCLK_RUN (0x1 << 9)
#define VIDCON1_INV_VCLK (1 << 7)
#define VIDCON1_INV_HSYNC (1 << 6)
@ -164,15 +167,17 @@
#define VIDTCON1_HSPW(_x) ((_x) << 0)
#define VIDTCON2 (0x18)
#define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
#define VIDTCON2_LINEVAL_SHIFT (11)
#define VIDTCON2_LINEVAL_LIMIT (0x7ff)
#define VIDTCON2_LINEVAL(_x) ((_x) << 11)
#define VIDTCON2_LINEVAL(_x) (((_x) & 0x7ff) << 11)
#define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >> 11) << 22)
#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)
#define VIDTCON2_HOZVAL_SHIFT (0)
#define VIDTCON2_HOZVAL_LIMIT (0x7ff)
#define VIDTCON2_HOZVAL(_x) ((_x) << 0)
#define VIDTCON2_HOZVAL(_x) (((_x) & 0x7ff) << 0)
/* WINCONx */
@ -228,25 +233,29 @@
/* Local input channels (windows 0-2) */
#define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win)))
#define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)
#define VIDOSDxA_TOPLEFT_X_SHIFT (11)
#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff)
#define VIDOSDxA_TOPLEFT_X(_x) ((_x) << 11)
#define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x7ff) << 11)
#define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)
#define VIDOSDxA_TOPLEFT_Y_SHIFT (0)
#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff)
#define VIDOSDxA_TOPLEFT_Y(_x) ((_x) << 0)
#define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x7ff) << 0)
#define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)
#define VIDOSDxB_BOTRIGHT_X_SHIFT (11)
#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff)
#define VIDOSDxB_BOTRIGHT_X(_x) ((_x) << 11)
#define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x7ff) << 11)
#define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)
#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0)
#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff)
#define VIDOSDxB_BOTRIGHT_Y(_x) ((_x) << 0)
#define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x7ff) << 0)
/* For VIDOSD[1..4]C */
#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)
@ -278,15 +287,17 @@
#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
#define VIDW_BUF_SIZE_OFFSET_E(_x) ((((_x) & 0x2000) >> 13) << 27)
#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)
#define VIDW_BUF_SIZE_OFFSET_SHIFT (13)
#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff)
#define VIDW_BUF_SIZE_OFFSET(_x) ((_x) << 13)
#define VIDW_BUF_SIZE_OFFSET(_x) (((_x) & 0x1fff) << 13)
#define VIDW_BUF_SIZE_PAGEWIDTH_E(_x) ((((_x) & 0x2000) >> 13) << 26)
#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0)
#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0)
#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff)
#define VIDW_BUF_SIZE_PAGEWIDTH(_x) ((_x) << 0)
#define VIDW_BUF_SIZE_PAGEWIDTH(_x) (((_x) & 0x1fff) << 0)
/* Interrupt controls and status */
@ -384,3 +395,9 @@
#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
/* Blending equation control */
#define BLENDCON (0x260)
#define BLENDCON_NEW_MASK (1 << 0)
#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)

22
arch/sh/boards/mach-ap325rxa/setup.c
View File

@ -157,7 +157,7 @@ static struct platform_device nand_flash_device = {
#define PORT_DRVCRA 0xA405018A
#define PORT_DRVCRB 0xA405018C
static int ap320_wvga_set_brightness(void *board_data, int brightness)
static int ap320_wvga_set_brightness(int brightness)
{
if (brightness) {
gpio_set_value(GPIO_PTS3, 0);
@ -170,12 +170,12 @@ static int ap320_wvga_set_brightness(void *board_data, int brightness)
return 0;
}
static int ap320_wvga_get_brightness(void *board_data)
static int ap320_wvga_get_brightness(void)
{
return gpio_get_value(GPIO_PTS3);
}
static void ap320_wvga_power_on(void *board_data, struct fb_info *info)
static void ap320_wvga_power_on(void)
{
msleep(100);
@ -183,7 +183,7 @@ static void ap320_wvga_power_on(void *board_data, struct fb_info *info)
__raw_writew(FPGA_LCDREG_VAL, FPGA_LCDREG);
}
static void ap320_wvga_power_off(void *board_data)
static void ap320_wvga_power_off(void)
{
/* ASD AP-320/325 LCD OFF */
__raw_writew(0, FPGA_LCDREG);
@ -211,21 +211,19 @@ static struct sh_mobile_lcdc_info lcdc_info = {
.fourcc = V4L2_PIX_FMT_RGB565,
.interface_type = RGB18,
.clock_divider = 1,
.lcd_cfg = ap325rxa_lcdc_modes,
.num_cfg = ARRAY_SIZE(ap325rxa_lcdc_modes),
.lcd_size_cfg = { /* 7.0 inch */
.width = 152,
.lcd_modes = ap325rxa_lcdc_modes,
.num_modes = ARRAY_SIZE(ap325rxa_lcdc_modes),
.panel_cfg = {
.width = 152, /* 7.0 inch */
.height = 91,
},
.board_cfg = {
.display_on = ap320_wvga_power_on,
.display_off = ap320_wvga_power_off,
.set_brightness = ap320_wvga_set_brightness,
.get_brightness = ap320_wvga_get_brightness,
},
.bl_info = {
.name = "sh_mobile_lcdc_bl",
.max_brightness = 1,
.set_brightness = ap320_wvga_set_brightness,
.get_brightness = ap320_wvga_get_brightness,
},
}
};

20
arch/sh/boards/mach-ecovec24/setup.c
View File

@ -310,14 +310,14 @@ static const struct fb_videomode ecovec_dvi_modes[] = {
},
};
static int ecovec24_set_brightness(void *board_data, int brightness)
static int ecovec24_set_brightness(int brightness)
{
gpio_set_value(GPIO_PTR1, brightness);
return 0;
}
static int ecovec24_get_brightness(void *board_data)
static int ecovec24_get_brightness(void)
{
return gpio_get_value(GPIO_PTR1);
}
@ -327,17 +327,15 @@ static struct sh_mobile_lcdc_info lcdc_info = {
.interface_type = RGB18,
.chan = LCDC_CHAN_MAINLCD,
.fourcc = V4L2_PIX_FMT_RGB565,
.lcd_size_cfg = { /* 7.0 inch */
.panel_cfg = { /* 7.0 inch */
.width = 152,
.height = 91,
},
.board_cfg = {
.set_brightness = ecovec24_set_brightness,
.get_brightness = ecovec24_get_brightness,
},
.bl_info = {
.name = "sh_mobile_lcdc_bl",
.max_brightness = 1,
.set_brightness = ecovec24_set_brightness,
.get_brightness = ecovec24_get_brightness,
},
}
};
@ -1118,8 +1116,8 @@ static int __init arch_setup(void)
/* DVI */
lcdc_info.clock_source = LCDC_CLK_EXTERNAL;
lcdc_info.ch[0].clock_divider = 1;
lcdc_info.ch[0].lcd_cfg = ecovec_dvi_modes;
lcdc_info.ch[0].num_cfg = ARRAY_SIZE(ecovec_dvi_modes);
lcdc_info.ch[0].lcd_modes = ecovec_dvi_modes;
lcdc_info.ch[0].num_modes = ARRAY_SIZE(ecovec_dvi_modes);
gpio_set_value(GPIO_PTA2, 1);
gpio_set_value(GPIO_PTU1, 1);
@ -1127,8 +1125,8 @@ static int __init arch_setup(void)
/* Panel */
lcdc_info.clock_source = LCDC_CLK_PERIPHERAL;
lcdc_info.ch[0].clock_divider = 2;
lcdc_info.ch[0].lcd_cfg = ecovec_lcd_modes;
lcdc_info.ch[0].num_cfg = ARRAY_SIZE(ecovec_lcd_modes);
lcdc_info.ch[0].lcd_modes = ecovec_lcd_modes;
lcdc_info.ch[0].num_modes = ARRAY_SIZE(ecovec_lcd_modes);
gpio_set_value(GPIO_PTR1, 1);

10
arch/sh/boards/mach-kfr2r09/lcd_wqvga.c
View File

@ -251,8 +251,7 @@ static void display_on(void *sohandle,
write_memory_start(sohandle, so);
}
int kfr2r09_lcd_setup(void *board_data, void *sohandle,
struct sh_mobile_lcdc_sys_bus_ops *so)
int kfr2r09_lcd_setup(void *sohandle, struct sh_mobile_lcdc_sys_bus_ops *so)
{
/* power on */
gpio_set_value(GPIO_PTF4, 0); /* PROTECT/ -> L */
@ -273,8 +272,7 @@ int kfr2r09_lcd_setup(void *board_data, void *sohandle,
return 0;
}
void kfr2r09_lcd_start(void *board_data, void *sohandle,
struct sh_mobile_lcdc_sys_bus_ops *so)
void kfr2r09_lcd_start(void *sohandle, struct sh_mobile_lcdc_sys_bus_ops *so)
{
write_memory_start(sohandle, so);
}
@ -327,12 +325,12 @@ static int kfr2r09_lcd_backlight(int on)
return 0;
}
void kfr2r09_lcd_on(void *board_data, struct fb_info *info)
void kfr2r09_lcd_on(void)
{
kfr2r09_lcd_backlight(1);
}
void kfr2r09_lcd_off(void *board_data)
void kfr2r09_lcd_off(void)
{
kfr2r09_lcd_backlight(0);
}

8
arch/sh/boards/mach-kfr2r09/setup.c
View File

@ -148,13 +148,11 @@ static struct sh_mobile_lcdc_info kfr2r09_sh_lcdc_info = {
.interface_type = SYS18,
.clock_divider = 6,
.flags = LCDC_FLAGS_DWPOL,
.lcd_cfg = kfr2r09_lcdc_modes,
.num_cfg = ARRAY_SIZE(kfr2r09_lcdc_modes),
.lcd_size_cfg = {
.lcd_modes = kfr2r09_lcdc_modes,
.num_modes = ARRAY_SIZE(kfr2r09_lcdc_modes),
.panel_cfg = {
.width = 35,
.height = 58,
},
.board_cfg = {
.setup_sys = kfr2r09_lcd_setup,
.start_transfer = kfr2r09_lcd_start,
.display_on = kfr2r09_lcd_on,

3
arch/sh/boards/mach-migor/lcd_qvga.c
View File

@ -113,8 +113,7 @@ static const unsigned short magic3_data[] = {
0x0010, 0x16B0, 0x0011, 0x0111, 0x0007, 0x0061,
};
int migor_lcd_qvga_setup(void *board_data, void *sohandle,
struct sh_mobile_lcdc_sys_bus_ops *so)
int migor_lcd_qvga_setup(void *sohandle, struct sh_mobile_lcdc_sys_bus_ops *so)
{
unsigned long xres = 320;
unsigned long yres = 240;

16
arch/sh/boards/mach-migor/setup.c
View File

@ -246,9 +246,9 @@ static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
.fourcc = V4L2_PIX_FMT_RGB565,
.interface_type = RGB16,
.clock_divider = 2,
.lcd_cfg = migor_lcd_modes,
.num_cfg = ARRAY_SIZE(migor_lcd_modes),
.lcd_size_cfg = { /* 7.0 inch */
.lcd_modes = migor_lcd_modes,
.num_modes = ARRAY_SIZE(migor_lcd_modes),
.panel_cfg = { /* 7.0 inch */
.width = 152,
.height = 91,
},
@ -260,13 +260,11 @@ static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
.fourcc = V4L2_PIX_FMT_RGB565,
.interface_type = SYS16A,
.clock_divider = 10,
.lcd_cfg = migor_lcd_modes,
.num_cfg = ARRAY_SIZE(migor_lcd_modes),
.lcd_size_cfg = { /* 2.4 inch */
.width = 49,
.lcd_modes = migor_lcd_modes,
.num_modes = ARRAY_SIZE(migor_lcd_modes),
.panel_cfg = {
.width = 49, /* 2.4 inch */
.height = 37,
},
.board_cfg = {
.setup_sys = migor_lcd_qvga_setup,
},
.sys_bus_cfg = {

12
arch/sh/boards/mach-se/7724/setup.c
View File

@ -182,12 +182,10 @@ static struct sh_mobile_lcdc_info lcdc_info = {
.chan = LCDC_CHAN_MAINLCD,
.fourcc = V4L2_PIX_FMT_RGB565,
.clock_divider = 1,
.lcd_size_cfg = { /* 7.0 inch */
.panel_cfg = { /* 7.0 inch */
.width = 152,
.height = 91,
},
.board_cfg = {
},
}
};
@ -890,12 +888,12 @@ static int __init devices_setup(void)
if (sw & SW41_B) {
/* 720p */
lcdc_info.ch[0].lcd_cfg = lcdc_720p_modes;
lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_720p_modes);
lcdc_info.ch[0].lcd_modes = lcdc_720p_modes;
lcdc_info.ch[0].num_modes = ARRAY_SIZE(lcdc_720p_modes);
} else {
/* VGA */
lcdc_info.ch[0].lcd_cfg = lcdc_vga_modes;
lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_vga_modes);
lcdc_info.ch[0].lcd_modes = lcdc_vga_modes;
lcdc_info.ch[0].num_modes = ARRAY_SIZE(lcdc_vga_modes);
}
if (sw & SW41_A) {

16
arch/sh/include/mach-kfr2r09/mach/kfr2r09.h
View File

@ -4,21 +4,21 @@
#include <video/sh_mobile_lcdc.h>
#if defined(CONFIG_FB_SH_MOBILE_LCDC) || defined(CONFIG_FB_SH_MOBILE_LCDC_MODULE)
void kfr2r09_lcd_on(void *board_data, struct fb_info *info);
void kfr2r09_lcd_off(void *board_data);
int kfr2r09_lcd_setup(void *board_data, void *sys_ops_handle,
void kfr2r09_lcd_on(void);
void kfr2r09_lcd_off(void);
int kfr2r09_lcd_setup(void *sys_ops_handle,
struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
void kfr2r09_lcd_start(void *board_data, void *sys_ops_handle,
void kfr2r09_lcd_start(void *sys_ops_handle,
struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
#else
static void kfr2r09_lcd_on(void *board_data) {}
static void kfr2r09_lcd_off(void *board_data) {}
static int kfr2r09_lcd_setup(void *board_data, void *sys_ops_handle,
static void kfr2r09_lcd_on(void) {}
static void kfr2r09_lcd_off(void) {}
static int kfr2r09_lcd_setup(void *sys_ops_handle,
struct sh_mobile_lcdc_sys_bus_ops *sys_ops)
{
return -ENODEV;
}
static void kfr2r09_lcd_start(void *board_data, void *sys_ops_handle,
static void kfr2r09_lcd_start(void *sys_ops_handle,
struct sh_mobile_lcdc_sys_bus_ops *sys_ops)
{
}

2
arch/sh/include/mach-migor/mach/migor.h
View File

@ -9,7 +9,7 @@
#include <video/sh_mobile_lcdc.h>
int migor_lcd_qvga_setup(void *board_data, void *sys_ops_handle,
int migor_lcd_qvga_setup(void *sys_ops_handle,
struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
#endif /* __ASM_SH_MIGOR_H */

39
drivers/video/Kconfig
View File

@ -1123,6 +1123,18 @@ config FB_RIVA_BACKLIGHT
help
Say Y here if you want to control the backlight of your display.
config FB_I740
tristate "Intel740 support (EXPERIMENTAL)"
depends on EXPERIMENTAL && FB && PCI
select FB_MODE_HELPERS
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
select VGASTATE
select FB_DDC
help
This driver supports graphics cards based on Intel740 chip.
config FB_I810
tristate "Intel 810/815 support (EXPERIMENTAL)"
depends on EXPERIMENTAL && FB && PCI && X86_32 && AGP_INTEL
@ -2001,18 +2013,6 @@ config FB_SH_MOBILE_HDMI
---help---
Driver for the on-chip SH-Mobile HDMI controller.
config FB_SH_MOBILE_MERAM
tristate "SuperH Mobile MERAM read ahead support for LCDC"
depends on FB_SH_MOBILE_LCDC
default y
---help---
Enable MERAM support for the SH-Mobile LCD controller.
This will allow for caching of the framebuffer to provide more
reliable access under heavy main memory bus traffic situations.
Up to 4 memory channels can be configured, allowing 4 RGB or
2 YCbCr framebuffers to be configured.
config FB_TMIO
tristate "Toshiba Mobile IO FrameBuffer support"
depends on FB && MFD_CORE
@ -2233,6 +2233,7 @@ config FB_DA8XX
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
select FB_CFB_REV_PIXELS_IN_BYTE
---help---
This is the frame buffer device driver for the TI LCD controller
found on DA8xx/OMAP-L1xx SoCs.
@ -2412,7 +2413,7 @@ config FB_PUV3_UNIGFX
source "drivers/video/omap/Kconfig"
source "drivers/video/omap2/Kconfig"
source "drivers/video/exynos/Kconfig"
source "drivers/video/backlight/Kconfig"
if VT
@ -2423,4 +2424,16 @@ if FB || SGI_NEWPORT_CONSOLE
source "drivers/video/logo/Kconfig"
endif
config FB_SH_MOBILE_MERAM
tristate "SuperH Mobile MERAM read ahead support"
depends on (SUPERH || ARCH_SHMOBILE)
select GENERIC_ALLOCATOR
---help---
Enable MERAM support for the SuperH controller.
This will allow for caching of the framebuffer to provide more
reliable access under heavy main memory bus traffic situations.
Up to 4 memory channels can be configured, allowing 4 RGB or
2 YCbCr framebuffers to be configured.
endmenu

3
drivers/video/Makefile
View File

@ -15,6 +15,8 @@ obj-$(CONFIG_VT) += console/
obj-$(CONFIG_LOGO) += logo/
obj-y += backlight/
obj-$(CONFIG_EXYNOS_VIDEO) += exynos/
obj-$(CONFIG_FB_CFB_FILLRECT) += cfbfillrect.o
obj-$(CONFIG_FB_CFB_COPYAREA) += cfbcopyarea.o
obj-$(CONFIG_FB_CFB_IMAGEBLIT) += cfbimgblt.o
@ -37,6 +39,7 @@ obj-$(CONFIG_FB_GRVGA) += grvga.o
obj-$(CONFIG_FB_PM2) += pm2fb.o
obj-$(CONFIG_FB_PM3) += pm3fb.o
obj-$(CONFIG_FB_I740) += i740fb.o
obj-$(CONFIG_FB_MATROX) += matrox/
obj-$(CONFIG_FB_RIVA) += riva/
obj-$(CONFIG_FB_NVIDIA) += nvidia/

12
drivers/video/atmel_lcdfb.c
View File

@ -421,24 +421,18 @@ static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var,
var->red.length = var->green.length = var->blue.length
= var->bits_per_pixel;
break;
case 15:
case 16:
if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
/* RGB:565 mode */
var->red.offset = 11;
var->blue.offset = 0;
var->green.length = 6;
} else if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB555) {
var->red.offset = 10;
var->blue.offset = 0;
var->green.length = 5;
} else {
/* BGR:555 mode */
/* BGR:565 mode */
var->red.offset = 0;
var->blue.offset = 10;
var->green.length = 5;
var->blue.offset = 11;
}
var->green.offset = 5;
var->green.length = 6;
var->red.length = var->blue.length = 5;
break;
case 32:

32
drivers/video/au1100fb.c
View File

@ -477,7 +477,8 @@ static int __devinit au1100fb_drv_probe(struct platform_device *dev)
u32 sys_clksrc;
/* Allocate new device private */
fbdev = kzalloc(sizeof(struct au1100fb_device), GFP_KERNEL);
fbdev = devm_kzalloc(&dev->dev, sizeof(struct au1100fb_device),
GFP_KERNEL);
if (!fbdev) {
print_err("fail to allocate device private record");
return -ENOMEM;
@ -498,8 +499,9 @@ static int __devinit au1100fb_drv_probe(struct platform_device *dev)
au1100fb_fix.mmio_start = regs_res->start;
au1100fb_fix.mmio_len = resource_size(regs_res);
if (!request_mem_region(au1100fb_fix.mmio_start, au1100fb_fix.mmio_len,
DRIVER_NAME)) {
if (!devm_request_mem_region(au1100fb_fix.mmio_start,
au1100fb_fix.mmio_len,
DRIVER_NAME)) {
print_err("fail to lock memory region at 0x%08lx",
au1100fb_fix.mmio_start);
return -EBUSY;
@ -514,8 +516,9 @@ static int __devinit au1100fb_drv_probe(struct platform_device *dev)
fbdev->fb_len = fbdev->panel->xres * fbdev->panel->yres *
(fbdev->panel->bpp >> 3) * AU1100FB_NBR_VIDEO_BUFFERS;
fbdev->fb_mem = dma_alloc_coherent(&dev->dev, PAGE_ALIGN(fbdev->fb_len),
&fbdev->fb_phys, GFP_KERNEL);
fbdev->fb_mem = dmam_alloc_coherent(&dev->dev, &dev->dev,
PAGE_ALIGN(fbdev->fb_len),
&fbdev->fb_phys, GFP_KERNEL);
if (!fbdev->fb_mem) {
print_err("fail to allocate frambuffer (size: %dK))",
fbdev->fb_len / 1024);
@ -557,14 +560,14 @@ static int __devinit au1100fb_drv_probe(struct platform_device *dev)
fbdev->info.fbops = &au1100fb_ops;
fbdev->info.fix = au1100fb_fix;
if (!(fbdev->info.pseudo_palette = kzalloc(sizeof(u32) * 16, GFP_KERNEL))) {
fbdev->info.pseudo_palette =
devm_kzalloc(&dev->dev, sizeof(u32) * 16, GFP_KERNEL);
if (!fbdev->info.pseudo_palette)
return -ENOMEM;
}
if (fb_alloc_cmap(&fbdev->info.cmap, AU1100_LCD_NBR_PALETTE_ENTRIES, 0) < 0) {
print_err("Fail to allocate colormap (%d entries)",
AU1100_LCD_NBR_PALETTE_ENTRIES);
kfree(fbdev->info.pseudo_palette);
return -EFAULT;
}
@ -582,9 +585,6 @@ static int __devinit au1100fb_drv_probe(struct platform_device *dev)
return 0;
failed:
if (fbdev->regs) {
release_mem_region(fbdev->regs_phys, fbdev->regs_len);
}
if (fbdev->fb_mem) {
dma_free_noncoherent(&dev->dev, fbdev->fb_len, fbdev->fb_mem,
fbdev->fb_phys);
@ -592,10 +592,9 @@ failed:
if (fbdev->info.cmap.len != 0) {
fb_dealloc_cmap(&fbdev->info.cmap);
}
kfree(fbdev);
platform_set_drvdata(dev, NULL);
return 0;
return -ENODEV;
}
int au1100fb_drv_remove(struct platform_device *dev)
@ -615,14 +614,7 @@ int au1100fb_drv_remove(struct platform_device *dev)
/* Clean up all probe data */
unregister_framebuffer(&fbdev->info);
release_mem_region(fbdev->regs_phys, fbdev->regs_len);
dma_free_coherent(&dev->dev, PAGE_ALIGN(fbdev->fb_len), fbdev->fb_mem,
fbdev->fb_phys);
fb_dealloc_cmap(&fbdev->info.cmap);
kfree(fbdev->info.pseudo_palette);
kfree((void*)fbdev);
return 0;
}

9
drivers/video/au1200fb.c
View File

@ -1724,7 +1724,7 @@ static int __devinit au1200fb_drv_probe(struct platform_device *dev)
/* Allocate the framebuffer to the maximum screen size */
fbdev->fb_len = (win->w[plane].xres * win->w[plane].yres * bpp) / 8;
fbdev->fb_mem = dma_alloc_noncoherent(&dev->dev,
fbdev->fb_mem = dmam_alloc_noncoherent(&dev->dev, &dev->dev,
PAGE_ALIGN(fbdev->fb_len),
&fbdev->fb_phys, GFP_KERNEL);
if (!fbdev->fb_mem) {
@ -1788,9 +1788,6 @@ static int __devinit au1200fb_drv_probe(struct platform_device *dev)
failed:
/* NOTE: This only does the current plane/window that failed; others are still active */
if (fbdev->fb_mem)
dma_free_noncoherent(&dev->dev, PAGE_ALIGN(fbdev->fb_len),
fbdev->fb_mem, fbdev->fb_phys);
if (fbi) {
if (fbi->cmap.len != 0)
fb_dealloc_cmap(&fbi->cmap);
@ -1817,10 +1814,6 @@ static int __devexit au1200fb_drv_remove(struct platform_device *dev)
/* Clean up all probe data */
unregister_framebuffer(fbi);
if (fbdev->fb_mem)
dma_free_noncoherent(&dev->dev,
PAGE_ALIGN(fbdev->fb_len),
fbdev->fb_mem, fbdev->fb_phys);
if (fbi->cmap.len != 0)
fb_dealloc_cmap(&fbi->cmap);
kfree(fbi->pseudo_palette);

12
drivers/video/bf537-lq035.c
View File

@ -383,23 +383,19 @@ static int __devinit request_ports(void)
}
#if (defined(UD) && defined(LBR))
if (gpio_request(UD, KBUILD_MODNAME)) {
if (gpio_request_one(UD, GPIOF_OUT_INIT_LOW, KBUILD_MODNAME)) {
pr_err("requesting GPIO %d failed\n", UD);
return -EBUSY;
}
if (gpio_request(LBR, KBUILD_MODNAME)) {
if (gpio_request_one(LBR, GPIOF_OUT_INIT_HIGH, KBUILD_MODNAME)) {
pr_err("requesting GPIO %d failed\n", LBR);
gpio_free(UD);
return -EBUSY;
}
gpio_direction_output(UD, 0);
gpio_direction_output(LBR, 1);
#endif
if (gpio_request(MOD, KBUILD_MODNAME)) {
if (gpio_request_one(MOD, GPIOF_OUT_INIT_HIGH, KBUILD_MODNAME)) {
pr_err("requesting GPIO %d failed\n", MOD);
#if (defined(UD) && defined(LBR))
gpio_free(LBR);
@ -408,8 +404,6 @@ static int __devinit request_ports(void)
return -EBUSY;
}
gpio_direction_output(MOD, 1);
SSYNC();
return 0;
}

4
drivers/video/bf54x-lq043fb.c
View File

@ -240,7 +240,7 @@ static int request_ports(struct bfin_bf54xfb_info *fbi)
u16 eppi_req_18[] = EPPI0_18;
u16 disp = fbi->mach_info->disp;
if (gpio_request(disp, DRIVER_NAME)) {
if (gpio_request_one(disp, GPIOF_OUT_INIT_HIGH, DRIVER_NAME)) {
printk(KERN_ERR "Requesting GPIO %d failed\n", disp);
return -EFAULT;
}
@ -263,8 +263,6 @@ static int request_ports(struct bfin_bf54xfb_info *fbi)
}
}
gpio_direction_output(disp, 1);
return 0;
}

8
drivers/video/bfin-lq035q1-fb.c
View File

@ -365,10 +365,10 @@ static int __devinit bfin_lq035q1_request_ports(struct platform_device *pdev,
* Drive PPI_FS3 Low
*/
if (ANOMALY_05000400) {
int ret = gpio_request(P_IDENT(P_PPI0_FS3), "PPI_FS3");
int ret = gpio_request_one(P_IDENT(P_PPI0_FS3),
GPIOF_OUT_INIT_LOW, "PPI_FS3");
if (ret)
return ret;
gpio_direction_output(P_IDENT(P_PPI0_FS3), 0);
}
if (ppi16)
@ -716,14 +716,14 @@ static int __devinit bfin_lq035q1_probe(struct platform_device *pdev)
}
if (info->disp_info->use_bl) {
ret = gpio_request(info->disp_info->gpio_bl, "LQ035 Backlight");
ret = gpio_request_one(info->disp_info->gpio_bl,
GPIOF_OUT_INIT_LOW, "LQ035 Backlight");
if (ret) {
dev_err(&pdev->dev, "failed to request GPIO %d\n",
info->disp_info->gpio_bl);
goto out9;
}
gpio_direction_output(info->disp_info->gpio_bl, 0);
}
ret = register_framebuffer(fbinfo);

7
drivers/video/bfin_adv7393fb.c
View File

@ -36,9 +36,7 @@
#include <linux/dma-mapping.h>
#include <linux/proc_fs.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/i2c-dev.h>
#include "bfin_adv7393fb.h"
@ -411,12 +409,13 @@ static int __devinit bfin_adv7393_fb_probe(struct i2c_client *client,
/* Workaround "PPI Does Not Start Properly In Specific Mode" */
if (ANOMALY_05000400) {
if (gpio_request(P_IDENT(P_PPI0_FS3), "PPI0_FS3")) {
ret = gpio_request_one(P_IDENT(P_PPI0_FS3), GPIOF_OUT_INIT_LOW,
"PPI0_FS3")
if (ret) {
dev_err(&client->dev, "PPI0_FS3 GPIO request failed\n");
ret = -EBUSY;
goto out_8;
}
gpio_direction_output(P_IDENT(P_PPI0_FS3), 0);
}
if (peripheral_request_list(ppi_pins, DRIVER_NAME)) {

79
drivers/video/da8xx-fb.c
View File

@ -32,6 +32,7 @@
#include <linux/console.h>
#include <linux/slab.h>
#include <video/da8xx-fb.h>
#include <asm/div64.h>
#define DRIVER_NAME "da8xx_lcdc"
@ -161,6 +162,7 @@ struct da8xx_fb_par {
int vsync_timeout;
#ifdef CONFIG_CPU_FREQ
struct notifier_block freq_transition;
unsigned int lcd_fck_rate;
#endif
void (*panel_power_ctrl)(int);
};
@ -174,7 +176,6 @@ static struct fb_var_screeninfo da8xx_fb_var __devinitdata = {
.activate = 0,
.height = -1,
.width = -1,
.pixclock = 46666, /* 46us - AUO display */
.accel_flags = 0,
.left_margin = LEFT_MARGIN,
.right_margin = RIGHT_MARGIN,
@ -238,6 +239,20 @@ static struct da8xx_panel known_lcd_panels[] = {
.pxl_clk = 7833600,
.invert_pxl_clk = 0,
},
[2] = {
/* Hitachi SP10Q010 */
.name = "SP10Q010",
.width = 320,
.height = 240,
.hfp = 10,
.hbp = 10,
.hsw = 10,
.vfp = 10,
.vbp = 10,
.vsw = 10,
.pxl_clk = 7833600,
.invert_pxl_clk = 0,
},
};
/* Enable the Raster Engine of the LCD Controller */
@ -546,7 +561,26 @@ static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
return 1;
if (info->var.bits_per_pixel == 8) {
if (info->var.bits_per_pixel == 4) {
if (regno > 15)
return 1;
if (info->var.grayscale) {
pal = regno;
} else {
red >>= 4;
green >>= 8;
blue >>= 12;
pal = (red & 0x0f00);
pal |= (green & 0x00f0);
pal |= (blue & 0x000f);
}
if (regno == 0)
pal |= 0x2000;
palette[regno] = pal;
} else if (info->var.bits_per_pixel == 8) {
red >>= 4;
green >>= 8;
blue >>= 12;
@ -801,6 +835,7 @@ static int fb_check_var(struct fb_var_screeninfo *var,
var->blue.length = 8;
var->transp.offset = 0;
var->transp.length = 0;
var->nonstd = 0;
break;
case 4:
var->red.offset = 0;
@ -811,6 +846,7 @@ static int fb_check_var(struct fb_var_screeninfo *var,
var->blue.length = 4;
var->transp.offset = 0;
var->transp.length = 0;
var->nonstd = FB_NONSTD_REV_PIX_IN_B;
break;
case 16: /* RGB 565 */
var->red.offset = 11;
@ -821,6 +857,7 @@ static int fb_check_var(struct fb_var_screeninfo *var,
var->blue.length = 5;
var->transp.offset = 0;
var->transp.length = 0;
var->nonstd = 0;
break;
default:
err = -EINVAL;
@ -840,11 +877,13 @@ static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,
struct da8xx_fb_par *par;
par = container_of(nb, struct da8xx_fb_par, freq_transition);
if (val == CPUFREQ_PRECHANGE) {
lcd_disable_raster();
} else if (val == CPUFREQ_POSTCHANGE) {
lcd_calc_clk_divider(par);
lcd_enable_raster();
if (val == CPUFREQ_POSTCHANGE) {
if (par->lcd_fck_rate != clk_get_rate(par->lcdc_clk)) {
par->lcd_fck_rate = clk_get_rate(par->lcdc_clk);
lcd_disable_raster();
lcd_calc_clk_divider(par);
lcd_enable_raster();
}
}
return 0;
@ -1048,6 +1087,22 @@ static struct fb_ops da8xx_fb_ops = {
.fb_blank = cfb_blank,
};
/* Calculate and return pixel clock period in pico seconds */
static unsigned int da8xxfb_pixel_clk_period(struct da8xx_fb_par *par)
{
unsigned int lcd_clk, div;
unsigned int configured_pix_clk;
unsigned long long pix_clk_period_picosec = 1000000000000ULL;
lcd_clk = clk_get_rate(par->lcdc_clk);
div = lcd_clk / par->pxl_clk;
configured_pix_clk = (lcd_clk / div);
do_div(pix_clk_period_picosec, configured_pix_clk);
return pix_clk_period_picosec;
}
static int __devinit fb_probe(struct platform_device *device)
{
struct da8xx_lcdc_platform_data *fb_pdata =
@ -1137,6 +1192,9 @@ static int __devinit fb_probe(struct platform_device *device)
par = da8xx_fb_info->par;
par->lcdc_clk = fb_clk;
#ifdef CONFIG_CPU_FREQ
par->lcd_fck_rate = clk_get_rate(fb_clk);
#endif
par->pxl_clk = lcdc_info->pxl_clk;
if (fb_pdata->panel_power_ctrl) {
par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
@ -1209,6 +1267,11 @@ static int __devinit fb_probe(struct platform_device *device)
da8xx_fb_var.hsync_len = lcdc_info->hsw;
da8xx_fb_var.vsync_len = lcdc_info->vsw;
da8xx_fb_var.right_margin = lcdc_info->hfp;
da8xx_fb_var.left_margin = lcdc_info->hbp;
da8xx_fb_var.lower_margin = lcdc_info->vfp;
da8xx_fb_var.upper_margin = lcdc_info->vbp;
da8xx_fb_var.pixclock = da8xxfb_pixel_clk_period(par);
/* Initialize fbinfo */
da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
@ -1264,8 +1327,8 @@ static int __devinit fb_probe(struct platform_device *device)
irq_freq:
#ifdef CONFIG_CPU_FREQ
lcd_da8xx_cpufreq_deregister(par);
#endif
err_cpu_freq:
#endif
unregister_framebuffer(da8xx_fb_info);
err_dealloc_cmap:

37
drivers/video/exynos/Kconfig Normal file
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@ -0,0 +1,37 @@
#
# Exynos Video configuration
#
menuconfig EXYNOS_VIDEO
bool "Exynos Video driver support"
help
This enables support for EXYNOS Video device.
if EXYNOS_VIDEO
#
# MIPI DSI driver
#
config EXYNOS_MIPI_DSI
bool "EXYNOS MIPI DSI driver support."
depends on ARCH_S5PV210 || ARCH_EXYNOS
help
This enables support for MIPI-DSI device.
config EXYNOS_LCD_S6E8AX0
bool "S6E8AX0 MIPI AMOLED LCD Driver"
depends on (EXYNOS_MIPI_DSI && BACKLIGHT_CLASS_DEVICE && LCD_CLASS_DEVICE)
default n
help
If you have an S6E8AX0 MIPI AMOLED LCD Panel, say Y to enable its
LCD control driver.
config EXYNOS_DP
bool "EXYNOS DP driver support"
depends on ARCH_EXYNOS
default n
help
This enables support for DP device.
endif # EXYNOS_VIDEO

8
drivers/video/exynos/Makefile Normal file
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@ -0,0 +1,8 @@
#
# Makefile for the exynos video drivers.
#
obj-$(CONFIG_EXYNOS_MIPI_DSI) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \
exynos_mipi_dsi_lowlevel.o
obj-$(CONFIG_EXYNOS_LCD_S6E8AX0) += s6e8ax0.o
obj-$(CONFIG_EXYNOS_DP) += exynos_dp_core.o exynos_dp_reg.o

1058
drivers/video/exynos/exynos_dp_core.c Normal file
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File diff suppressed because it is too large Load Diff

206
drivers/video/exynos/exynos_dp_core.h Normal file
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@ -0,0 +1,206 @@
/*
* Header file for Samsung DP (Display Port) interface driver.
*
* Copyright (C) 2012 Samsung Electronics Co., Ltd.
* Author: Jingoo Han <jg1.han@samsung.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef _EXYNOS_DP_CORE_H
#define _EXYNOS_DP_CORE_H
struct link_train {
int eq_loop;
int cr_loop[4];
u8 link_rate;
u8 lane_count;
u8 training_lane[4];
enum link_training_state lt_state;
};
struct exynos_dp_device {
struct device *dev;
struct resource *res;
struct clk *clock;
unsigned int irq;
void __iomem *reg_base;
struct video_info *video_info;
struct link_train link_train;
};
/* exynos_dp_reg.c */
void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable);
void exynos_dp_stop_video(struct exynos_dp_device *dp);
void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable);
void exynos_dp_init_interrupt(struct exynos_dp_device *dp);
void exynos_dp_reset(struct exynos_dp_device *dp);
void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
u32 exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
enum analog_power_block block,
bool enable);
void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
void exynos_dp_init_hpd(struct exynos_dp_device *dp);
void exynos_dp_reset_aux(struct exynos_dp_device *dp);
void exynos_dp_init_aux(struct exynos_dp_device *dp);
int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
unsigned int reg_addr,
unsigned char data);
int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
unsigned int reg_addr,
unsigned char *data);
int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
unsigned int reg_addr,
unsigned int count,
unsigned char data[]);
int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
unsigned int reg_addr,
unsigned int count,
unsigned char data[]);
int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
unsigned int device_addr,
unsigned int reg_addr);
int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
unsigned int device_addr,
unsigned int reg_addr,
unsigned int *data);
int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
unsigned int device_addr,
unsigned int reg_addr,
unsigned int count,
unsigned char edid[]);
void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
enum pattern_set pattern);
void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
u32 training_lane);
void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
u32 training_lane);
void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
u32 training_lane);
void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
u32 training_lane);
u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
void exynos_dp_reset_macro(struct exynos_dp_device *dp);
int exynos_dp_init_video(struct exynos_dp_device *dp);
void exynos_dp_set_video_color_format(struct exynos_dp_device *dp,
u32 color_depth,
u32 color_space,
u32 dynamic_range,
u32 ycbcr_coeff);
int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
enum clock_recovery_m_value_type type,
u32 m_value,
u32 n_value);
void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
void exynos_dp_start_video(struct exynos_dp_device *dp);
int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp);
void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp,
struct video_info *video_info);
void exynos_dp_enable_scrambling(struct exynos_dp_device *dp);
void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
/* I2C EDID Chip ID, Slave Address */
#define I2C_EDID_DEVICE_ADDR 0x50
#define I2C_E_EDID_DEVICE_ADDR 0x30
#define EDID_BLOCK_LENGTH 0x80
#define EDID_HEADER_PATTERN 0x00
#define EDID_EXTENSION_FLAG 0x7e
#define EDID_CHECKSUM 0x7f
/* Definition for DPCD Register */
#define DPCD_ADDR_DPCD_REV 0x0000
#define DPCD_ADDR_MAX_LINK_RATE 0x0001
#define DPCD_ADDR_MAX_LANE_COUNT 0x0002
#define DPCD_ADDR_LINK_BW_SET 0x0100
#define DPCD_ADDR_LANE_COUNT_SET 0x0101
#define DPCD_ADDR_TRAINING_PATTERN_SET 0x0102
#define DPCD_ADDR_TRAINING_LANE0_SET 0x0103
#define DPCD_ADDR_LANE0_1_STATUS 0x0202
#define DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED 0x0204
#define DPCD_ADDR_ADJUST_REQUEST_LANE0_1 0x0206
#define DPCD_ADDR_ADJUST_REQUEST_LANE2_3 0x0207
#define DPCD_ADDR_TEST_REQUEST 0x0218
#define DPCD_ADDR_TEST_RESPONSE 0x0260
#define DPCD_ADDR_TEST_EDID_CHECKSUM 0x0261
#define DPCD_ADDR_SINK_POWER_STATE 0x0600
/* DPCD_ADDR_MAX_LANE_COUNT */
#define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
#define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
/* DPCD_ADDR_LANE_COUNT_SET */
#define DPCD_ENHANCED_FRAME_EN (0x1 << 7)
#define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
/* DPCD_ADDR_TRAINING_PATTERN_SET */
#define DPCD_SCRAMBLING_DISABLED (0x1 << 5)
#define DPCD_SCRAMBLING_ENABLED (0x0 << 5)
#define DPCD_TRAINING_PATTERN_2 (0x2 << 0)
#define DPCD_TRAINING_PATTERN_1 (0x1 << 0)
#define DPCD_TRAINING_PATTERN_DISABLED (0x0 << 0)
/* DPCD_ADDR_TRAINING_LANE0_SET */
#define DPCD_MAX_PRE_EMPHASIS_REACHED (0x1 << 5)
#define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
#define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
#define DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 (0x0 << 3)
#define DPCD_MAX_SWING_REACHED (0x1 << 2)
#define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
#define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
#define DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0 (0x0 << 0)
/* DPCD_ADDR_LANE0_1_STATUS */
#define DPCD_LANE_SYMBOL_LOCKED (0x1 << 2)
#define DPCD_LANE_CHANNEL_EQ_DONE (0x1 << 1)
#define DPCD_LANE_CR_DONE (0x1 << 0)
#define DPCD_CHANNEL_EQ_BITS (DPCD_LANE_CR_DONE| \
DPCD_LANE_CHANNEL_EQ_DONE|\
DPCD_LANE_SYMBOL_LOCKED)
/* DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED */
#define DPCD_LINK_STATUS_UPDATED (0x1 << 7)
#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (0x1 << 6)
#define DPCD_INTERLANE_ALIGN_DONE (0x1 << 0)
/* DPCD_ADDR_TEST_REQUEST */
#define DPCD_TEST_EDID_READ (0x1 << 2)
/* DPCD_ADDR_TEST_RESPONSE */
#define DPCD_TEST_EDID_CHECKSUM_WRITE (0x1 << 2)
/* DPCD_ADDR_SINK_POWER_STATE */
#define DPCD_SET_POWER_STATE_D0 (0x1 << 0)
#define DPCD_SET_POWER_STATE_D4 (0x2 << 0)
#endif /* _EXYNOS_DP_CORE_H */

1173
drivers/video/exynos/exynos_dp_reg.c Normal file
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335
drivers/video/exynos/exynos_dp_reg.h Normal file
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@ -0,0 +1,335 @@
/*
* Register definition file for Samsung DP driver
*
* Copyright (C) 2012 Samsung Electronics Co., Ltd.
* Author: Jingoo Han <jg1.han@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _EXYNOS_DP_REG_H
#define _EXYNOS_DP_REG_H
#define EXYNOS_DP_TX_SW_RESET 0x14
#define EXYNOS_DP_FUNC_EN_1 0x18
#define EXYNOS_DP_FUNC_EN_2 0x1C
#define EXYNOS_DP_VIDEO_CTL_1 0x20
#define EXYNOS_DP_VIDEO_CTL_2 0x24
#define EXYNOS_DP_VIDEO_CTL_3 0x28
#define EXYNOS_DP_VIDEO_CTL_8 0x3C
#define EXYNOS_DP_VIDEO_CTL_10 0x44
#define EXYNOS_DP_LANE_MAP 0x35C
#define EXYNOS_DP_AUX_HW_RETRY_CTL 0x390
#define EXYNOS_DP_COMMON_INT_STA_1 0x3C4
#define EXYNOS_DP_COMMON_INT_STA_2 0x3C8
#define EXYNOS_DP_COMMON_INT_STA_3 0x3CC
#define EXYNOS_DP_COMMON_INT_STA_4 0x3D0
#define EXYNOS_DP_INT_STA 0x3DC
#define EXYNOS_DP_COMMON_INT_MASK_1 0x3E0
#define EXYNOS_DP_COMMON_INT_MASK_2 0x3E4
#define EXYNOS_DP_COMMON_INT_MASK_3 0x3E8
#define EXYNOS_DP_COMMON_INT_MASK_4 0x3EC
#define EXYNOS_DP_INT_STA_MASK 0x3F8
#define EXYNOS_DP_INT_CTL 0x3FC
#define EXYNOS_DP_SYS_CTL_1 0x600
#define EXYNOS_DP_SYS_CTL_2 0x604
#define EXYNOS_DP_SYS_CTL_3 0x608
#define EXYNOS_DP_SYS_CTL_4 0x60C
#define EXYNOS_DP_PKT_SEND_CTL 0x640
#define EXYNOS_DP_HDCP_CTL 0x648
#define EXYNOS_DP_LINK_BW_SET 0x680
#define EXYNOS_DP_LANE_COUNT_SET 0x684
#define EXYNOS_DP_TRAINING_PTN_SET 0x688
#define EXYNOS_DP_LN0_LINK_TRAINING_CTL 0x68C
#define EXYNOS_DP_LN1_LINK_TRAINING_CTL 0x690
#define EXYNOS_DP_LN2_LINK_TRAINING_CTL 0x694
#define EXYNOS_DP_LN3_LINK_TRAINING_CTL 0x698
#define EXYNOS_DP_DEBUG_CTL 0x6C0
#define EXYNOS_DP_HPD_DEGLITCH_L 0x6C4
#define EXYNOS_DP_HPD_DEGLITCH_H 0x6C8
#define EXYNOS_DP_LINK_DEBUG_CTL 0x6E0
#define EXYNOS_DP_M_VID_0 0x700
#define EXYNOS_DP_M_VID_1 0x704
#define EXYNOS_DP_M_VID_2 0x708
#define EXYNOS_DP_N_VID_0 0x70C
#define EXYNOS_DP_N_VID_1 0x710
#define EXYNOS_DP_N_VID_2 0x714
#define EXYNOS_DP_PLL_CTL 0x71C
#define EXYNOS_DP_PHY_PD 0x720
#define EXYNOS_DP_PHY_TEST 0x724
#define EXYNOS_DP_VIDEO_FIFO_THRD 0x730
#define EXYNOS_DP_AUDIO_MARGIN 0x73C
#define EXYNOS_DP_M_VID_GEN_FILTER_TH 0x764
#define EXYNOS_DP_M_AUD_GEN_FILTER_TH 0x778
#define EXYNOS_DP_AUX_CH_STA 0x780
#define EXYNOS_DP_AUX_CH_DEFER_CTL 0x788
#define EXYNOS_DP_AUX_RX_COMM 0x78C
#define EXYNOS_DP_BUFFER_DATA_CTL 0x790
#define EXYNOS_DP_AUX_CH_CTL_1 0x794
#define EXYNOS_DP_AUX_ADDR_7_0 0x798
#define EXYNOS_DP_AUX_ADDR_15_8 0x79C
#define EXYNOS_DP_AUX_ADDR_19_16 0x7A0
#define EXYNOS_DP_AUX_CH_CTL_2 0x7A4
#define EXYNOS_DP_BUF_DATA_0 0x7C0
#define EXYNOS_DP_SOC_GENERAL_CTL 0x800
/* EXYNOS_DP_TX_SW_RESET */
#define RESET_DP_TX (0x1 << 0)
/* EXYNOS_DP_FUNC_EN_1 */
#define MASTER_VID_FUNC_EN_N (0x1 << 7)
#define SLAVE_VID_FUNC_EN_N (0x1 << 5)
#define AUD_FIFO_FUNC_EN_N (0x1 << 4)
#define AUD_FUNC_EN_N (0x1 << 3)
#define HDCP_FUNC_EN_N (0x1 << 2)
#define CRC_FUNC_EN_N (0x1 << 1)
#define SW_FUNC_EN_N (0x1 << 0)
/* EXYNOS_DP_FUNC_EN_2 */
#define SSC_FUNC_EN_N (0x1 << 7)
#define AUX_FUNC_EN_N (0x1 << 2)
#define SERDES_FIFO_FUNC_EN_N (0x1 << 1)
#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0)
/* EXYNOS_DP_VIDEO_CTL_1 */
#define VIDEO_EN (0x1 << 7)
#define HDCP_VIDEO_MUTE (0x1 << 6)
/* EXYNOS_DP_VIDEO_CTL_1 */
#define IN_D_RANGE_MASK (0x1 << 7)
#define IN_D_RANGE_SHIFT (7)
#define IN_D_RANGE_CEA (0x1 << 7)
#define IN_D_RANGE_VESA (0x0 << 7)
#define IN_BPC_MASK (0x7 << 4)
#define IN_BPC_SHIFT (4)
#define IN_BPC_12_BITS (0x3 << 4)
#define IN_BPC_10_BITS (0x2 << 4)
#define IN_BPC_8_BITS (0x1 << 4)
#define IN_BPC_6_BITS (0x0 << 4)
#define IN_COLOR_F_MASK (0x3 << 0)
#define IN_COLOR_F_SHIFT (0)
#define IN_COLOR_F_YCBCR444 (0x2 << 0)
#define IN_COLOR_F_YCBCR422 (0x1 << 0)
#define IN_COLOR_F_RGB (0x0 << 0)
/* EXYNOS_DP_VIDEO_CTL_3 */
#define IN_YC_COEFFI_MASK (0x1 << 7)
#define IN_YC_COEFFI_SHIFT (7)
#define IN_YC_COEFFI_ITU709 (0x1 << 7)
#define IN_YC_COEFFI_ITU601 (0x0 << 7)
#define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4)
#define VID_CHK_UPDATE_TYPE_SHIFT (4)
#define VID_CHK_UPDATE_TYPE_1 (0x1 << 4)
#define VID_CHK_UPDATE_TYPE_0 (0x0 << 4)
/* EXYNOS_DP_VIDEO_CTL_8 */
#define VID_HRES_TH(x) (((x) & 0xf) << 4)
#define VID_VRES_TH(x) (((x) & 0xf) << 0)
/* EXYNOS_DP_VIDEO_CTL_10 */
#define FORMAT_SEL (0x1 << 4)
#define INTERACE_SCAN_CFG (0x1 << 2)
#define VSYNC_POLARITY_CFG (0x1 << 1)
#define HSYNC_POLARITY_CFG (0x1 << 0)
/* EXYNOS_DP_LANE_MAP */
#define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6)
#define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6)
#define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6)
#define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6)
#define LANE2_MAP_LOGIC_LANE_0 (0x0 << 4)
#define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4)
#define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4)
#define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4)
#define LANE1_MAP_LOGIC_LANE_0 (0x0 << 2)
#define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2)
#define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2)
#define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2)
#define LANE0_MAP_LOGIC_LANE_0 (0x0 << 0)
#define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0)
#define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0)
#define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0)
/* EXYNOS_DP_AUX_HW_RETRY_CTL */
#define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8)
#define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3)
#define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3)
#define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3)
#define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3)
#define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3)
#define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0)
/* EXYNOS_DP_COMMON_INT_STA_1 */
#define VSYNC_DET (0x1 << 7)
#define PLL_LOCK_CHG (0x1 << 6)
#define SPDIF_ERR (0x1 << 5)
#define SPDIF_UNSTBL (0x1 << 4)
#define VID_FORMAT_CHG (0x1 << 3)
#define AUD_CLK_CHG (0x1 << 2)
#define VID_CLK_CHG (0x1 << 1)
#define SW_INT (0x1 << 0)
/* EXYNOS_DP_COMMON_INT_STA_2 */
#define ENC_EN_CHG (0x1 << 6)
#define HW_BKSV_RDY (0x1 << 3)
#define HW_SHA_DONE (0x1 << 2)
#define HW_AUTH_STATE_CHG (0x1 << 1)
#define HW_AUTH_DONE (0x1 << 0)
/* EXYNOS_DP_COMMON_INT_STA_3 */
#define AFIFO_UNDER (0x1 << 7)
#define AFIFO_OVER (0x1 << 6)
#define R0_CHK_FLAG (0x1 << 5)
/* EXYNOS_DP_COMMON_INT_STA_4 */
#define PSR_ACTIVE (0x1 << 7)
#define PSR_INACTIVE (0x1 << 6)
#define SPDIF_BI_PHASE_ERR (0x1 << 5)
#define HOTPLUG_CHG (0x1 << 2)
#define HPD_LOST (0x1 << 1)
#define PLUG (0x1 << 0)
/* EXYNOS_DP_INT_STA */
#define INT_HPD (0x1 << 6)
#define HW_TRAINING_FINISH (0x1 << 5)
#define RPLY_RECEIV (0x1 << 1)
#define AUX_ERR (0x1 << 0)
/* EXYNOS_DP_INT_CTL */
#define SOFT_INT_CTRL (0x1 << 2)
#define INT_POL (0x1 << 0)
/* EXYNOS_DP_SYS_CTL_1 */
#define DET_STA (0x1 << 2)
#define FORCE_DET (0x1 << 1)
#define DET_CTRL (0x1 << 0)
/* EXYNOS_DP_SYS_CTL_2 */
#define CHA_CRI(x) (((x) & 0xf) << 4)
#define CHA_STA (0x1 << 2)
#define FORCE_CHA (0x1 << 1)
#define CHA_CTRL (0x1 << 0)
/* EXYNOS_DP_SYS_CTL_3 */
#define HPD_STATUS (0x1 << 6)
#define F_HPD (0x1 << 5)
#define HPD_CTRL (0x1 << 4)
#define HDCP_RDY (0x1 << 3)
#define STRM_VALID (0x1 << 2)
#define F_VALID (0x1 << 1)
#define VALID_CTRL (0x1 << 0)
/* EXYNOS_DP_SYS_CTL_4 */
#define FIX_M_AUD (0x1 << 4)
#define ENHANCED (0x1 << 3)
#define FIX_M_VID (0x1 << 2)
#define M_VID_UPDATE_CTRL (0x3 << 0)
/* EXYNOS_DP_TRAINING_PTN_SET */
#define SCRAMBLER_TYPE (0x1 << 9)
#define HW_LINK_TRAINING_PATTERN (0x1 << 8)
#define SCRAMBLING_DISABLE (0x1 << 5)
#define SCRAMBLING_ENABLE (0x0 << 5)
#define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2)
#define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2)
#define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2)
#define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2)
#define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0)
#define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0)
#define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0)
#define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0)
/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */
#define PRE_EMPHASIS_SET_SHIFT (3)
/* EXYNOS_DP_DEBUG_CTL */
#define PLL_LOCK (0x1 << 4)
#define F_PLL_LOCK (0x1 << 3)
#define PLL_LOCK_CTRL (0x1 << 2)
#define PN_INV (0x1 << 0)
/* EXYNOS_DP_PLL_CTL */
#define DP_PLL_PD (0x1 << 7)
#define DP_PLL_RESET (0x1 << 6)
#define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4)
#define DP_PLL_REF_BIT_1_1250V (0x5 << 0)
#define DP_PLL_REF_BIT_1_2500V (0x7 << 0)
/* EXYNOS_DP_PHY_PD */
#define DP_PHY_PD (0x1 << 5)
#define AUX_PD (0x1 << 4)
#define CH3_PD (0x1 << 3)
#define CH2_PD (0x1 << 2)
#define CH1_PD (0x1 << 1)
#define CH0_PD (0x1 << 0)
/* EXYNOS_DP_PHY_TEST */
#define MACRO_RST (0x1 << 5)
#define CH1_TEST (0x1 << 1)
#define CH0_TEST (0x1 << 0)
/* EXYNOS_DP_AUX_CH_STA */
#define AUX_BUSY (0x1 << 4)
#define AUX_STATUS_MASK (0xf << 0)
/* EXYNOS_DP_AUX_CH_DEFER_CTL */
#define DEFER_CTRL_EN (0x1 << 7)
#define DEFER_COUNT(x) (((x) & 0x7f) << 0)
/* EXYNOS_DP_AUX_RX_COMM */
#define AUX_RX_COMM_I2C_DEFER (0x2 << 2)
#define AUX_RX_COMM_AUX_DEFER (0x2 << 0)
/* EXYNOS_DP_BUFFER_DATA_CTL */
#define BUF_CLR (0x1 << 7)
#define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0)
/* EXYNOS_DP_AUX_CH_CTL_1 */
#define AUX_LENGTH(x) (((x - 1) & 0xf) << 4)
#define AUX_TX_COMM_MASK (0xf << 0)
#define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3)
#define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3)
#define AUX_TX_COMM_MOT (0x1 << 2)
#define AUX_TX_COMM_WRITE (0x0 << 0)
#define AUX_TX_COMM_READ (0x1 << 0)
/* EXYNOS_DP_AUX_ADDR_7_0 */
#define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff)
/* EXYNOS_DP_AUX_ADDR_15_8 */
#define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff)
/* EXYNOS_DP_AUX_ADDR_19_16 */
#define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f)
/* EXYNOS_DP_AUX_CH_CTL_2 */
#define ADDR_ONLY (0x1 << 1)
#define AUX_EN (0x1 << 0)
/* EXYNOS_DP_SOC_GENERAL_CTL */
#define AUDIO_MODE_SPDIF_MODE (0x1 << 8)
#define AUDIO_MODE_MASTER_MODE (0x0 << 8)
#define MASTER_VIDEO_INTERLACE_EN (0x1 << 4)
#define VIDEO_MASTER_CLK_SEL (0x1 << 2)
#define VIDEO_MASTER_MODE_EN (0x1 << 1)
#define VIDEO_MODE_MASK (0x1 << 0)
#define VIDEO_MODE_SLAVE_MODE (0x1 << 0)
#define VIDEO_MODE_MASTER_MODE (0x0 << 0)
#endif /* _EXYNOS_DP_REG_H */

600
drivers/video/exynos/exynos_mipi_dsi.c Normal file
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@ -0,0 +1,600 @@
/* linux/drivers/video/exynos/exynos_mipi_dsi.c
*
* Samsung SoC MIPI-DSIM driver.
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd
*
* InKi Dae, <inki.dae@samsung.com>
* Donghwa Lee, <dh09.lee@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/clk.h>
#include <linux/mutex.h>
#include <linux/wait.h>
#include <linux/fs.h>
#include <linux/mm.h>
#include <linux/fb.h>
#include <linux/ctype.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/memory.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/kthread.h>
#include <linux/notifier.h>
#include <linux/regulator/consumer.h>
#include <linux/pm_runtime.h>
#include <video/exynos_mipi_dsim.h>
#include <plat/fb.h>
#include "exynos_mipi_dsi_common.h"
#include "exynos_mipi_dsi_lowlevel.h"
struct mipi_dsim_ddi {
int bus_id;
struct list_head list;
struct mipi_dsim_lcd_device *dsim_lcd_dev;
struct mipi_dsim_lcd_driver *dsim_lcd_drv;
};
static LIST_HEAD(dsim_ddi_list);
static DEFINE_MUTEX(mipi_dsim_lock);
static struct mipi_dsim_platform_data *to_dsim_plat(struct platform_device
*pdev)
{
return pdev->dev.platform_data;
}
static struct regulator_bulk_data supplies[] = {
{ .supply = "vdd10", },
{ .supply = "vdd18", },
};
static int exynos_mipi_regulator_enable(struct mipi_dsim_device *dsim)
{
int ret;
mutex_lock(&dsim->lock);
ret = regulator_bulk_enable(ARRAY_SIZE(supplies), supplies);
mutex_unlock(&dsim->lock);
return ret;
}
static int exynos_mipi_regulator_disable(struct mipi_dsim_device *dsim)
{
int ret;
mutex_lock(&dsim->lock);
ret = regulator_bulk_disable(ARRAY_SIZE(supplies), supplies);
mutex_unlock(&dsim->lock);
return ret;
}
/* update all register settings to MIPI DSI controller. */
static void exynos_mipi_update_cfg(struct mipi_dsim_device *dsim)
{
/*
* data from Display controller(FIMD) is not transferred in video mode
* but in case of command mode, all settings is not updated to
* registers.
*/
exynos_mipi_dsi_stand_by(dsim, 0);
exynos_mipi_dsi_init_dsim(dsim);
exynos_mipi_dsi_init_link(dsim);
exynos_mipi_dsi_set_hs_enable(dsim);
/* set display timing. */
exynos_mipi_dsi_set_display_mode(dsim, dsim->dsim_config);
/*
* data from Display controller(FIMD) is transferred in video mode
* but in case of command mode, all settigs is updated to registers.
*/
exynos_mipi_dsi_stand_by(dsim, 1);
}
static int exynos_mipi_dsi_early_blank_mode(struct mipi_dsim_device *dsim,
int power)
{
struct mipi_dsim_lcd_driver *client_drv = dsim->dsim_lcd_drv;
struct mipi_dsim_lcd_device *client_dev = dsim->dsim_lcd_dev;
switch (power) {
case FB_BLANK_POWERDOWN:
if (dsim->suspended)
return 0;
if (client_drv && client_drv->suspend)
client_drv->suspend(client_dev);
clk_disable(dsim->clock);
exynos_mipi_regulator_disable(dsim);
dsim->suspended = true;
break;
default:
break;
}
return 0;
}
static int exynos_mipi_dsi_blank_mode(struct mipi_dsim_device *dsim, int power)
{
struct platform_device *pdev = to_platform_device(dsim->dev);
struct mipi_dsim_lcd_driver *client_drv = dsim->dsim_lcd_drv;
struct mipi_dsim_lcd_device *client_dev = dsim->dsim_lcd_dev;
switch (power) {
case FB_BLANK_UNBLANK:
if (!dsim->suspended)
return 0;
/* lcd panel power on. */
if (client_drv && client_drv->power_on)
client_drv->power_on(client_dev, 1);
exynos_mipi_regulator_disable(dsim);
/* enable MIPI-DSI PHY. */
if (dsim->pd->phy_enable)
dsim->pd->phy_enable(pdev, true);
clk_enable(dsim->clock);
exynos_mipi_update_cfg(dsim);
/* set lcd panel sequence commands. */
if (client_drv && client_drv->set_sequence)
client_drv->set_sequence(client_dev);
dsim->suspended = false;
break;
case FB_BLANK_NORMAL:
/* TODO. */
break;
default:
break;
}
return 0;
}
int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device *lcd_dev)
{
struct mipi_dsim_ddi *dsim_ddi;
if (!lcd_dev->name) {
pr_err("dsim_lcd_device name is NULL.\n");
return -EFAULT;
}
dsim_ddi = kzalloc(sizeof(struct mipi_dsim_ddi), GFP_KERNEL);
if (!dsim_ddi) {
pr_err("failed to allocate dsim_ddi object.\n");
return -ENOMEM;
}
dsim_ddi->dsim_lcd_dev = lcd_dev;
mutex_lock(&mipi_dsim_lock);
list_add_tail(&dsim_ddi->list, &dsim_ddi_list);
mutex_unlock(&mipi_dsim_lock);
return 0;
}
struct mipi_dsim_ddi *exynos_mipi_dsi_find_lcd_device(struct mipi_dsim_lcd_driver *lcd_drv)
{
struct mipi_dsim_ddi *dsim_ddi, *next;
struct mipi_dsim_lcd_device *lcd_dev;
mutex_lock(&mipi_dsim_lock);
list_for_each_entry_safe(dsim_ddi, next, &dsim_ddi_list, list) {
if (!dsim_ddi)
goto out;
lcd_dev = dsim_ddi->dsim_lcd_dev;
if (!lcd_dev)
continue;
if ((strcmp(lcd_drv->name, lcd_dev->name)) == 0) {
/**
* bus_id would be used to identify
* connected bus.
*/
dsim_ddi->bus_id = lcd_dev->bus_id;
mutex_unlock(&mipi_dsim_lock);
return dsim_ddi;
}
list_del(&dsim_ddi->list);
kfree(dsim_ddi);
}
out:
mutex_unlock(&mipi_dsim_lock);
return NULL;
}
int exynos_mipi_dsi_register_lcd_driver(struct mipi_dsim_lcd_driver *lcd_drv)
{
struct mipi_dsim_ddi *dsim_ddi;
if (!lcd_drv->name) {
pr_err("dsim_lcd_driver name is NULL.\n");
return -EFAULT;
}
dsim_ddi = exynos_mipi_dsi_find_lcd_device(lcd_drv);
if (!dsim_ddi) {
pr_err("mipi_dsim_ddi object not found.\n");
return -EFAULT;
}
dsim_ddi->dsim_lcd_drv = lcd_drv;
pr_info("registered panel driver(%s) to mipi-dsi driver.\n",
lcd_drv->name);
return 0;
}
struct mipi_dsim_ddi *exynos_mipi_dsi_bind_lcd_ddi(struct mipi_dsim_device *dsim,
const char *name)
{
struct mipi_dsim_ddi *dsim_ddi, *next;
struct mipi_dsim_lcd_driver *lcd_drv;
struct mipi_dsim_lcd_device *lcd_dev;
int ret;
mutex_lock(&dsim->lock);
list_for_each_entry_safe(dsim_ddi, next, &dsim_ddi_list, list) {
lcd_drv = dsim_ddi->dsim_lcd_drv;
lcd_dev = dsim_ddi->dsim_lcd_dev;
if (!lcd_drv || !lcd_dev ||
(dsim->id != dsim_ddi->bus_id))
continue;
dev_dbg(dsim->dev, "lcd_drv->id = %d, lcd_dev->id = %d\n",
lcd_drv->id, lcd_dev->id);
dev_dbg(dsim->dev, "lcd_dev->bus_id = %d, dsim->id = %d\n",
lcd_dev->bus_id, dsim->id);
if ((strcmp(lcd_drv->name, name) == 0)) {
lcd_dev->master = dsim;
lcd_dev->dev.parent = dsim->dev;
dev_set_name(&lcd_dev->dev, "%s", lcd_drv->name);
ret = device_register(&lcd_dev->dev);
if (ret < 0) {
dev_err(dsim->dev,
"can't register %s, status %d\n",
dev_name(&lcd_dev->dev), ret);
mutex_unlock(&dsim->lock);
return NULL;
}
dsim->dsim_lcd_dev = lcd_dev;
dsim->dsim_lcd_drv = lcd_drv;
mutex_unlock(&dsim->lock);
return dsim_ddi;
}
}
mutex_unlock(&dsim->lock);
return NULL;
}
/* define MIPI-DSI Master operations. */
static struct mipi_dsim_master_ops master_ops = {
.cmd_read = exynos_mipi_dsi_rd_data,
.cmd_write = exynos_mipi_dsi_wr_data,
.get_dsim_frame_done = exynos_mipi_dsi_get_frame_done_status,
.clear_dsim_frame_done = exynos_mipi_dsi_clear_frame_done,
.set_early_blank_mode = exynos_mipi_dsi_early_blank_mode,
.set_blank_mode = exynos_mipi_dsi_blank_mode,
};
static int exynos_mipi_dsi_probe(struct platform_device *pdev)
{
struct resource *res;
struct mipi_dsim_device *dsim;
struct mipi_dsim_config *dsim_config;
struct mipi_dsim_platform_data *dsim_pd;
struct mipi_dsim_ddi *dsim_ddi;
int ret = -EINVAL;
dsim = kzalloc(sizeof(struct mipi_dsim_device), GFP_KERNEL);
if (!dsim) {
dev_err(&pdev->dev, "failed to allocate dsim object.\n");
return -ENOMEM;
}
dsim->pd = to_dsim_plat(pdev);
dsim->dev = &pdev->dev;
dsim->id = pdev->id;
/* get mipi_dsim_platform_data. */
dsim_pd = (struct mipi_dsim_platform_data *)dsim->pd;
if (dsim_pd == NULL) {
dev_err(&pdev->dev, "failed to get platform data for dsim.\n");
goto err_clock_get;
}
/* get mipi_dsim_config. */
dsim_config = dsim_pd->dsim_config;
if (dsim_config == NULL) {
dev_err(&pdev->dev, "failed to get dsim config data.\n");
goto err_clock_get;
}
dsim->dsim_config = dsim_config;
dsim->master_ops = &master_ops;
mutex_init(&dsim->lock);
ret = regulator_bulk_get(&pdev->dev, ARRAY_SIZE(supplies), supplies);
if (ret) {
dev_err(&pdev->dev, "Failed to get regulators: %d\n", ret);
goto err_clock_get;
}
dsim->clock = clk_get(&pdev->dev, "dsim0");
if (IS_ERR(dsim->clock)) {
dev_err(&pdev->dev, "failed to get dsim clock source\n");
goto err_clock_get;
}
clk_enable(dsim->clock);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "failed to get io memory region\n");
goto err_platform_get;
}
dsim->res = request_mem_region(res->start, resource_size(res),
dev_name(&pdev->dev));
if (!dsim->res) {
dev_err(&pdev->dev, "failed to request io memory region\n");
ret = -ENOMEM;
goto err_mem_region;
}
dsim->reg_base = ioremap(res->start, resource_size(res));
if (!dsim->reg_base) {
dev_err(&pdev->dev, "failed to remap io region\n");
ret = -ENOMEM;
goto err_ioremap;
}
mutex_init(&dsim->lock);
/* bind lcd ddi matched with panel name. */
dsim_ddi = exynos_mipi_dsi_bind_lcd_ddi(dsim, dsim_pd->lcd_panel_name);
if (!dsim_ddi) {
dev_err(&pdev->dev, "mipi_dsim_ddi object not found.\n");
goto err_bind;
}
dsim->irq = platform_get_irq(pdev, 0);
if (dsim->irq < 0) {
dev_err(&pdev->dev, "failed to request dsim irq resource\n");
ret = -EINVAL;
goto err_platform_get_irq;
}
ret = request_irq(dsim->irq, exynos_mipi_dsi_interrupt_handler,
IRQF_SHARED, pdev->name, dsim);
if (ret != 0) {
dev_err(&pdev->dev, "failed to request dsim irq\n");
ret = -EINVAL;
goto err_bind;
}
init_completion(&dsim_wr_comp);
init_completion(&dsim_rd_comp);
/* enable interrupt */
exynos_mipi_dsi_init_interrupt(dsim);
/* initialize mipi-dsi client(lcd panel). */
if (dsim_ddi->dsim_lcd_drv && dsim_ddi->dsim_lcd_drv->probe)
dsim_ddi->dsim_lcd_drv->probe(dsim_ddi->dsim_lcd_dev);
/* in case that mipi got enabled at bootloader. */
if (dsim_pd->enabled)
goto out;
/* lcd panel power on. */
if (dsim_ddi->dsim_lcd_drv && dsim_ddi->dsim_lcd_drv->power_on)
dsim_ddi->dsim_lcd_drv->power_on(dsim_ddi->dsim_lcd_dev, 1);
exynos_mipi_regulator_enable(dsim);
/* enable MIPI-DSI PHY. */
if (dsim->pd->phy_enable)
dsim->pd->phy_enable(pdev, true);
exynos_mipi_update_cfg(dsim);
/* set lcd panel sequence commands. */
if (dsim_ddi->dsim_lcd_drv && dsim_ddi->dsim_lcd_drv->set_sequence)
dsim_ddi->dsim_lcd_drv->set_sequence(dsim_ddi->dsim_lcd_dev);
dsim->suspended = false;
out:
platform_set_drvdata(pdev, dsim);
dev_dbg(&pdev->dev, "mipi-dsi driver(%s mode) has been probed.\n",
(dsim_config->e_interface == DSIM_COMMAND) ?
"CPU" : "RGB");
return 0;
err_bind:
iounmap(dsim->reg_base);
err_ioremap:
release_mem_region(dsim->res->start, resource_size(dsim->res));
err_mem_region:
release_resource(dsim->res);
err_platform_get:
clk_disable(dsim->clock);
clk_put(dsim->clock);
err_clock_get:
kfree(dsim);
err_platform_get_irq:
return ret;
}
static int __devexit exynos_mipi_dsi_remove(struct platform_device *pdev)
{
struct mipi_dsim_device *dsim = platform_get_drvdata(pdev);
struct mipi_dsim_ddi *dsim_ddi, *next;
struct mipi_dsim_lcd_driver *dsim_lcd_drv;
iounmap(dsim->reg_base);
clk_disable(dsim->clock);
clk_put(dsim->clock);
release_resource(dsim->res);
release_mem_region(dsim->res->start, resource_size(dsim->res));
list_for_each_entry_safe(dsim_ddi, next, &dsim_ddi_list, list) {
if (dsim_ddi) {
if (dsim->id != dsim_ddi->bus_id)
continue;
dsim_lcd_drv = dsim_ddi->dsim_lcd_drv;
if (dsim_lcd_drv->remove)
dsim_lcd_drv->remove(dsim_ddi->dsim_lcd_dev);
kfree(dsim_ddi);
}
}
regulator_bulk_free(ARRAY_SIZE(supplies), supplies);
kfree(dsim);
return 0;
}
#ifdef CONFIG_PM
static int exynos_mipi_dsi_suspend(struct platform_device *pdev,
pm_message_t state)
{
struct mipi_dsim_device *dsim = platform_get_drvdata(pdev);
struct mipi_dsim_lcd_driver *client_drv = dsim->dsim_lcd_drv;
struct mipi_dsim_lcd_device *client_dev = dsim->dsim_lcd_dev;
disable_irq(dsim->irq);
if (dsim->suspended)
return 0;
if (client_drv && client_drv->suspend)
client_drv->suspend(client_dev);
/* enable MIPI-DSI PHY. */
if (dsim->pd->phy_enable)
dsim->pd->phy_enable(pdev, false);
clk_disable(dsim->clock);
exynos_mipi_regulator_disable(dsim);
dsim->suspended = true;
return 0;
}
static int exynos_mipi_dsi_resume(struct platform_device *pdev)
{
struct mipi_dsim_device *dsim = platform_get_drvdata(pdev);
struct mipi_dsim_lcd_driver *client_drv = dsim->dsim_lcd_drv;
struct mipi_dsim_lcd_device *client_dev = dsim->dsim_lcd_dev;
enable_irq(dsim->irq);
if (!dsim->suspended)
return 0;
/* lcd panel power on. */
if (client_drv && client_drv->power_on)
client_drv->power_on(client_dev, 1);
exynos_mipi_regulator_enable(dsim);
/* enable MIPI-DSI PHY. */
if (dsim->pd->phy_enable)
dsim->pd->phy_enable(pdev, true);
clk_enable(dsim->clock);
exynos_mipi_update_cfg(dsim);
/* set lcd panel sequence commands. */
if (client_drv && client_drv->set_sequence)
client_drv->set_sequence(client_dev);
dsim->suspended = false;
return 0;
}
#else
#define exynos_mipi_dsi_suspend NULL
#define exynos_mipi_dsi_resume NULL
#endif
static struct platform_driver exynos_mipi_dsi_driver = {
.probe = exynos_mipi_dsi_probe,
.remove = __devexit_p(exynos_mipi_dsi_remove),
.suspend = exynos_mipi_dsi_suspend,
.resume = exynos_mipi_dsi_resume,
.driver = {
.name = "exynos-mipi-dsim",
.owner = THIS_MODULE,
},
};
module_platform_driver(exynos_mipi_dsi_driver);
MODULE_AUTHOR("InKi Dae <inki.dae@samsung.com>");
MODULE_DESCRIPTION("Samusung SoC MIPI-DSI driver");
MODULE_LICENSE("GPL");

896
drivers/video/exynos/exynos_mipi_dsi_common.c Normal file
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/* linux/drivers/video/exynos/exynos_mipi_dsi_common.c
*
* Samsung SoC MIPI-DSI common driver.
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd
*
* InKi Dae, <inki.dae@samsung.com>
* Donghwa Lee, <dh09.lee@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/mutex.h>
#include <linux/wait.h>
#include <linux/fs.h>
#include <linux/mm.h>
#include <linux/fb.h>
#include <linux/ctype.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/memory.h>
#include <linux/delay.h>
#include <linux/kthread.h>
#include <video/mipi_display.h>
#include <video/exynos_mipi_dsim.h>
#include <mach/map.h>
#include "exynos_mipi_dsi_regs.h"
#include "exynos_mipi_dsi_lowlevel.h"
#include "exynos_mipi_dsi_common.h"
#define MIPI_FIFO_TIMEOUT msecs_to_jiffies(250)
#define MIPI_RX_FIFO_READ_DONE 0x30800002
#define MIPI_MAX_RX_FIFO 20
#define MHZ (1000 * 1000)
#define FIN_HZ (24 * MHZ)
#define DFIN_PLL_MIN_HZ (6 * MHZ)
#define DFIN_PLL_MAX_HZ (12 * MHZ)
#define DFVCO_MIN_HZ (500 * MHZ)
#define DFVCO_MAX_HZ (1000 * MHZ)
#define TRY_GET_FIFO_TIMEOUT (5000 * 2)
#define TRY_FIFO_CLEAR (10)
/* MIPI-DSIM status types. */
enum {
DSIM_STATE_INIT, /* should be initialized. */
DSIM_STATE_STOP, /* CPU and LCDC are LP mode. */
DSIM_STATE_HSCLKEN, /* HS clock was enabled. */
DSIM_STATE_ULPS
};
/* define DSI lane types. */
enum {
DSIM_LANE_CLOCK = (1 << 0),
DSIM_LANE_DATA0 = (1 << 1),
DSIM_LANE_DATA1 = (1 << 2),
DSIM_LANE_DATA2 = (1 << 3),
DSIM_LANE_DATA3 = (1 << 4)
};
static unsigned int dpll_table[15] = {
100, 120, 170, 220, 270,
320, 390, 450, 510, 560,
640, 690, 770, 870, 950
};
irqreturn_t exynos_mipi_dsi_interrupt_handler(int irq, void *dev_id)
{
unsigned int intsrc = 0;
unsigned int intmsk = 0;
struct mipi_dsim_device *dsim = NULL;
dsim = dev_id;
if (!dsim) {
dev_dbg(dsim->dev, KERN_ERR "%s:error: wrong parameter\n",
__func__);
return IRQ_HANDLED;
}
intsrc = exynos_mipi_dsi_read_interrupt(dsim);
intmsk = exynos_mipi_dsi_read_interrupt_mask(dsim);
intmsk = ~(intmsk) & intsrc;
switch (intmsk) {
case INTMSK_RX_DONE:
complete(&dsim_rd_comp);
dev_dbg(dsim->dev, "MIPI INTMSK_RX_DONE\n");
break;
case INTMSK_FIFO_EMPTY:
complete(&dsim_wr_comp);
dev_dbg(dsim->dev, "MIPI INTMSK_FIFO_EMPTY\n");
break;
default:
break;
}
exynos_mipi_dsi_clear_interrupt(dsim, intmsk);
return IRQ_HANDLED;
}
/*
* write long packet to mipi dsi slave
* @dsim: mipi dsim device structure.
* @data0: packet data to send.
* @data1: size of packet data
*/
static void exynos_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim,
const unsigned char *data0, unsigned int data_size)
{
unsigned int data_cnt = 0, payload = 0;
/* in case that data count is more then 4 */
for (data_cnt = 0; data_cnt < data_size; data_cnt += 4) {
/*
* after sending 4bytes per one time,
* send remainder data less then 4.
*/
if ((data_size - data_cnt) < 4) {
if ((data_size - data_cnt) == 3) {
payload = data0[data_cnt] |
data0[data_cnt + 1] << 8 |
data0[data_cnt + 2] << 16;
dev_dbg(dsim->dev, "count = 3 payload = %x, %x %x %x\n",
payload, data0[data_cnt],
data0[data_cnt + 1],
data0[data_cnt + 2]);
} else if ((data_size - data_cnt) == 2) {
payload = data0[data_cnt] |
data0[data_cnt + 1] << 8;
dev_dbg(dsim->dev,
"count = 2 payload = %x, %x %x\n", payload,
data0[data_cnt],
data0[data_cnt + 1]);
} else if ((data_size - data_cnt) == 1) {
payload = data0[data_cnt];
}
exynos_mipi_dsi_wr_tx_data(dsim, payload);
/* send 4bytes per one time. */
} else {
payload = data0[data_cnt] |
data0[data_cnt + 1] << 8 |
data0[data_cnt + 2] << 16 |
data0[data_cnt + 3] << 24;
dev_dbg(dsim->dev,
"count = 4 payload = %x, %x %x %x %x\n",
payload, *(u8 *)(data0 + data_cnt),
data0[data_cnt + 1],
data0[data_cnt + 2],
data0[data_cnt + 3]);
exynos_mipi_dsi_wr_tx_data(dsim, payload);
}
}
}
int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,
const unsigned char *data0, unsigned int data_size)
{
unsigned int check_rx_ack = 0;
if (dsim->state == DSIM_STATE_ULPS) {
dev_err(dsim->dev, "state is ULPS.\n");
return -EINVAL;
}
/* FIXME!!! why does it need this delay? */
msleep(20);
mutex_lock(&dsim->lock);
switch (data_id) {
/* short packet types of packet types for command. */
case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
case MIPI_DSI_DCS_SHORT_WRITE:
case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
if (check_rx_ack) {
/* process response func should be implemented */
mutex_unlock(&dsim->lock);
return 0;
} else {
mutex_unlock(&dsim->lock);
return -EINVAL;
}
/* general command */
case MIPI_DSI_COLOR_MODE_OFF:
case MIPI_DSI_COLOR_MODE_ON:
case MIPI_DSI_SHUTDOWN_PERIPHERAL:
case MIPI_DSI_TURN_ON_PERIPHERAL:
exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
if (check_rx_ack) {
/* process response func should be implemented. */
mutex_unlock(&dsim->lock);
return 0;
} else {
mutex_unlock(&dsim->lock);
return -EINVAL;
}
/* packet types for video data */
case MIPI_DSI_V_SYNC_START:
case MIPI_DSI_V_SYNC_END:
case MIPI_DSI_H_SYNC_START:
case MIPI_DSI_H_SYNC_END:
case MIPI_DSI_END_OF_TRANSMISSION:
mutex_unlock(&dsim->lock);
return 0;
/* long packet type and null packet */
case MIPI_DSI_NULL_PACKET:
case MIPI_DSI_BLANKING_PACKET:
mutex_unlock(&dsim->lock);
return 0;
case MIPI_DSI_GENERIC_LONG_WRITE:
case MIPI_DSI_DCS_LONG_WRITE:
{
unsigned int size, payload = 0;
INIT_COMPLETION(dsim_wr_comp);
size = data_size * 4;
/* if data count is less then 4, then send 3bytes data. */
if (data_size < 4) {
payload = data0[0] |
data0[1] << 8 |
data0[2] << 16;
exynos_mipi_dsi_wr_tx_data(dsim, payload);
dev_dbg(dsim->dev, "count = %d payload = %x,%x %x %x\n",
data_size, payload, data0[0],
data0[1], data0[2]);
/* in case that data count is more then 4 */
} else
exynos_mipi_dsi_long_data_wr(dsim, data0, data_size);
/* put data into header fifo */
exynos_mipi_dsi_wr_tx_header(dsim, data_id, data_size & 0xff,
(data_size & 0xff00) >> 8);
if (!wait_for_completion_interruptible_timeout(&dsim_wr_comp,
MIPI_FIFO_TIMEOUT)) {
dev_warn(dsim->dev, "command write timeout.\n");
mutex_unlock(&dsim->lock);
return -EAGAIN;
}
if (check_rx_ack) {
/* process response func should be implemented. */
mutex_unlock(&dsim->lock);
return 0;
} else {
mutex_unlock(&dsim->lock);
return -EINVAL;
}
}
/* packet typo for video data */
case MIPI_DSI_PACKED_PIXEL_STREAM_16:
case MIPI_DSI_PACKED_PIXEL_STREAM_18:
case MIPI_DSI_PIXEL_STREAM_3BYTE_18:
case MIPI_DSI_PACKED_PIXEL_STREAM_24:
if (check_rx_ack) {
/* process response func should be implemented. */
mutex_unlock(&dsim->lock);
return 0;
} else {
mutex_unlock(&dsim->lock);
return -EINVAL;
}
default:
dev_warn(dsim->dev,
"data id %x is not supported current DSI spec.\n",
data_id);
mutex_unlock(&dsim->lock);
return -EINVAL;
}
mutex_unlock(&dsim->lock);
return 0;
}
static unsigned int exynos_mipi_dsi_long_data_rd(struct mipi_dsim_device *dsim,
unsigned int req_size, unsigned int rx_data, u8 *rx_buf)
{
unsigned int rcv_pkt, i, j;
u16 rxsize;
/* for long packet */
rxsize = (u16)((rx_data & 0x00ffff00) >> 8);
dev_dbg(dsim->dev, "mipi dsi rx size : %d\n", rxsize);
if (rxsize != req_size) {
dev_dbg(dsim->dev,
"received size mismatch received: %d, requested: %d\n",
rxsize, req_size);
goto err;
}
for (i = 0; i < (rxsize >> 2); i++) {
rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);
dev_dbg(dsim->dev, "received pkt : %08x\n", rcv_pkt);
for (j = 0; j < 4; j++) {
rx_buf[(i * 4) + j] =
(u8)(rcv_pkt >> (j * 8)) & 0xff;
dev_dbg(dsim->dev, "received value : %02x\n",
(rcv_pkt >> (j * 8)) & 0xff);
}
}
if (rxsize % 4) {
rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);
dev_dbg(dsim->dev, "received pkt : %08x\n", rcv_pkt);
for (j = 0; j < (rxsize % 4); j++) {
rx_buf[(i * 4) + j] =
(u8)(rcv_pkt >> (j * 8)) & 0xff;
dev_dbg(dsim->dev, "received value : %02x\n",
(rcv_pkt >> (j * 8)) & 0xff);
}
}
return rxsize;
err:
return -EINVAL;
}
static unsigned int exynos_mipi_dsi_response_size(unsigned int req_size)
{
switch (req_size) {
case 1:
return MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE;
case 2:
return MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE;
default:
return MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE;
}
}
int exynos_mipi_dsi_rd_data(struct mipi_dsim_device *dsim, unsigned int data_id,
unsigned int data0, unsigned int req_size, u8 *rx_buf)
{
unsigned int rx_data, rcv_pkt, i;
u8 response = 0;
u16 rxsize;
if (dsim->state == DSIM_STATE_ULPS) {
dev_err(dsim->dev, "state is ULPS.\n");
return -EINVAL;
}
/* FIXME!!! */
msleep(20);
mutex_lock(&dsim->lock);
INIT_COMPLETION(dsim_rd_comp);
exynos_mipi_dsi_rd_tx_header(dsim,
MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, req_size);
response = exynos_mipi_dsi_response_size(req_size);
switch (data_id) {
case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
case MIPI_DSI_DCS_READ:
exynos_mipi_dsi_rd_tx_header(dsim,
data_id, data0);
/* process response func should be implemented. */
break;
default:
dev_warn(dsim->dev,
"data id %x is not supported current DSI spec.\n",
data_id);
return -EINVAL;
}
if (!wait_for_completion_interruptible_timeout(&dsim_rd_comp,
MIPI_FIFO_TIMEOUT)) {
pr_err("RX done interrupt timeout\n");
mutex_unlock(&dsim->lock);
return 0;
}
msleep(20);
rx_data = exynos_mipi_dsi_rd_rx_fifo(dsim);
if ((u8)(rx_data & 0xff) != response) {
printk(KERN_ERR
"mipi dsi wrong response rx_data : %x, response:%x\n",
rx_data, response);
goto clear_rx_fifo;
}
if (req_size <= 2) {
/* for short packet */
for (i = 0; i < req_size; i++)
rx_buf[i] = (rx_data >> (8 + (i * 8))) & 0xff;
rxsize = req_size;
} else {
/* for long packet */
rxsize = exynos_mipi_dsi_long_data_rd(dsim, req_size, rx_data,
rx_buf);
if (rxsize != req_size)
goto clear_rx_fifo;
}
rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);
msleep(20);
if (rcv_pkt != MIPI_RX_FIFO_READ_DONE) {
dev_info(dsim->dev,
"Can't found RX FIFO READ DONE FLAG : %x\n", rcv_pkt);
goto clear_rx_fifo;
}
mutex_unlock(&dsim->lock);
return rxsize;
clear_rx_fifo:
i = 0;
while (1) {
rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);
if ((rcv_pkt == MIPI_RX_FIFO_READ_DONE)
|| (i > MIPI_MAX_RX_FIFO))
break;
dev_dbg(dsim->dev,
"mipi dsi clear rx fifo : %08x\n", rcv_pkt);
i++;
}
dev_info(dsim->dev,
"mipi dsi rx done count : %d, rcv_pkt : %08x\n", i, rcv_pkt);
mutex_unlock(&dsim->lock);
return 0;
}
static int exynos_mipi_dsi_pll_on(struct mipi_dsim_device *dsim,
unsigned int enable)
{
int sw_timeout;
if (enable) {
sw_timeout = 1000;
exynos_mipi_dsi_enable_pll(dsim, 1);
while (1) {
sw_timeout--;
if (exynos_mipi_dsi_is_pll_stable(dsim))
return 0;
if (sw_timeout == 0)
return -EINVAL;
}
} else
exynos_mipi_dsi_enable_pll(dsim, 0);
return 0;
}
static unsigned long exynos_mipi_dsi_change_pll(struct mipi_dsim_device *dsim,
unsigned int pre_divider, unsigned int main_divider,
unsigned int scaler)
{
unsigned long dfin_pll, dfvco, dpll_out;
unsigned int i, freq_band = 0xf;
dfin_pll = (FIN_HZ / pre_divider);
/******************************************************
* Serial Clock(=ByteClk X 8) FreqBand[3:0] *
******************************************************
* ~ 99.99 MHz 0000
* 100 ~ 119.99 MHz 0001
* 120 ~ 159.99 MHz 0010
* 160 ~ 199.99 MHz 0011
* 200 ~ 239.99 MHz 0100
* 140 ~ 319.99 MHz 0101
* 320 ~ 389.99 MHz 0110
* 390 ~ 449.99 MHz 0111
* 450 ~ 509.99 MHz 1000
* 510 ~ 559.99 MHz 1001
* 560 ~ 639.99 MHz 1010
* 640 ~ 689.99 MHz 1011
* 690 ~ 769.99 MHz 1100
* 770 ~ 869.99 MHz 1101
* 870 ~ 949.99 MHz 1110
* 950 ~ 1000 MHz 1111
******************************************************/
if (dfin_pll < DFIN_PLL_MIN_HZ || dfin_pll > DFIN_PLL_MAX_HZ) {
dev_warn(dsim->dev, "fin_pll range should be 6MHz ~ 12MHz\n");
exynos_mipi_dsi_enable_afc(dsim, 0, 0);
} else {
if (dfin_pll < 7 * MHZ)
exynos_mipi_dsi_enable_afc(dsim, 1, 0x1);
else if (dfin_pll < 8 * MHZ)
exynos_mipi_dsi_enable_afc(dsim, 1, 0x0);
else if (dfin_pll < 9 * MHZ)
exynos_mipi_dsi_enable_afc(dsim, 1, 0x3);
else if (dfin_pll < 10 * MHZ)
exynos_mipi_dsi_enable_afc(dsim, 1, 0x2);
else if (dfin_pll < 11 * MHZ)
exynos_mipi_dsi_enable_afc(dsim, 1, 0x5);
else
exynos_mipi_dsi_enable_afc(dsim, 1, 0x4);
}
dfvco = dfin_pll * main_divider;
dev_dbg(dsim->dev, "dfvco = %lu, dfin_pll = %lu, main_divider = %d\n",
dfvco, dfin_pll, main_divider);
if (dfvco < DFVCO_MIN_HZ || dfvco > DFVCO_MAX_HZ)
dev_warn(dsim->dev, "fvco range should be 500MHz ~ 1000MHz\n");
dpll_out = dfvco / (1 << scaler);
dev_dbg(dsim->dev, "dpll_out = %lu, dfvco = %lu, scaler = %d\n",
dpll_out, dfvco, scaler);
for (i = 0; i < ARRAY_SIZE(dpll_table); i++) {
if (dpll_out < dpll_table[i] * MHZ) {
freq_band = i;
break;
}
}
dev_dbg(dsim->dev, "freq_band = %d\n", freq_band);
exynos_mipi_dsi_pll_freq(dsim, pre_divider, main_divider, scaler);
exynos_mipi_dsi_hs_zero_ctrl(dsim, 0);
exynos_mipi_dsi_prep_ctrl(dsim, 0);
/* Freq Band */
exynos_mipi_dsi_pll_freq_band(dsim, freq_band);
/* Stable time */
exynos_mipi_dsi_pll_stable_time(dsim, dsim->dsim_config->pll_stable_time);
/* Enable PLL */
dev_dbg(dsim->dev, "FOUT of mipi dphy pll is %luMHz\n",
(dpll_out / MHZ));
return dpll_out;
}
static int exynos_mipi_dsi_set_clock(struct mipi_dsim_device *dsim,
unsigned int byte_clk_sel, unsigned int enable)
{
unsigned int esc_div;
unsigned long esc_clk_error_rate;
unsigned long hs_clk = 0, byte_clk = 0, escape_clk = 0;
if (enable) {
dsim->e_clk_src = byte_clk_sel;
/* Escape mode clock and byte clock source */
exynos_mipi_dsi_set_byte_clock_src(dsim, byte_clk_sel);
/* DPHY, DSIM Link : D-PHY clock out */
if (byte_clk_sel == DSIM_PLL_OUT_DIV8) {
hs_clk = exynos_mipi_dsi_change_pll(dsim,
dsim->dsim_config->p, dsim->dsim_config->m,
dsim->dsim_config->s);
if (hs_clk == 0) {
dev_err(dsim->dev,
"failed to get hs clock.\n");
return -EINVAL;
}
byte_clk = hs_clk / 8;
exynos_mipi_dsi_enable_pll_bypass(dsim, 0);
exynos_mipi_dsi_pll_on(dsim, 1);
/* DPHY : D-PHY clock out, DSIM link : external clock out */
} else if (byte_clk_sel == DSIM_EXT_CLK_DIV8) {
dev_warn(dsim->dev, "this project is not support\n");
dev_warn(dsim->dev,
"external clock source for MIPI DSIM.\n");
} else if (byte_clk_sel == DSIM_EXT_CLK_BYPASS) {
dev_warn(dsim->dev, "this project is not support\n");
dev_warn(dsim->dev,
"external clock source for MIPI DSIM\n");
}
/* escape clock divider */
esc_div = byte_clk / (dsim->dsim_config->esc_clk);
dev_dbg(dsim->dev,
"esc_div = %d, byte_clk = %lu, esc_clk = %lu\n",
esc_div, byte_clk, dsim->dsim_config->esc_clk);
if ((byte_clk / esc_div) >= (20 * MHZ) ||
(byte_clk / esc_div) >
dsim->dsim_config->esc_clk)
esc_div += 1;
escape_clk = byte_clk / esc_div;
dev_dbg(dsim->dev,
"escape_clk = %lu, byte_clk = %lu, esc_div = %d\n",
escape_clk, byte_clk, esc_div);
/* enable escape clock. */
exynos_mipi_dsi_enable_byte_clock(dsim, 1);
/* enable byte clk and escape clock */
exynos_mipi_dsi_set_esc_clk_prs(dsim, 1, esc_div);
/* escape clock on lane */
exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,
(DSIM_LANE_CLOCK | dsim->data_lane), 1);
dev_dbg(dsim->dev, "byte clock is %luMHz\n",
(byte_clk / MHZ));
dev_dbg(dsim->dev, "escape clock that user's need is %lu\n",
(dsim->dsim_config->esc_clk / MHZ));
dev_dbg(dsim->dev, "escape clock divider is %x\n", esc_div);
dev_dbg(dsim->dev, "escape clock is %luMHz\n",
((byte_clk / esc_div) / MHZ));
if ((byte_clk / esc_div) > escape_clk) {
esc_clk_error_rate = escape_clk /
(byte_clk / esc_div);
dev_warn(dsim->dev, "error rate is %lu over.\n",
(esc_clk_error_rate / 100));
} else if ((byte_clk / esc_div) < (escape_clk)) {
esc_clk_error_rate = (byte_clk / esc_div) /
escape_clk;
dev_warn(dsim->dev, "error rate is %lu under.\n",
(esc_clk_error_rate / 100));
}
} else {
exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,
(DSIM_LANE_CLOCK | dsim->data_lane), 0);
exynos_mipi_dsi_set_esc_clk_prs(dsim, 0, 0);
/* disable escape clock. */
exynos_mipi_dsi_enable_byte_clock(dsim, 0);
if (byte_clk_sel == DSIM_PLL_OUT_DIV8)
exynos_mipi_dsi_pll_on(dsim, 0);
}
return 0;
}
int exynos_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim)
{
dsim->state = DSIM_STATE_INIT;
switch (dsim->dsim_config->e_no_data_lane) {
case DSIM_DATA_LANE_1:
dsim->data_lane = DSIM_LANE_DATA0;
break;
case DSIM_DATA_LANE_2:
dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1;
break;
case DSIM_DATA_LANE_3:
dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
DSIM_LANE_DATA2;
break;
case DSIM_DATA_LANE_4:
dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
DSIM_LANE_DATA2 | DSIM_LANE_DATA3;
break;
default:
dev_info(dsim->dev, "data lane is invalid.\n");
return -EINVAL;
};
exynos_mipi_dsi_sw_reset(dsim);
exynos_mipi_dsi_func_reset(dsim);
exynos_mipi_dsi_dp_dn_swap(dsim, 0);
return 0;
}
void exynos_mipi_dsi_init_interrupt(struct mipi_dsim_device *dsim)
{
unsigned int src = 0;
src = (INTSRC_SFR_FIFO_EMPTY | INTSRC_RX_DATA_DONE);
exynos_mipi_dsi_set_interrupt(dsim, src, 1);
src = 0;
src = ~(INTMSK_RX_DONE | INTMSK_FIFO_EMPTY);
exynos_mipi_dsi_set_interrupt_mask(dsim, src, 1);
}
int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,
unsigned int enable)
{
/* enable only frame done interrupt */
exynos_mipi_dsi_set_interrupt_mask(dsim, INTMSK_FRAME_DONE, enable);
return 0;
}
void exynos_mipi_dsi_stand_by(struct mipi_dsim_device *dsim,
unsigned int enable)
{
/* consider Main display and Sub display. */
exynos_mipi_dsi_set_main_stand_by(dsim, enable);
}
int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,
struct mipi_dsim_config *dsim_config)
{
struct mipi_dsim_platform_data *dsim_pd;
struct fb_videomode *timing;
dsim_pd = (struct mipi_dsim_platform_data *)dsim->pd;
timing = (struct fb_videomode *)dsim_pd->lcd_panel_info;
/* in case of VIDEO MODE (RGB INTERFACE), it sets polarities. */
if (dsim_config->e_interface == (u32) DSIM_VIDEO) {
if (dsim_config->auto_vertical_cnt == 0) {
exynos_mipi_dsi_set_main_disp_vporch(dsim,
dsim_config->cmd_allow,
timing->upper_margin,
timing->lower_margin);
exynos_mipi_dsi_set_main_disp_hporch(dsim,
timing->left_margin,
timing->right_margin);
exynos_mipi_dsi_set_main_disp_sync_area(dsim,
timing->vsync_len,
timing->hsync_len);
}
}
exynos_mipi_dsi_set_main_disp_resol(dsim, timing->xres,
timing->yres);
exynos_mipi_dsi_display_config(dsim, dsim_config);
dev_info(dsim->dev, "lcd panel ==> width = %d, height = %d\n",
timing->xres, timing->yres);
return 0;
}
int exynos_mipi_dsi_init_link(struct mipi_dsim_device *dsim)
{
unsigned int time_out = 100;
switch (dsim->state) {
case DSIM_STATE_INIT:
exynos_mipi_dsi_init_fifo_pointer(dsim, 0x1f);
/* dsi configuration */
exynos_mipi_dsi_init_config(dsim);
exynos_mipi_dsi_enable_lane(dsim, DSIM_LANE_CLOCK, 1);
exynos_mipi_dsi_enable_lane(dsim, dsim->data_lane, 1);
/* set clock configuration */
exynos_mipi_dsi_set_clock(dsim, dsim->dsim_config->e_byte_clk, 1);
/* check clock and data lane state are stop state */
while (!(exynos_mipi_dsi_is_lane_state(dsim))) {
time_out--;
if (time_out == 0) {
dev_err(dsim->dev,
"DSI Master is not stop state.\n");
dev_err(dsim->dev,
"Check initialization process\n");
return -EINVAL;
}
}
if (time_out != 0) {
dev_info(dsim->dev,
"DSI Master driver has been completed.\n");
dev_info(dsim->dev, "DSI Master state is stop state\n");
}
dsim->state = DSIM_STATE_STOP;
/* BTA sequence counters */
exynos_mipi_dsi_set_stop_state_counter(dsim,
dsim->dsim_config->stop_holding_cnt);
exynos_mipi_dsi_set_bta_timeout(dsim,
dsim->dsim_config->bta_timeout);
exynos_mipi_dsi_set_lpdr_timeout(dsim,
dsim->dsim_config->rx_timeout);
return 0;
default:
dev_info(dsim->dev, "DSI Master is already init.\n");
return 0;
}
return 0;
}
int exynos_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim)
{
if (dsim->state != DSIM_STATE_STOP) {
dev_warn(dsim->dev, "DSIM is not in stop state.\n");
return 0;
}
if (dsim->e_clk_src == DSIM_EXT_CLK_BYPASS) {
dev_warn(dsim->dev, "clock source is external bypass.\n");
return 0;
}
dsim->state = DSIM_STATE_HSCLKEN;
/* set LCDC and CPU transfer mode to HS. */
exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
exynos_mipi_dsi_enable_hs_clock(dsim, 1);
return 0;
}
int exynos_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim,
unsigned int mode)
{
if (mode) {
if (dsim->state != DSIM_STATE_HSCLKEN) {
dev_err(dsim->dev, "HS Clock lane is not enabled.\n");
return -EINVAL;
}
exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
} else {
if (dsim->state == DSIM_STATE_INIT || dsim->state ==
DSIM_STATE_ULPS) {
dev_err(dsim->dev,
"DSI Master is not STOP or HSDT state.\n");
return -EINVAL;
}
exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
}
return 0;
}
int exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim)
{
return _exynos_mipi_dsi_get_frame_done_status(dsim);
}
int exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim)
{
_exynos_mipi_dsi_clear_frame_done(dsim);
return 0;
}
int exynos_mipi_dsi_fifo_clear(struct mipi_dsim_device *dsim,
unsigned int val)
{
int try = TRY_FIFO_CLEAR;
exynos_mipi_dsi_sw_reset_release(dsim);
exynos_mipi_dsi_func_reset(dsim);
do {
if (exynos_mipi_dsi_get_sw_reset_release(dsim)) {
exynos_mipi_dsi_init_interrupt(dsim);
dev_dbg(dsim->dev, "reset release done.\n");
return 0;
}
} while (--try);
dev_err(dsim->dev, "failed to clear dsim fifo.\n");
return -EAGAIN;
}
MODULE_AUTHOR("InKi Dae <inki.dae@samsung.com>");
MODULE_DESCRIPTION("Samusung SoC MIPI-DSI common driver");
MODULE_LICENSE("GPL");

46
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/* linux/drivers/video/exynos_mipi_dsi_common.h
*
* Header file for Samsung SoC MIPI-DSI common driver.
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd
*
* InKi Dae <inki.dae@samsung.com>
* Donghwa Lee <dh09.lee@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _EXYNOS_MIPI_DSI_COMMON_H
#define _EXYNOS_MIPI_DSI_COMMON_H
static DECLARE_COMPLETION(dsim_rd_comp);
static DECLARE_COMPLETION(dsim_wr_comp);
int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,
const unsigned char *data0, unsigned int data_size);
int exynos_mipi_dsi_rd_data(struct mipi_dsim_device *dsim, unsigned int data_id,
unsigned int data0, unsigned int req_size, u8 *rx_buf);
irqreturn_t exynos_mipi_dsi_interrupt_handler(int irq, void *dev_id);
void exynos_mipi_dsi_init_interrupt(struct mipi_dsim_device *dsim);
int exynos_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim);
void exynos_mipi_dsi_stand_by(struct mipi_dsim_device *dsim,
unsigned int enable);
int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,
struct mipi_dsim_config *dsim_info);
int exynos_mipi_dsi_init_link(struct mipi_dsim_device *dsim);
int exynos_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim);
int exynos_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim,
unsigned int mode);
int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,
unsigned int enable);
int exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim);
int exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim);
extern struct fb_info *registered_fb[FB_MAX] __read_mostly;
int exynos_mipi_dsi_fifo_clear(struct mipi_dsim_device *dsim,
unsigned int val);
#endif /* _EXYNOS_MIPI_DSI_COMMON_H */

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/* linux/drivers/video/exynos/exynos_mipi_dsi_lowlevel.c
*
* Samsung SoC MIPI-DSI lowlevel driver.
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd
*
* InKi Dae, <inki.dae@samsung.com>
* Donghwa Lee, <dh09.lee@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/mutex.h>
#include <linux/wait.h>
#include <linux/delay.h>
#include <linux/fs.h>
#include <linux/mm.h>
#include <linux/ctype.h>
#include <linux/io.h>
#include <video/exynos_mipi_dsim.h>
#include <mach/map.h>
#include "exynos_mipi_dsi_regs.h"
void exynos_mipi_dsi_func_reset(struct mipi_dsim_device *dsim)
{
unsigned int reg;
reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST);
reg |= DSIM_FUNCRST;
writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST);
}
void exynos_mipi_dsi_sw_reset(struct mipi_dsim_device *dsim)
{
unsigned int reg;
reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST);
reg |= DSIM_SWRST;
writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST);
}
void exynos_mipi_dsi_sw_reset_release(struct mipi_dsim_device *dsim)
{
unsigned int reg;
reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
reg |= INTSRC_SW_RST_RELEASE;
writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC);
}
int exynos_mipi_dsi_get_sw_reset_release(struct mipi_dsim_device *dsim)
{
return (readl(dsim->reg_base + EXYNOS_DSIM_INTSRC)) &
INTSRC_SW_RST_RELEASE;
}
unsigned int exynos_mipi_dsi_read_interrupt_mask(struct mipi_dsim_device *dsim)
{
unsigned int reg;
reg = readl(dsim->reg_base + EXYNOS_DSIM_INTMSK);
return reg;
}
void exynos_mipi_dsi_set_interrupt_mask(struct mipi_dsim_device *dsim,
unsigned int mode, unsigned int mask)
{
unsigned int reg = 0;
if (mask)
reg |= mode;
else
reg &= ~mode;
writel(reg, dsim->reg_base + EXYNOS_DSIM_INTMSK);
}
void exynos_mipi_dsi_init_fifo_pointer(struct mipi_dsim_device *dsim,
unsigned int cfg)
{
unsigned int reg;
reg = readl(dsim->reg_base + EXYNOS_DSIM_FIFOCTRL);
writel(reg & ~(cfg), dsim->reg_base + EXYNOS_DSIM_FIFOCTRL);
mdelay(10);
reg |= cfg;
writel(reg, dsim->reg_base + EXYNOS_DSIM_FIFOCTRL);
}
/*
* this function set PLL P, M and S value in D-PHY
*/
void exynos_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim,
unsigned int value)
{
writel(DSIM_AFC_CTL(value), dsim->reg_base + EXYNOS_DSIM_PHYACCHR);
}
void exynos_mipi_dsi_set_main_stand_by(struct mipi_dsim_device *dsim,
unsigned int enable)
{
unsigned int reg;
reg = readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL);
reg &= ~DSIM_MAIN_STAND_BY;
if (enable)
reg |= DSIM_MAIN_STAND_BY;
writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL);
}
void exynos_mipi_dsi_set_main_disp_resol(struct mipi_dsim_device *dsim,
unsigned int width_resol, unsigned int height_resol)
{
unsigned int reg;
/* standby should be set after configuration so set to not ready*/
reg = (readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL)) &
~(DSIM_MAIN_STAND_BY);
writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL);
reg &= ~((0x7ff << 16) | (0x7ff << 0));
reg |= DSIM_MAIN_VRESOL(height_resol) | DSIM_MAIN_HRESOL(width_resol);
reg |= DSIM_MAIN_STAND_BY;
writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL);
}
void exynos_mipi_dsi_set_main_disp_vporch(struct mipi_dsim_device *dsim,
unsigned int cmd_allow, unsigned int vfront, unsigned int vback)
{
unsigned int reg;
reg = (readl(dsim->reg_base + EXYNOS_DSIM_MVPORCH)) &
~((DSIM_CMD_ALLOW_MASK) | (DSIM_STABLE_VFP_MASK) |
(DSIM_MAIN_VBP_MASK));
reg |= (DSIM_CMD_ALLOW_SHIFT(cmd_allow & 0xf) |
DSIM_STABLE_VFP_SHIFT(vfront & 0x7ff) |
DSIM_MAIN_VBP_SHIFT(vback & 0x7ff));
writel(reg, dsim->reg_base + EXYNOS_DSIM_MVPORCH);
}
void exynos_mipi_dsi_set_main_disp_hporch(struct mipi_dsim_device *dsim,
unsigned int front, unsigned int back)
{
unsigned int reg;
reg = (readl(dsim->reg_base + EXYNOS_DSIM_MHPORCH)) &
~((DSIM_MAIN_HFP_MASK) | (DSIM_MAIN_HBP_MASK));
reg |= DSIM_MAIN_HFP_SHIFT(front) | DSIM_MAIN_HBP_SHIFT(back);
writel(reg, dsim->reg_base + EXYNOS_DSIM_MHPORCH);
}
void exynos_mipi_dsi_set_main_disp_sync_area(struct mipi_dsim_device *dsim,
unsigned int vert, unsigned int hori)
{
unsigned int reg;
reg = (readl(dsim->reg_base + EXYNOS_DSIM_MSYNC)) &
~((DSIM_MAIN_VSA_MASK) | (DSIM_MAIN_HSA_MASK));
reg |= (DSIM_MAIN_VSA_SHIFT(vert & 0x3ff) |
DSIM_MAIN_HSA_SHIFT(hori));
writel(reg, dsim->reg_base + EXYNOS_DSIM_MSYNC);
}
void exynos_mipi_dsi_set_sub_disp_resol(struct mipi_dsim_device *dsim,
unsigned int vert, unsigned int hori)
{
unsigned int reg;
reg = (readl(dsim->reg_base + EXYNOS_DSIM_SDRESOL)) &
~(DSIM_SUB_STANDY_MASK);
writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL);
reg &= ~(DSIM_SUB_VRESOL_MASK) | ~(DSIM_SUB_HRESOL_MASK);
reg |= (DSIM_SUB_VRESOL_SHIFT(vert & 0x7ff) |
DSIM_SUB_HRESOL_SHIFT(hori & 0x7ff));
writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL);
reg |= DSIM_SUB_STANDY_SHIFT(1);
writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL);
}
void exynos_mipi_dsi_init_config(struct mipi_dsim_device *dsim)
{
struct mipi_dsim_config *dsim_config = dsim->dsim_config;
unsigned int cfg = (readl(dsim->reg_base + EXYNOS_DSIM_CONFIG)) &
~((1 << 28) | (0x1f << 20) | (0x3 << 5));
cfg = ((DSIM_AUTO_FLUSH(dsim_config->auto_flush)) |
(DSIM_EOT_DISABLE(dsim_config->eot_disable)) |
(DSIM_AUTO_MODE_SHIFT(dsim_config->auto_vertical_cnt)) |
(DSIM_HSE_MODE_SHIFT(dsim_config->hse)) |
(DSIM_HFP_MODE_SHIFT(dsim_config->hfp)) |
(DSIM_HBP_MODE_SHIFT(dsim_config->hbp)) |
(DSIM_HSA_MODE_SHIFT(dsim_config->hsa)) |
(DSIM_NUM_OF_DATALANE_SHIFT(dsim_config->e_no_data_lane)));
writel(cfg, dsim->reg_base + EXYNOS_DSIM_CONFIG);
}
void exynos_mipi_dsi_display_config(struct mipi_dsim_device *dsim,
struct mipi_dsim_config *dsim_config)
{
u32 reg = (readl(dsim->reg_base + EXYNOS_DSIM_CONFIG)) &
~((0x3 << 26) | (1 << 25) | (0x3 << 18) | (0x7 << 12) |
(0x3 << 16) | (0x7 << 8));
if (dsim_config->e_interface == DSIM_VIDEO)
reg |= (1 << 25);
else if (dsim_config->e_interface == DSIM_COMMAND)
reg &= ~(1 << 25);
else {
dev_err(dsim->dev, "unknown lcd type.\n");
return;
}
/* main lcd */
reg |= ((u8) (dsim_config->e_burst_mode) & 0x3) << 26 |
((u8) (dsim_config->e_virtual_ch) & 0x3) << 18 |
((u8) (dsim_config->e_pixel_format) & 0x7) << 12;
writel(reg, dsim->reg_base + EXYNOS_DSIM_CONFIG);
}
void exynos_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim, unsigned int lane,
unsigned int enable)
{
unsigned int reg;
reg = readl(dsim->reg_base + EXYNOS_DSIM_CONFIG);
if (enable)
reg |= DSIM_LANE_ENx(lane);
else
reg &= ~DSIM_LANE_ENx(lane);
writel(reg, dsim->reg_base + EXYNOS_DSIM_CONFIG);
}
void exynos_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim,
unsigned int count)
{
unsigned int cfg;
/* get the data lane number. */
cfg = DSIM_NUM_OF_DATALANE_SHIFT(count);
writel(cfg, dsim->reg_base + EXYNOS_DSIM_CONFIG);
}
void exynos_mipi_dsi_enable_afc(struct mipi_dsim_device *dsim, unsigned int enable,
unsigned int afc_code)
{
unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PHYACCHR);
if (enable) {
reg |= (1 << 14);
reg &= ~(0x7 << 5);
reg |= (afc_code & 0x7) << 5;
} else
reg &= ~(1 << 14);
writel(reg, dsim->reg_base + EXYNOS_DSIM_PHYACCHR);
}
void exynos_mipi_dsi_enable_pll_bypass(struct mipi_dsim_device *dsim,
unsigned int enable)
{
unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
~(DSIM_PLL_BYPASS_SHIFT(0x1));
reg |= DSIM_PLL_BYPASS_SHIFT(enable);
writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
}
void exynos_mipi_dsi_set_pll_pms(struct mipi_dsim_device *dsim, unsigned int p,
unsigned int m, unsigned int s)
{
unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
reg |= ((p & 0x3f) << 13) | ((m & 0x1ff) << 4) | ((s & 0x7) << 1);
writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
}
void exynos_mipi_dsi_pll_freq_band(struct mipi_dsim_device *dsim,
unsigned int freq_band)
{
unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
~(DSIM_FREQ_BAND_SHIFT(0x1f));
reg |= DSIM_FREQ_BAND_SHIFT(freq_band & 0x1f);
writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
}
void exynos_mipi_dsi_pll_freq(struct mipi_dsim_device *dsim,
unsigned int pre_divider, unsigned int main_divider,
unsigned int scaler)
{
unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
~(0x7ffff << 1);
reg |= (pre_divider & 0x3f) << 13 | (main_divider & 0x1ff) << 4 |
(scaler & 0x7) << 1;
writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
}
void exynos_mipi_dsi_pll_stable_time(struct mipi_dsim_device *dsim,
unsigned int lock_time)
{
writel(lock_time, dsim->reg_base + EXYNOS_DSIM_PLLTMR);
}
void exynos_mipi_dsi_enable_pll(struct mipi_dsim_device *dsim, unsigned int enable)
{
unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
~(DSIM_PLL_EN_SHIFT(0x1));
reg |= DSIM_PLL_EN_SHIFT(enable & 0x1);
writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
}
void exynos_mipi_dsi_set_byte_clock_src(struct mipi_dsim_device *dsim,
unsigned int src)
{
unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
~(DSIM_BYTE_CLK_SRC_SHIFT(0x3));
reg |= (DSIM_BYTE_CLK_SRC_SHIFT(src));
writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
}
void exynos_mipi_dsi_enable_byte_clock(struct mipi_dsim_device *dsim,
unsigned int enable)
{
unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
~(DSIM_BYTE_CLKEN_SHIFT(0x1));
reg |= DSIM_BYTE_CLKEN_SHIFT(enable);
writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
}
void exynos_mipi_dsi_set_esc_clk_prs(struct mipi_dsim_device *dsim,
unsigned int enable, unsigned int prs_val)
{
unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
~(DSIM_ESC_CLKEN_SHIFT(0x1) | 0xffff);
reg |= DSIM_ESC_CLKEN_SHIFT(enable);
if (enable)
reg |= prs_val;
writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
}
void exynos_mipi_dsi_enable_esc_clk_on_lane(struct mipi_dsim_device *dsim,
unsigned int lane_sel, unsigned int enable)
{
unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
if (enable)
reg |= DSIM_LANE_ESC_CLKEN(lane_sel);
else
reg &= ~DSIM_LANE_ESC_CLKEN(lane_sel);
writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
}
void exynos_mipi_dsi_force_dphy_stop_state(struct mipi_dsim_device *dsim,
unsigned int enable)
{
unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE)) &
~(DSIM_FORCE_STOP_STATE_SHIFT(0x1));
reg |= (DSIM_FORCE_STOP_STATE_SHIFT(enable & 0x1));
writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);
}
unsigned int exynos_mipi_dsi_is_lane_state(struct mipi_dsim_device *dsim)
{
unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_STATUS);
/**
* check clock and data lane states.
* if MIPI-DSI controller was enabled at bootloader then
* TX_READY_HS_CLK is enabled otherwise STOP_STATE_CLK.
* so it should be checked for two case.
*/
if ((reg & DSIM_STOP_STATE_DAT(0xf)) &&
((reg & DSIM_STOP_STATE_CLK) ||
(reg & DSIM_TX_READY_HS_CLK)))
return 1;
return 0;
}
void exynos_mipi_dsi_set_stop_state_counter(struct mipi_dsim_device *dsim,
unsigned int cnt_val)
{
unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE)) &
~(DSIM_STOP_STATE_CNT_SHIFT(0x7ff));
reg |= (DSIM_STOP_STATE_CNT_SHIFT(cnt_val & 0x7ff));
writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);
}
void exynos_mipi_dsi_set_bta_timeout(struct mipi_dsim_device *dsim,
unsigned int timeout)
{
unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_TIMEOUT)) &
~(DSIM_BTA_TOUT_SHIFT(0xff));
reg |= (DSIM_BTA_TOUT_SHIFT(timeout));
writel(reg, dsim->reg_base + EXYNOS_DSIM_TIMEOUT);
}
void exynos_mipi_dsi_set_lpdr_timeout(struct mipi_dsim_device *dsim,
unsigned int timeout)
{
unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_TIMEOUT)) &
~(DSIM_LPDR_TOUT_SHIFT(0xffff));
reg |= (DSIM_LPDR_TOUT_SHIFT(timeout));
writel(reg, dsim->reg_base + EXYNOS_DSIM_TIMEOUT);
}
void exynos_mipi_dsi_set_cpu_transfer_mode(struct mipi_dsim_device *dsim,
unsigned int lp)
{
unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE);
reg &= ~DSIM_CMD_LPDT_LP;
if (lp)
reg |= DSIM_CMD_LPDT_LP;
writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);
}
void exynos_mipi_dsi_set_lcdc_transfer_mode(struct mipi_dsim_device *dsim,
unsigned int lp)
{
unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE);
reg &= ~DSIM_TX_LPDT_LP;
if (lp)
reg |= DSIM_TX_LPDT_LP;
writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);
}
void exynos_mipi_dsi_enable_hs_clock(struct mipi_dsim_device *dsim,
unsigned int enable)
{
unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
~(DSIM_TX_REQUEST_HSCLK_SHIFT(0x1));
reg |= DSIM_TX_REQUEST_HSCLK_SHIFT(enable);
writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
}
void exynos_mipi_dsi_dp_dn_swap(struct mipi_dsim_device *dsim,
unsigned int swap_en)
{
unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PHYACCHR1);
reg &= ~(0x3 << 0);
reg |= (swap_en & 0x3) << 0;
writel(reg, dsim->reg_base + EXYNOS_DSIM_PHYACCHR1);
}
void exynos_mipi_dsi_hs_zero_ctrl(struct mipi_dsim_device *dsim,
unsigned int hs_zero)
{
unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
~(0xf << 28);
reg |= ((hs_zero & 0xf) << 28);
writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
}
void exynos_mipi_dsi_prep_ctrl(struct mipi_dsim_device *dsim, unsigned int prep)
{
unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
~(0x7 << 20);
reg |= ((prep & 0x7) << 20);
writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
}
unsigned int exynos_mipi_dsi_read_interrupt(struct mipi_dsim_device *dsim)
{
return readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
}
void exynos_mipi_dsi_clear_interrupt(struct mipi_dsim_device *dsim,
unsigned int src)
{
unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
reg |= src;
writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC);
}
void exynos_mipi_dsi_set_interrupt(struct mipi_dsim_device *dsim,
unsigned int src, unsigned int enable)
{
unsigned int reg = 0;
if (enable)
reg |= src;
else
reg &= ~src;
writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC);
}
unsigned int exynos_mipi_dsi_is_pll_stable(struct mipi_dsim_device *dsim)
{
unsigned int reg;
reg = readl(dsim->reg_base + EXYNOS_DSIM_STATUS);
return reg & (1 << 31) ? 1 : 0;
}
unsigned int exynos_mipi_dsi_get_fifo_state(struct mipi_dsim_device *dsim)
{
return readl(dsim->reg_base + EXYNOS_DSIM_FIFOCTRL) & ~(0x1f);
}
void exynos_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim,
unsigned int di, unsigned int data0, unsigned int data1)
{
unsigned int reg = (data1 << 16) | (data0 << 8) | ((di & 0x3f) << 0);
writel(reg, dsim->reg_base + EXYNOS_DSIM_PKTHDR);
}
void exynos_mipi_dsi_rd_tx_header(struct mipi_dsim_device *dsim,
unsigned int di, unsigned int data0)
{
unsigned int reg = (data0 << 8) | (di << 0);
writel(reg, dsim->reg_base + EXYNOS_DSIM_PKTHDR);
}
unsigned int exynos_mipi_dsi_rd_rx_fifo(struct mipi_dsim_device *dsim)
{
return readl(dsim->reg_base + EXYNOS_DSIM_RXFIFO);
}
unsigned int _exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim)
{
unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
return (reg & INTSRC_FRAME_DONE) ? 1 : 0;
}
void _exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim)
{
unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
writel(reg | INTSRC_FRAME_DONE, dsim->reg_base +
EXYNOS_DSIM_INTSRC);
}
void exynos_mipi_dsi_wr_tx_data(struct mipi_dsim_device *dsim,
unsigned int tx_data)
{
writel(tx_data, dsim->reg_base + EXYNOS_DSIM_PAYLOAD);
}

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drivers/video/exynos/exynos_mipi_dsi_lowlevel.h Normal file
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/* linux/drivers/video/exynos/exynos_mipi_dsi_lowlevel.h
*
* Header file for Samsung SoC MIPI-DSI lowlevel driver.
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd
*
* InKi Dae <inki.dae@samsung.com>
* Donghwa Lee <dh09.lee@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _EXYNOS_MIPI_DSI_LOWLEVEL_H
#define _EXYNOS_MIPI_DSI_LOWLEVEL_H
void exynos_mipi_dsi_func_reset(struct mipi_dsim_device *dsim);
void exynos_mipi_dsi_sw_reset(struct mipi_dsim_device *dsim);
void exynos_mipi_dsi_sw_reset_release(struct mipi_dsim_device *dsim);
int exynos_mipi_dsi_get_sw_reset_release(struct mipi_dsim_device *dsim);
void exynos_mipi_dsi_set_interrupt_mask(struct mipi_dsim_device *dsim,
unsigned int mode, unsigned int mask);
void exynos_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim,
unsigned int count);
void exynos_mipi_dsi_init_fifo_pointer(struct mipi_dsim_device *dsim,
unsigned int cfg);
void exynos_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim,
unsigned int value);
void exynos_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim,
unsigned int value);
void exynos_mipi_dsi_set_main_stand_by(struct mipi_dsim_device *dsim,
unsigned int enable);
void exynos_mipi_dsi_set_main_disp_resol(struct mipi_dsim_device *dsim,
unsigned int width_resol, unsigned int height_resol);
void exynos_mipi_dsi_set_main_disp_vporch(struct mipi_dsim_device *dsim,
unsigned int cmd_allow, unsigned int vfront, unsigned int vback);
void exynos_mipi_dsi_set_main_disp_hporch(struct mipi_dsim_device *dsim,
unsigned int front, unsigned int back);
void exynos_mipi_dsi_set_main_disp_sync_area(struct mipi_dsim_device *dsim,
unsigned int vert, unsigned int hori);
void exynos_mipi_dsi_set_sub_disp_resol(struct mipi_dsim_device *dsim,
unsigned int vert, unsigned int hori);
void exynos_mipi_dsi_init_config(struct mipi_dsim_device *dsim);
void exynos_mipi_dsi_display_config(struct mipi_dsim_device *dsim,
struct mipi_dsim_config *dsim_config);
void exynos_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim,
unsigned int count);
void exynos_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim, unsigned int lane,
unsigned int enable);
void exynos_mipi_dsi_enable_afc(struct mipi_dsim_device *dsim, unsigned int enable,
unsigned int afc_code);
void exynos_mipi_dsi_enable_pll_bypass(struct mipi_dsim_device *dsim,
unsigned int enable);
void exynos_mipi_dsi_set_pll_pms(struct mipi_dsim_device *dsim, unsigned int p,
unsigned int m, unsigned int s);
void exynos_mipi_dsi_pll_freq_band(struct mipi_dsim_device *dsim,
unsigned int freq_band);
void exynos_mipi_dsi_pll_freq(struct mipi_dsim_device *dsim,
unsigned int pre_divider, unsigned int main_divider,
unsigned int scaler);
void exynos_mipi_dsi_pll_stable_time(struct mipi_dsim_device *dsim,
unsigned int lock_time);
void exynos_mipi_dsi_enable_pll(struct mipi_dsim_device *dsim,
unsigned int enable);
void exynos_mipi_dsi_set_byte_clock_src(struct mipi_dsim_device *dsim,
unsigned int src);
void exynos_mipi_dsi_enable_byte_clock(struct mipi_dsim_device *dsim,
unsigned int enable);
void exynos_mipi_dsi_set_esc_clk_prs(struct mipi_dsim_device *dsim,
unsigned int enable, unsigned int prs_val);
void exynos_mipi_dsi_enable_esc_clk_on_lane(struct mipi_dsim_device *dsim,
unsigned int lane_sel, unsigned int enable);
void exynos_mipi_dsi_force_dphy_stop_state(struct mipi_dsim_device *dsim,
unsigned int enable);
unsigned int exynos_mipi_dsi_is_lane_state(struct mipi_dsim_device *dsim);
void exynos_mipi_dsi_set_stop_state_counter(struct mipi_dsim_device *dsim,
unsigned int cnt_val);
void exynos_mipi_dsi_set_bta_timeout(struct mipi_dsim_device *dsim,
unsigned int timeout);
void exynos_mipi_dsi_set_lpdr_timeout(struct mipi_dsim_device *dsim,
unsigned int timeout);
void exynos_mipi_dsi_set_lcdc_transfer_mode(struct mipi_dsim_device *dsim,
unsigned int lp);
void exynos_mipi_dsi_set_cpu_transfer_mode(struct mipi_dsim_device *dsim,
unsigned int lp);
void exynos_mipi_dsi_enable_hs_clock(struct mipi_dsim_device *dsim,
unsigned int enable);
void exynos_mipi_dsi_dp_dn_swap(struct mipi_dsim_device *dsim,
unsigned int swap_en);
void exynos_mipi_dsi_hs_zero_ctrl(struct mipi_dsim_device *dsim,
unsigned int hs_zero);
void exynos_mipi_dsi_prep_ctrl(struct mipi_dsim_device *dsim, unsigned int prep);
unsigned int exynos_mipi_dsi_read_interrupt(struct mipi_dsim_device *dsim);
unsigned int exynos_mipi_dsi_read_interrupt_mask(struct mipi_dsim_device *dsim);
void exynos_mipi_dsi_clear_interrupt(struct mipi_dsim_device *dsim,
unsigned int src);
void exynos_mipi_dsi_set_interrupt(struct mipi_dsim_device *dsim,
unsigned int src, unsigned int enable);
unsigned int exynos_mipi_dsi_is_pll_stable(struct mipi_dsim_device *dsim);
unsigned int exynos_mipi_dsi_get_fifo_state(struct mipi_dsim_device *dsim);
unsigned int _exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim);
void _exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim);
void exynos_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim, unsigned int di,
unsigned int data0, unsigned int data1);
void exynos_mipi_dsi_wr_tx_data(struct mipi_dsim_device *dsim,
unsigned int tx_data);
void exynos_mipi_dsi_rd_tx_header(struct mipi_dsim_device *dsim,
unsigned int data0, unsigned int data1);
unsigned int exynos_mipi_dsi_rd_rx_fifo(struct mipi_dsim_device *dsim);
#endif /* _EXYNOS_MIPI_DSI_LOWLEVEL_H */

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drivers/video/exynos/exynos_mipi_dsi_regs.h Normal file
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/* linux/driver/video/exynos/exynos_mipi_dsi_regs.h
*
* Register definition file for Samsung MIPI-DSIM driver
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd
*
* InKi Dae <inki.dae@samsung.com>
* Donghwa Lee <dh09.lee@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _EXYNOS_MIPI_DSI_REGS_H
#define _EXYNOS_MIPI_DSI_REGS_H
#define EXYNOS_DSIM_STATUS 0x0 /* Status register */
#define EXYNOS_DSIM_SWRST 0x4 /* Software reset register */
#define EXYNOS_DSIM_CLKCTRL 0x8 /* Clock control register */
#define EXYNOS_DSIM_TIMEOUT 0xc /* Time out register */
#define EXYNOS_DSIM_CONFIG 0x10 /* Configuration register */
#define EXYNOS_DSIM_ESCMODE 0x14 /* Escape mode register */
/* Main display image resolution register */
#define EXYNOS_DSIM_MDRESOL 0x18
#define EXYNOS_DSIM_MVPORCH 0x1c /* Main display Vporch register */
#define EXYNOS_DSIM_MHPORCH 0x20 /* Main display Hporch register */
#define EXYNOS_DSIM_MSYNC 0x24 /* Main display sync area register */
/* Sub display image resolution register */
#define EXYNOS_DSIM_SDRESOL 0x28
#define EXYNOS_DSIM_INTSRC 0x2c /* Interrupt source register */
#define EXYNOS_DSIM_INTMSK 0x30 /* Interrupt mask register */
#define EXYNOS_DSIM_PKTHDR 0x34 /* Packet Header FIFO register */
#define EXYNOS_DSIM_PAYLOAD 0x38 /* Payload FIFO register */
#define EXYNOS_DSIM_RXFIFO 0x3c /* Read FIFO register */
#define EXYNOS_DSIM_FIFOTHLD 0x40 /* FIFO threshold level register */
#define EXYNOS_DSIM_FIFOCTRL 0x44 /* FIFO status and control register */
/* FIFO memory AC characteristic register */
#define EXYNOS_DSIM_PLLCTRL 0x4c /* PLL control register */
#define EXYNOS_DSIM_PLLTMR 0x50 /* PLL timer register */
#define EXYNOS_DSIM_PHYACCHR 0x54 /* D-PHY AC characteristic register */
#define EXYNOS_DSIM_PHYACCHR1 0x58 /* D-PHY AC characteristic register1 */
/* DSIM_STATUS */
#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
#define DSIM_STOP_STATE_CLK (1 << 8)
#define DSIM_TX_READY_HS_CLK (1 << 10)
/* DSIM_SWRST */
#define DSIM_FUNCRST (1 << 16)
#define DSIM_SWRST (1 << 0)
/* EXYNOS_DSIM_TIMEOUT */
#define DSIM_LPDR_TOUT_SHIFT(x) ((x) << 0)
#define DSIM_BTA_TOUT_SHIFT(x) ((x) << 16)
/* EXYNOS_DSIM_CLKCTRL */
#define DSIM_LANE_ESC_CLKEN(x) (((x) & 0x1f) << 19)
#define DSIM_BYTE_CLKEN_SHIFT(x) ((x) << 24)
#define DSIM_BYTE_CLK_SRC_SHIFT(x) ((x) << 25)
#define DSIM_PLL_BYPASS_SHIFT(x) ((x) << 27)
#define DSIM_ESC_CLKEN_SHIFT(x) ((x) << 28)
#define DSIM_TX_REQUEST_HSCLK_SHIFT(x) ((x) << 31)
/* EXYNOS_DSIM_CONFIG */
#define DSIM_LANE_ENx(x) (((x) & 0x1f) << 0)
#define DSIM_NUM_OF_DATALANE_SHIFT(x) ((x) << 5)
#define DSIM_HSA_MODE_SHIFT(x) ((x) << 20)
#define DSIM_HBP_MODE_SHIFT(x) ((x) << 21)
#define DSIM_HFP_MODE_SHIFT(x) ((x) << 22)
#define DSIM_HSE_MODE_SHIFT(x) ((x) << 23)
#define DSIM_AUTO_MODE_SHIFT(x) ((x) << 24)
#define DSIM_EOT_DISABLE(x) ((x) << 28)
#define DSIM_AUTO_FLUSH(x) ((x) << 29)
#define DSIM_NUM_OF_DATA_LANE(x) ((x) << DSIM_NUM_OF_DATALANE_SHIFT)
/* EXYNOS_DSIM_ESCMODE */
#define DSIM_TX_LPDT_LP (1 << 6)
#define DSIM_CMD_LPDT_LP (1 << 7)
#define DSIM_FORCE_STOP_STATE_SHIFT(x) ((x) << 20)
#define DSIM_STOP_STATE_CNT_SHIFT(x) ((x) << 21)
/* EXYNOS_DSIM_MDRESOL */
#define DSIM_MAIN_STAND_BY (1 << 31)
#define DSIM_MAIN_VRESOL(x) (((x) & 0x7ff) << 16)
#define DSIM_MAIN_HRESOL(x) (((x) & 0X7ff) << 0)
/* EXYNOS_DSIM_MVPORCH */
#define DSIM_CMD_ALLOW_SHIFT(x) ((x) << 28)
#define DSIM_STABLE_VFP_SHIFT(x) ((x) << 16)
#define DSIM_MAIN_VBP_SHIFT(x) ((x) << 0)
#define DSIM_CMD_ALLOW_MASK (0xf << 28)
#define DSIM_STABLE_VFP_MASK (0x7ff << 16)
#define DSIM_MAIN_VBP_MASK (0x7ff << 0)
/* EXYNOS_DSIM_MHPORCH */
#define DSIM_MAIN_HFP_SHIFT(x) ((x) << 16)
#define DSIM_MAIN_HBP_SHIFT(x) ((x) << 0)
#define DSIM_MAIN_HFP_MASK ((0xffff) << 16)
#define DSIM_MAIN_HBP_MASK ((0xffff) << 0)
/* EXYNOS_DSIM_MSYNC */
#define DSIM_MAIN_VSA_SHIFT(x) ((x) << 22)
#define DSIM_MAIN_HSA_SHIFT(x) ((x) << 0)
#define DSIM_MAIN_VSA_MASK ((0x3ff) << 22)
#define DSIM_MAIN_HSA_MASK ((0xffff) << 0)
/* EXYNOS_DSIM_SDRESOL */
#define DSIM_SUB_STANDY_SHIFT(x) ((x) << 31)
#define DSIM_SUB_VRESOL_SHIFT(x) ((x) << 16)
#define DSIM_SUB_HRESOL_SHIFT(x) ((x) << 0)
#define DSIM_SUB_STANDY_MASK ((0x1) << 31)
#define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16)
#define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0)
/* EXYNOS_DSIM_INTSRC */
#define INTSRC_PLL_STABLE (1 << 31)
#define INTSRC_SW_RST_RELEASE (1 << 30)
#define INTSRC_SFR_FIFO_EMPTY (1 << 29)
#define INTSRC_FRAME_DONE (1 << 24)
#define INTSRC_RX_DATA_DONE (1 << 18)
/* EXYNOS_DSIM_INTMSK */
#define INTMSK_FIFO_EMPTY (1 << 29)
#define INTMSK_BTA (1 << 25)
#define INTMSK_FRAME_DONE (1 << 24)
#define INTMSK_RX_TIMEOUT (1 << 21)
#define INTMSK_BTA_TIMEOUT (1 << 20)
#define INTMSK_RX_DONE (1 << 18)
#define INTMSK_RX_TE (1 << 17)
#define INTMSK_RX_ACK (1 << 16)
#define INTMSK_RX_ECC_ERR (1 << 15)
#define INTMSK_RX_CRC_ERR (1 << 14)
/* EXYNOS_DSIM_FIFOCTRL */
#define SFR_HEADER_EMPTY (1 << 22)
/* EXYNOS_DSIM_PHYACCHR */
#define DSIM_AFC_CTL(x) (((x) & 0x7) << 5)
/* EXYNOS_DSIM_PLLCTRL */
#define DSIM_PLL_EN_SHIFT(x) ((x) << 23)
#define DSIM_FREQ_BAND_SHIFT(x) ((x) << 24)
#endif /* _EXYNOS_MIPI_DSI_REGS_H */

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drivers/video/exynos/s6e8ax0.c Normal file
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/* linux/drivers/video/exynos/s6e8ax0.c
*
* MIPI-DSI based s6e8ax0 AMOLED lcd 4.65 inch panel driver.
*
* Inki Dae, <inki.dae@samsung.com>
* Donghwa Lee, <dh09.lee@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/mutex.h>
#include <linux/wait.h>
#include <linux/ctype.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/lcd.h>
#include <linux/fb.h>
#include <linux/backlight.h>
#include <linux/regulator/consumer.h>
#include <video/mipi_display.h>
#include <video/exynos_mipi_dsim.h>
#define LDI_MTP_LENGTH 24
#define DSIM_PM_STABLE_TIME 10
#define MIN_BRIGHTNESS 0
#define MAX_BRIGHTNESS 24
#define GAMMA_TABLE_COUNT 26
#define POWER_IS_ON(pwr) ((pwr) == FB_BLANK_UNBLANK)
#define POWER_IS_OFF(pwr) ((pwr) == FB_BLANK_POWERDOWN)
#define POWER_IS_NRM(pwr) ((pwr) == FB_BLANK_NORMAL)
#define lcd_to_master(a) (a->dsim_dev->master)
#define lcd_to_master_ops(a) ((lcd_to_master(a))->master_ops)
enum {
DSIM_NONE_STATE = 0,
DSIM_RESUME_COMPLETE = 1,
DSIM_FRAME_DONE = 2,
};
struct s6e8ax0 {
struct device *dev;
unsigned int power;
unsigned int id;
unsigned int gamma;
unsigned int acl_enable;
unsigned int cur_acl;
struct lcd_device *ld;
struct backlight_device *bd;
struct mipi_dsim_lcd_device *dsim_dev;
struct lcd_platform_data *ddi_pd;
struct mutex lock;
bool enabled;
};
static struct regulator_bulk_data supplies[] = {
{ .supply = "vdd3", },
{ .supply = "vci", },
};
static void s6e8ax0_regulator_enable(struct s6e8ax0 *lcd)
{
int ret = 0;
struct lcd_platform_data *pd = NULL;
pd = lcd->ddi_pd;
mutex_lock(&lcd->lock);
if (!lcd->enabled) {
ret = regulator_bulk_enable(ARRAY_SIZE(supplies), supplies);
if (ret)
goto out;
lcd->enabled = true;
}
msleep(pd->power_on_delay);
out:
mutex_unlock(&lcd->lock);
}
static void s6e8ax0_regulator_disable(struct s6e8ax0 *lcd)
{
int ret = 0;
mutex_lock(&lcd->lock);
if (lcd->enabled) {
ret = regulator_bulk_disable(ARRAY_SIZE(supplies), supplies);
if (ret)
goto out;
lcd->enabled = false;
}
out:
mutex_unlock(&lcd->lock);
}
static const unsigned char s6e8ax0_22_gamma_30[] = {
0xfa, 0x01, 0x60, 0x10, 0x60, 0xf5, 0x00, 0xff, 0xad, 0xaf,
0xbA, 0xc3, 0xd8, 0xc5, 0x9f, 0xc6, 0x9e, 0xc1, 0xdc, 0xc0,
0x00, 0x61, 0x00, 0x5a, 0x00, 0x74,
};
static const unsigned char s6e8ax0_22_gamma_50[] = {
0xfa, 0x01, 0x60, 0x10, 0x60, 0xe8, 0x1f, 0xf7, 0xad, 0xc0,
0xb5, 0xc4, 0xdc, 0xc4, 0x9e, 0xc6, 0x9c, 0xbb, 0xd8, 0xbb,
0x00, 0x70, 0x00, 0x68, 0x00, 0x86,
};
static const unsigned char s6e8ax0_22_gamma_60[] = {
0xfa, 0x01, 0x60, 0x10, 0x60, 0xde, 0x1f, 0xef, 0xad, 0xc4,
0xb3, 0xc3, 0xdd, 0xc4, 0x9e, 0xc6, 0x9c, 0xbc, 0xd6, 0xba,
0x00, 0x75, 0x00, 0x6e, 0x00, 0x8d,
};
static const unsigned char s6e8ax0_22_gamma_70[] = {
0xfa, 0x01, 0x60, 0x10, 0x60, 0xd8, 0x1f, 0xe7, 0xaf, 0xc8,
0xb4, 0xc4, 0xdd, 0xc3, 0x9d, 0xc6, 0x9c, 0xbb, 0xd6, 0xb9,
0x00, 0x7a, 0x00, 0x72, 0x00, 0x93,
};
static const unsigned char s6e8ax0_22_gamma_80[] = {
0xfa, 0x01, 0x60, 0x10, 0x60, 0xc9, 0x1f, 0xde, 0xae, 0xc9,
0xb1, 0xc3, 0xdd, 0xc2, 0x9d, 0xc5, 0x9b, 0xbc, 0xd6, 0xbb,
0x00, 0x7f, 0x00, 0x77, 0x00, 0x99,
};
static const unsigned char s6e8ax0_22_gamma_90[] = {
0xfa, 0x01, 0x60, 0x10, 0x60, 0xc7, 0x1f, 0xd9, 0xb0, 0xcc,
0xb2, 0xc3, 0xdc, 0xc1, 0x9c, 0xc6, 0x9c, 0xbc, 0xd4, 0xb9,
0x00, 0x83, 0x00, 0x7b, 0x00, 0x9e,
};
static const unsigned char s6e8ax0_22_gamma_100[] = {
0xfa, 0x01, 0x60, 0x10, 0x60, 0xbd, 0x80, 0xcd, 0xba, 0xce,
0xb3, 0xc4, 0xde, 0xc3, 0x9c, 0xc4, 0x9, 0xb8, 0xd3, 0xb6,
0x00, 0x88, 0x00, 0x80, 0x00, 0xa5,
};
static const unsigned char s6e8ax0_22_gamma_120[] = {
0xfa, 0x01, 0x60, 0x10, 0x60, 0xb9, 0x95, 0xc8, 0xb1, 0xcf,
0xb2, 0xc6, 0xdf, 0xc5, 0x9b, 0xc3, 0x99, 0xb6, 0xd2, 0xb6,
0x00, 0x8f, 0x00, 0x86, 0x00, 0xac,
};
static const unsigned char s6e8ax0_22_gamma_130[] = {
0xfa, 0x01, 0x60, 0x10, 0x60, 0xb7, 0xa0, 0xc7, 0xb1, 0xd0,
0xb2, 0xc4, 0xdd, 0xc3, 0x9a, 0xc3, 0x98, 0xb6, 0xd0, 0xb4,
0x00, 0x92, 0x00, 0x8a, 0x00, 0xb1,
};
static const unsigned char s6e8ax0_22_gamma_140[] = {
0xfa, 0x01, 0x60, 0x10, 0x60, 0xb7, 0xa0, 0xc5, 0xb2, 0xd0,
0xb3, 0xc3, 0xde, 0xc3, 0x9b, 0xc2, 0x98, 0xb6, 0xd0, 0xb4,
0x00, 0x95, 0x00, 0x8d, 0x00, 0xb5,
};
static const unsigned char s6e8ax0_22_gamma_150[] = {
0xfa, 0x01, 0x60, 0x10, 0x60, 0xb3, 0xa0, 0xc2, 0xb2, 0xd0,
0xb2, 0xc1, 0xdd, 0xc2, 0x9b, 0xc2, 0x98, 0xb4, 0xcf, 0xb1,
0x00, 0x99, 0x00, 0x90, 0x00, 0xba,
};
static const unsigned char s6e8ax0_22_gamma_160[] = {
0xfa, 0x01, 0x60, 0x10, 0x60, 0xaf, 0xa5, 0xbf, 0xb0, 0xd0,
0xb1, 0xc3, 0xde, 0xc2, 0x99, 0xc1, 0x97, 0xb4, 0xce, 0xb1,
0x00, 0x9c, 0x00, 0x93, 0x00, 0xbe,
};
static const unsigned char s6e8ax0_22_gamma_170[] = {
0xfa, 0x01, 0x60, 0x10, 0x60, 0xaf, 0xb5, 0xbf, 0xb1, 0xd1,
0xb1, 0xc3, 0xde, 0xc3, 0x99, 0xc0, 0x96, 0xb4, 0xce, 0xb1,
0x00, 0x9f, 0x00, 0x96, 0x00, 0xc2,
};
static const unsigned char s6e8ax0_22_gamma_180[] = {
0xfa, 0x01, 0x60, 0x10, 0x60, 0xaf, 0xb7, 0xbe, 0xb3, 0xd2,
0xb3, 0xc3, 0xde, 0xc2, 0x97, 0xbf, 0x95, 0xb4, 0xcd, 0xb1,
0x00, 0xa2, 0x00, 0x99, 0x00, 0xc5,
};
static const unsigned char s6e8ax0_22_gamma_190[] = {
0xfa, 0x01, 0x60, 0x10, 0x60, 0xaf, 0xb9, 0xbe, 0xb2, 0xd2,
0xb2, 0xc3, 0xdd, 0xc3, 0x98, 0xbf, 0x95, 0xb2, 0xcc, 0xaf,
0x00, 0xa5, 0x00, 0x9c, 0x00, 0xc9,
};
static const unsigned char s6e8ax0_22_gamma_200[] = {
0xfa, 0x01, 0x60, 0x10, 0x60, 0xaf, 0xb9, 0xbc, 0xb2, 0xd2,
0xb1, 0xc4, 0xdd, 0xc3, 0x97, 0xbe, 0x95, 0xb1, 0xcb, 0xae,
0x00, 0xa8, 0x00, 0x9f, 0x00, 0xcd,
};
static const unsigned char s6e8ax0_22_gamma_210[] = {
0xfa, 0x01, 0x60, 0x10, 0x60, 0xb1, 0xc1, 0xbd, 0xb1, 0xd1,
0xb1, 0xc2, 0xde, 0xc2, 0x97, 0xbe, 0x94, 0xB0, 0xc9, 0xad,
0x00, 0xae, 0x00, 0xa4, 0x00, 0xd4,
};
static const unsigned char s6e8ax0_22_gamma_220[] = {
0xfa, 0x01, 0x60, 0x10, 0x60, 0xb1, 0xc7, 0xbd, 0xb1, 0xd1,
0xb1, 0xc2, 0xdd, 0xc2, 0x97, 0xbd, 0x94, 0xb0, 0xc9, 0xad,
0x00, 0xad, 0x00, 0xa2, 0x00, 0xd3,
};
static const unsigned char s6e8ax0_22_gamma_230[] = {
0xfa, 0x01, 0x60, 0x10, 0x60, 0xb1, 0xc3, 0xbd, 0xb2, 0xd1,
0xb1, 0xc3, 0xdd, 0xc1, 0x96, 0xbd, 0x94, 0xb0, 0xc9, 0xad,
0x00, 0xb0, 0x00, 0xa7, 0x00, 0xd7,
};
static const unsigned char s6e8ax0_22_gamma_240[] = {
0xfa, 0x01, 0x60, 0x10, 0x60, 0xb1, 0xcb, 0xbd, 0xb1, 0xd2,
0xb1, 0xc3, 0xdD, 0xc2, 0x95, 0xbd, 0x93, 0xaf, 0xc8, 0xab,
0x00, 0xb3, 0x00, 0xa9, 0x00, 0xdb,
};
static const unsigned char s6e8ax0_22_gamma_250[] = {
0xfa, 0x01, 0x60, 0x10, 0x60, 0xb3, 0xcc, 0xbe, 0xb0, 0xd2,
0xb0, 0xc3, 0xdD, 0xc2, 0x94, 0xbc, 0x92, 0xae, 0xc8, 0xab,
0x00, 0xb6, 0x00, 0xab, 0x00, 0xde,
};
static const unsigned char s6e8ax0_22_gamma_260[] = {
0xfa, 0x01, 0x60, 0x10, 0x60, 0xb3, 0xd0, 0xbe, 0xaf, 0xd1,
0xaf, 0xc2, 0xdd, 0xc1, 0x96, 0xbc, 0x93, 0xaf, 0xc8, 0xac,
0x00, 0xb7, 0x00, 0xad, 0x00, 0xe0,
};
static const unsigned char s6e8ax0_22_gamma_270[] = {
0xfa, 0x01, 0x60, 0x10, 0x60, 0xb2, 0xcF, 0xbd, 0xb0, 0xd2,
0xaf, 0xc2, 0xdc, 0xc1, 0x95, 0xbd, 0x93, 0xae, 0xc6, 0xaa,
0x00, 0xba, 0x00, 0xb0, 0x00, 0xe4,
};
static const unsigned char s6e8ax0_22_gamma_280[] = {
0xfa, 0x01, 0x60, 0x10, 0x60, 0xb2, 0xd0, 0xbd, 0xaf, 0xd0,
0xad, 0xc4, 0xdd, 0xc3, 0x95, 0xbd, 0x93, 0xac, 0xc5, 0xa9,
0x00, 0xbd, 0x00, 0xb2, 0x00, 0xe7,
};
static const unsigned char s6e8ax0_22_gamma_300[] = {
0xfa, 0x01, 0x60, 0x10, 0x60, 0xb5, 0xd3, 0xbd, 0xb1, 0xd2,
0xb0, 0xc0, 0xdc, 0xc0, 0x94, 0xba, 0x91, 0xac, 0xc5, 0xa9,
0x00, 0xc2, 0x00, 0xb7, 0x00, 0xed,
};
static const unsigned char *s6e8ax0_22_gamma_table[] = {
s6e8ax0_22_gamma_30,
s6e8ax0_22_gamma_50,
s6e8ax0_22_gamma_60,
s6e8ax0_22_gamma_70,
s6e8ax0_22_gamma_80,
s6e8ax0_22_gamma_90,
s6e8ax0_22_gamma_100,
s6e8ax0_22_gamma_120,
s6e8ax0_22_gamma_130,
s6e8ax0_22_gamma_140,
s6e8ax0_22_gamma_150,
s6e8ax0_22_gamma_160,
s6e8ax0_22_gamma_170,
s6e8ax0_22_gamma_180,
s6e8ax0_22_gamma_190,
s6e8ax0_22_gamma_200,
s6e8ax0_22_gamma_210,
s6e8ax0_22_gamma_220,
s6e8ax0_22_gamma_230,
s6e8ax0_22_gamma_240,
s6e8ax0_22_gamma_250,
s6e8ax0_22_gamma_260,
s6e8ax0_22_gamma_270,
s6e8ax0_22_gamma_280,
s6e8ax0_22_gamma_300,
};
static void s6e8ax0_panel_cond(struct s6e8ax0 *lcd)
{
struct mipi_dsim_master_ops *ops = lcd_to_master_ops(lcd);
static const unsigned char data_to_send[] = {
0xf8, 0x3d, 0x35, 0x00, 0x00, 0x00, 0x93, 0x00, 0x3c, 0x7d,
0x08, 0x27, 0x7d, 0x3f, 0x00, 0x00, 0x00, 0x20, 0x04, 0x08,
0x6e, 0x00, 0x00, 0x00, 0x02, 0x08, 0x08, 0x23, 0x23, 0xc0,
0xc8, 0x08, 0x48, 0xc1, 0x00, 0xc1, 0xff, 0xff, 0xc8
};
ops->cmd_write(lcd_to_master(lcd), MIPI_DSI_DCS_LONG_WRITE,
data_to_send, ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_display_cond(struct s6e8ax0 *lcd)
{
struct mipi_dsim_master_ops *ops = lcd_to_master_ops(lcd);
static const unsigned char data_to_send[] = {
0xf2, 0x80, 0x03, 0x0d
};
ops->cmd_write(lcd_to_master(lcd), MIPI_DSI_DCS_LONG_WRITE,
data_to_send, ARRAY_SIZE(data_to_send));
}
/* Gamma 2.2 Setting (200cd, 7500K, 10MPCD) */
static void s6e8ax0_gamma_cond(struct s6e8ax0 *lcd)
{
struct mipi_dsim_master_ops *ops = lcd_to_master_ops(lcd);
unsigned int gamma = lcd->bd->props.brightness;
ops->cmd_write(lcd_to_master(lcd), MIPI_DSI_DCS_LONG_WRITE,
s6e8ax0_22_gamma_table[gamma],
GAMMA_TABLE_COUNT);
}
static void s6e8ax0_gamma_update(struct s6e8ax0 *lcd)
{
struct mipi_dsim_master_ops *ops = lcd_to_master_ops(lcd);
static const unsigned char data_to_send[] = {
0xf7, 0x03
};
ops->cmd_write(lcd_to_master(lcd),
MIPI_DSI_DCS_SHORT_WRITE_PARAM, data_to_send,
ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_etc_cond1(struct s6e8ax0 *lcd)
{
struct mipi_dsim_master_ops *ops = lcd_to_master_ops(lcd);
static const unsigned char data_to_send[] = {
0xd1, 0xfe, 0x80, 0x00, 0x01, 0x0b, 0x00, 0x00, 0x40,
0x0d, 0x00, 0x00
};
ops->cmd_write(lcd_to_master(lcd), MIPI_DSI_DCS_LONG_WRITE,
data_to_send, ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_etc_cond2(struct s6e8ax0 *lcd)
{
struct mipi_dsim_master_ops *ops = lcd_to_master_ops(lcd);
static const unsigned char data_to_send[] = {
0xb6, 0x0c, 0x02, 0x03, 0x32, 0xff, 0x44, 0x44, 0xc0,
0x00
};
ops->cmd_write(lcd_to_master(lcd), MIPI_DSI_DCS_LONG_WRITE,
data_to_send, ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_etc_cond3(struct s6e8ax0 *lcd)
{
struct mipi_dsim_master_ops *ops = lcd_to_master_ops(lcd);
static const unsigned char data_to_send[] = {
0xe1, 0x10, 0x1c, 0x17, 0x08, 0x1d
};
ops->cmd_write(lcd_to_master(lcd), MIPI_DSI_DCS_LONG_WRITE,
data_to_send, ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_etc_cond4(struct s6e8ax0 *lcd)
{
struct mipi_dsim_master_ops *ops = lcd_to_master_ops(lcd);
static const unsigned char data_to_send[] = {
0xe2, 0xed, 0x07, 0xc3, 0x13, 0x0d, 0x03
};
ops->cmd_write(lcd_to_master(lcd), MIPI_DSI_DCS_LONG_WRITE,
data_to_send, ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_etc_cond5(struct s6e8ax0 *lcd)
{
struct mipi_dsim_master_ops *ops = lcd_to_master_ops(lcd);
static const unsigned char data_to_send[] = {
0xf4, 0xcf, 0x0a, 0x12, 0x10, 0x19, 0x33, 0x02
};
ops->cmd_write(lcd_to_master(lcd), MIPI_DSI_DCS_LONG_WRITE,
data_to_send, ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_etc_cond6(struct s6e8ax0 *lcd)
{
struct mipi_dsim_master_ops *ops = lcd_to_master_ops(lcd);
static const unsigned char data_to_send[] = {
0xe3, 0x40
};
ops->cmd_write(lcd_to_master(lcd),
MIPI_DSI_DCS_SHORT_WRITE_PARAM,
data_to_send, ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_etc_cond7(struct s6e8ax0 *lcd)
{
struct mipi_dsim_master_ops *ops = lcd_to_master_ops(lcd);
static const unsigned char data_to_send[] = {
0xe4, 0x00, 0x00, 0x14, 0x80, 0x00, 0x00, 0x00
};
ops->cmd_write(lcd_to_master(lcd), MIPI_DSI_DCS_LONG_WRITE,
data_to_send, ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_elvss_set(struct s6e8ax0 *lcd)
{
struct mipi_dsim_master_ops *ops = lcd_to_master_ops(lcd);
static const unsigned char data_to_send[] = {
0xb1, 0x04, 0x00
};
ops->cmd_write(lcd_to_master(lcd), MIPI_DSI_DCS_LONG_WRITE,
data_to_send, ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_elvss_nvm_set(struct s6e8ax0 *lcd)
{
struct mipi_dsim_master_ops *ops = lcd_to_master_ops(lcd);
static const unsigned char data_to_send[] = {
0xd9, 0x5c, 0x20, 0x0c, 0x0f, 0x41, 0x00, 0x10, 0x11,
0x12, 0xd1, 0x00, 0x00, 0x00, 0x00, 0x80, 0xcb, 0xed,
0x64, 0xaf
};
ops->cmd_write(lcd_to_master(lcd), MIPI_DSI_DCS_LONG_WRITE,
data_to_send, ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_sleep_in(struct s6e8ax0 *lcd)
{
struct mipi_dsim_master_ops *ops = lcd_to_master_ops(lcd);
static const unsigned char data_to_send[] = {
0x10, 0x00
};
ops->cmd_write(lcd_to_master(lcd),
MIPI_DSI_DCS_SHORT_WRITE,
data_to_send, ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_sleep_out(struct s6e8ax0 *lcd)
{
struct mipi_dsim_master_ops *ops = lcd_to_master_ops(lcd);
static const unsigned char data_to_send[] = {
0x11, 0x00
};
ops->cmd_write(lcd_to_master(lcd),
MIPI_DSI_DCS_SHORT_WRITE,
data_to_send, ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_display_on(struct s6e8ax0 *lcd)
{
struct mipi_dsim_master_ops *ops = lcd_to_master_ops(lcd);
static const unsigned char data_to_send[] = {
0x29, 0x00
};
ops->cmd_write(lcd_to_master(lcd),
MIPI_DSI_DCS_SHORT_WRITE,
data_to_send, ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_display_off(struct s6e8ax0 *lcd)
{
struct mipi_dsim_master_ops *ops = lcd_to_master_ops(lcd);
static const unsigned char data_to_send[] = {
0x28, 0x00
};
ops->cmd_write(lcd_to_master(lcd),
MIPI_DSI_DCS_SHORT_WRITE,
data_to_send, ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_apply_level2_key(struct s6e8ax0 *lcd)
{
struct mipi_dsim_master_ops *ops = lcd_to_master_ops(lcd);
static const unsigned char data_to_send[] = {
0xf0, 0x5a, 0x5a
};
ops->cmd_write(lcd_to_master(lcd), MIPI_DSI_DCS_LONG_WRITE,
data_to_send, ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_acl_on(struct s6e8ax0 *lcd)
{
struct mipi_dsim_master_ops *ops = lcd_to_master_ops(lcd);
static const unsigned char data_to_send[] = {
0xc0, 0x01
};
ops->cmd_write(lcd_to_master(lcd),
MIPI_DSI_DCS_SHORT_WRITE,
data_to_send, ARRAY_SIZE(data_to_send));
}
static void s6e8ax0_acl_off(struct s6e8ax0 *lcd)
{
struct mipi_dsim_master_ops *ops = lcd_to_master_ops(lcd);
static const unsigned char data_to_send[] = {
0xc0, 0x00
};
ops->cmd_write(lcd_to_master(lcd),
MIPI_DSI_DCS_SHORT_WRITE,
data_to_send, ARRAY_SIZE(data_to_send));
}
/* Full white 50% reducing setting */
static void s6e8ax0_acl_ctrl_set(struct s6e8ax0 *lcd)
{
struct mipi_dsim_master_ops *ops = lcd_to_master_ops(lcd);
/* Full white 50% reducing setting */
static const unsigned char cutoff_50[] = {
0xc1, 0x47, 0x53, 0x13, 0x53, 0x00, 0x00, 0x02, 0xcf,
0x00, 0x00, 0x04, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
0x01, 0x08, 0x0f, 0x16, 0x1d, 0x24, 0x2a, 0x31, 0x38,
0x3f, 0x46
};
/* Full white 45% reducing setting */
static const unsigned char cutoff_45[] = {
0xc1, 0x47, 0x53, 0x13, 0x53, 0x00, 0x00, 0x02, 0xcf,
0x00, 0x00, 0x04, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
0x01, 0x07, 0x0d, 0x13, 0x19, 0x1f, 0x25, 0x2b, 0x31,
0x37, 0x3d
};
/* Full white 40% reducing setting */
static const unsigned char cutoff_40[] = {
0xc1, 0x47, 0x53, 0x13, 0x53, 0x00, 0x00, 0x02, 0xcf,
0x00, 0x00, 0x04, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
0x01, 0x06, 0x0c, 0x11, 0x16, 0x1c, 0x21, 0x26, 0x2b,
0x31, 0x36
};
if (lcd->acl_enable) {
if (lcd->cur_acl == 0) {
if (lcd->gamma == 0 || lcd->gamma == 1) {
s6e8ax0_acl_off(lcd);
dev_dbg(&lcd->ld->dev,
"cur_acl=%d\n", lcd->cur_acl);
} else
s6e8ax0_acl_on(lcd);
}
switch (lcd->gamma) {
case 0: /* 30cd */
s6e8ax0_acl_off(lcd);
lcd->cur_acl = 0;
break;
case 1 ... 3: /* 50cd ~ 90cd */
ops->cmd_write(lcd_to_master(lcd),
MIPI_DSI_DCS_LONG_WRITE,
cutoff_40,
ARRAY_SIZE(cutoff_40));
lcd->cur_acl = 40;
break;
case 4 ... 7: /* 120cd ~ 210cd */
ops->cmd_write(lcd_to_master(lcd),
MIPI_DSI_DCS_LONG_WRITE,
cutoff_45,
ARRAY_SIZE(cutoff_45));
lcd->cur_acl = 45;
break;
case 8 ... 10: /* 220cd ~ 300cd */
ops->cmd_write(lcd_to_master(lcd),
MIPI_DSI_DCS_LONG_WRITE,
cutoff_50,
ARRAY_SIZE(cutoff_50));
lcd->cur_acl = 50;
break;
default:
break;
}
} else {
s6e8ax0_acl_off(lcd);
lcd->cur_acl = 0;
dev_dbg(&lcd->ld->dev, "cur_acl = %d\n", lcd->cur_acl);
}
}
static void s6e8ax0_read_id(struct s6e8ax0 *lcd, u8 *mtp_id)
{
unsigned int ret;
unsigned int addr = 0xd1; /* MTP ID */
struct mipi_dsim_master_ops *ops = lcd_to_master_ops(lcd);
ret = ops->cmd_read(lcd_to_master(lcd),
MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM,
addr, 3, mtp_id);
}
static int s6e8ax0_panel_init(struct s6e8ax0 *lcd)
{
s6e8ax0_apply_level2_key(lcd);
s6e8ax0_sleep_out(lcd);
msleep(1);
s6e8ax0_panel_cond(lcd);
s6e8ax0_display_cond(lcd);
s6e8ax0_gamma_cond(lcd);
s6e8ax0_gamma_update(lcd);
s6e8ax0_etc_cond1(lcd);
s6e8ax0_etc_cond2(lcd);
s6e8ax0_etc_cond3(lcd);
s6e8ax0_etc_cond4(lcd);
s6e8ax0_etc_cond5(lcd);
s6e8ax0_etc_cond6(lcd);
s6e8ax0_etc_cond7(lcd);
s6e8ax0_elvss_nvm_set(lcd);
s6e8ax0_elvss_set(lcd);
s6e8ax0_acl_ctrl_set(lcd);
s6e8ax0_acl_on(lcd);
/* if ID3 value is not 33h, branch private elvss mode */
msleep(lcd->ddi_pd->power_on_delay);
return 0;
}
static int s6e8ax0_update_gamma_ctrl(struct s6e8ax0 *lcd, int brightness)
{
struct mipi_dsim_master_ops *ops = lcd_to_master_ops(lcd);
ops->cmd_write(lcd_to_master(lcd), MIPI_DSI_DCS_LONG_WRITE,
s6e8ax0_22_gamma_table[brightness],
ARRAY_SIZE(s6e8ax0_22_gamma_table));
/* update gamma table. */
s6e8ax0_gamma_update(lcd);
lcd->gamma = brightness;
return 0;
}
static int s6e8ax0_gamma_ctrl(struct s6e8ax0 *lcd, int gamma)
{
s6e8ax0_update_gamma_ctrl(lcd, gamma);
return 0;
}
static int s6e8ax0_set_power(struct lcd_device *ld, int power)
{
struct s6e8ax0 *lcd = lcd_get_data(ld);
struct mipi_dsim_master_ops *ops = lcd_to_master_ops(lcd);
int ret = 0;
if (power != FB_BLANK_UNBLANK && power != FB_BLANK_POWERDOWN &&
power != FB_BLANK_NORMAL) {
dev_err(lcd->dev, "power value should be 0, 1 or 4.\n");
return -EINVAL;
}
if ((power == FB_BLANK_UNBLANK) && ops->set_blank_mode) {
/* LCD power on */
if ((POWER_IS_ON(power) && POWER_IS_OFF(lcd->power))
|| (POWER_IS_ON(power) && POWER_IS_NRM(lcd->power))) {
ret = ops->set_blank_mode(lcd_to_master(lcd), power);
if (!ret && lcd->power != power)
lcd->power = power;
}
} else if ((power == FB_BLANK_POWERDOWN) && ops->set_early_blank_mode) {
/* LCD power off */
if ((POWER_IS_OFF(power) && POWER_IS_ON(lcd->power)) ||
(POWER_IS_ON(lcd->power) && POWER_IS_NRM(power))) {
ret = ops->set_early_blank_mode(lcd_to_master(lcd),
power);
if (!ret && lcd->power != power)
lcd->power = power;
}
}
return ret;
}
static int s6e8ax0_get_power(struct lcd_device *ld)
{
struct s6e8ax0 *lcd = lcd_get_data(ld);
return lcd->power;
}
static int s6e8ax0_get_brightness(struct backlight_device *bd)
{
return bd->props.brightness;
}
static int s6e8ax0_set_brightness(struct backlight_device *bd)
{
int ret = 0, brightness = bd->props.brightness;
struct s6e8ax0 *lcd = bl_get_data(bd);
if (brightness < MIN_BRIGHTNESS ||
brightness > bd->props.max_brightness) {
dev_err(lcd->dev, "lcd brightness should be %d to %d.\n",
MIN_BRIGHTNESS, MAX_BRIGHTNESS);
return -EINVAL;
}
ret = s6e8ax0_gamma_ctrl(lcd, brightness);
if (ret) {
dev_err(&bd->dev, "lcd brightness setting failed.\n");
return -EIO;
}
return ret;
}
static struct lcd_ops s6e8ax0_lcd_ops = {
.set_power = s6e8ax0_set_power,
.get_power = s6e8ax0_get_power,
};
static const struct backlight_ops s6e8ax0_backlight_ops = {
.get_brightness = s6e8ax0_get_brightness,
.update_status = s6e8ax0_set_brightness,
};
static void s6e8ax0_power_on(struct mipi_dsim_lcd_device *dsim_dev, int power)
{
struct s6e8ax0 *lcd = dev_get_drvdata(&dsim_dev->dev);
msleep(lcd->ddi_pd->power_on_delay);
/* lcd power on */
if (power)
s6e8ax0_regulator_enable(lcd);
else
s6e8ax0_regulator_disable(lcd);
msleep(lcd->ddi_pd->reset_delay);
/* lcd reset */
if (lcd->ddi_pd->reset)
lcd->ddi_pd->reset(lcd->ld);
msleep(5);
}
static void s6e8ax0_set_sequence(struct mipi_dsim_lcd_device *dsim_dev)
{
struct s6e8ax0 *lcd = dev_get_drvdata(&dsim_dev->dev);
s6e8ax0_panel_init(lcd);
s6e8ax0_display_on(lcd);
lcd->power = FB_BLANK_UNBLANK;
}
static int s6e8ax0_probe(struct mipi_dsim_lcd_device *dsim_dev)
{
struct s6e8ax0 *lcd;
int ret;
u8 mtp_id[3] = {0, };
lcd = kzalloc(sizeof(struct s6e8ax0), GFP_KERNEL);
if (!lcd) {
dev_err(&dsim_dev->dev, "failed to allocate s6e8ax0 structure.\n");
return -ENOMEM;
}
lcd->dsim_dev = dsim_dev;
lcd->ddi_pd = (struct lcd_platform_data *)dsim_dev->platform_data;
lcd->dev = &dsim_dev->dev;
mutex_init(&lcd->lock);
ret = regulator_bulk_get(lcd->dev, ARRAY_SIZE(supplies), supplies);
if (ret) {
dev_err(lcd->dev, "Failed to get regulators: %d\n", ret);
goto err_lcd_register;
}
lcd->ld = lcd_device_register("s6e8ax0", lcd->dev, lcd,
&s6e8ax0_lcd_ops);
if (IS_ERR(lcd->ld)) {
dev_err(lcd->dev, "failed to register lcd ops.\n");
ret = PTR_ERR(lcd->ld);
goto err_lcd_register;
}
lcd->bd = backlight_device_register("s6e8ax0-bl", lcd->dev, lcd,
&s6e8ax0_backlight_ops, NULL);
if (IS_ERR(lcd->bd)) {
dev_err(lcd->dev, "failed to register backlight ops.\n");
ret = PTR_ERR(lcd->bd);
goto err_backlight_register;
}
lcd->bd->props.max_brightness = MAX_BRIGHTNESS;
lcd->bd->props.brightness = MAX_BRIGHTNESS;
s6e8ax0_read_id(lcd, mtp_id);
if (mtp_id[0] == 0x00)
dev_err(lcd->dev, "read id failed\n");
dev_info(lcd->dev, "Read ID : %x, %x, %x\n",
mtp_id[0], mtp_id[1], mtp_id[2]);
if (mtp_id[2] == 0x33)
dev_info(lcd->dev,
"ID-3 is 0xff does not support dynamic elvss\n");
else
dev_info(lcd->dev,
"ID-3 is 0x%x support dynamic elvss\n", mtp_id[2]);
lcd->acl_enable = 1;
lcd->cur_acl = 0;
dev_set_drvdata(&dsim_dev->dev, lcd);
dev_dbg(lcd->dev, "probed s6e8ax0 panel driver.\n");
return 0;
err_backlight_register:
lcd_device_unregister(lcd->ld);
err_lcd_register:
regulator_bulk_free(ARRAY_SIZE(supplies), supplies);
kfree(lcd);
return ret;
}
#ifdef CONFIG_PM
static int s6e8ax0_suspend(struct mipi_dsim_lcd_device *dsim_dev)
{
struct s6e8ax0 *lcd = dev_get_drvdata(&dsim_dev->dev);
s6e8ax0_sleep_in(lcd);
msleep(lcd->ddi_pd->power_off_delay);
s6e8ax0_display_off(lcd);
s6e8ax0_regulator_disable(lcd);
return 0;
}
static int s6e8ax0_resume(struct mipi_dsim_lcd_device *dsim_dev)
{
struct s6e8ax0 *lcd = dev_get_drvdata(&dsim_dev->dev);
s6e8ax0_sleep_out(lcd);
msleep(lcd->ddi_pd->power_on_delay);
s6e8ax0_regulator_enable(lcd);
s6e8ax0_set_sequence(dsim_dev);
return 0;
}
#else
#define s6e8ax0_suspend NULL
#define s6e8ax0_resume NULL
#endif
static struct mipi_dsim_lcd_driver s6e8ax0_dsim_ddi_driver = {
.name = "s6e8ax0",
.id = -1,
.power_on = s6e8ax0_power_on,
.set_sequence = s6e8ax0_set_sequence,
.probe = s6e8ax0_probe,
.suspend = s6e8ax0_suspend,
.resume = s6e8ax0_resume,
};
static int s6e8ax0_init(void)
{
exynos_mipi_dsi_register_lcd_driver(&s6e8ax0_dsim_ddi_driver);
return 0;
}
static void s6e8ax0_exit(void)
{
return;
}
module_init(s6e8ax0_init);
module_exit(s6e8ax0_exit);
MODULE_AUTHOR("Donghwa Lee <dh09.lee@samsung.com>");
MODULE_AUTHOR("Inki Dae <inki.dae@samsung.com>");
MODULE_DESCRIPTION("MIPI-DSI based s6e8ax0 AMOLED LCD Panel Driver");
MODULE_LICENSE("GPL");

21
drivers/video/exynos/s6e8ax0.h Normal file
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/* linux/drivers/video/backlight/s6e8ax0.h
*
* MIPI-DSI based s6e8ax0 AMOLED LCD Panel definitions.
*
* Copyright (c) 2011 Samsung Electronics
*
* Inki Dae, <inki.dae@samsung.com>
* Donghwa Lee <dh09.lee@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _S6E8AX0_H
#define _S6E8AX0_H
extern void s6e8ax0_init(void);
#endif

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drivers/video/i740_reg.h Normal file
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/**************************************************************************
Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
All Rights Reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sub license, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial portions
of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/*
* Authors:
* Kevin E. Martin <kevin@precisioninsight.com>
*/
/* I/O register offsets */
#define SRX VGA_SEQ_I
#define GRX VGA_GFX_I
#define ARX VGA_ATT_IW
#define XRX 0x3D6
#define MRX 0x3D2
/* VGA Color Palette Registers */
#define DACMASK 0x3C6
#define DACSTATE 0x3C7
#define DACRX 0x3C7
#define DACWX 0x3C8
#define DACDATA 0x3C9
/* CRT Controller Registers (CRX) */
#define START_ADDR_HI 0x0C
#define START_ADDR_LO 0x0D
#define VERT_SYNC_END 0x11
#define EXT_VERT_TOTAL 0x30
#define EXT_VERT_DISPLAY 0x31
#define EXT_VERT_SYNC_START 0x32
#define EXT_VERT_BLANK_START 0x33
#define EXT_HORIZ_TOTAL 0x35
#define EXT_HORIZ_BLANK 0x39
#define EXT_START_ADDR 0x40
#define EXT_START_ADDR_ENABLE 0x80
#define EXT_OFFSET 0x41
#define EXT_START_ADDR_HI 0x42
#define INTERLACE_CNTL 0x70
#define INTERLACE_ENABLE 0x80
#define INTERLACE_DISABLE 0x00
/* Miscellaneous Output Register */
#define MSR_R 0x3CC
#define MSR_W 0x3C2
#define IO_ADDR_SELECT 0x01
#define MDA_BASE 0x3B0
#define CGA_BASE 0x3D0
/* System Configuration Extension Registers (XRX) */
#define IO_CTNL 0x09
#define EXTENDED_ATTR_CNTL 0x02
#define EXTENDED_CRTC_CNTL 0x01
#define ADDRESS_MAPPING 0x0A
#define PACKED_MODE_ENABLE 0x04
#define LINEAR_MODE_ENABLE 0x02
#define PAGE_MAPPING_ENABLE 0x01
#define BITBLT_CNTL 0x20
#define COLEXP_MODE 0x30
#define COLEXP_8BPP 0x00
#define COLEXP_16BPP 0x10
#define COLEXP_24BPP 0x20
#define COLEXP_RESERVED 0x30
#define CHIP_RESET 0x02
#define BITBLT_STATUS 0x01
#define DISPLAY_CNTL 0x40
#define VGA_WRAP_MODE 0x02
#define VGA_WRAP_AT_256KB 0x00
#define VGA_NO_WRAP 0x02
#define GUI_MODE 0x01
#define STANDARD_VGA_MODE 0x00
#define HIRES_MODE 0x01
#define DRAM_ROW_TYPE 0x50
#define DRAM_ROW_0 0x07
#define DRAM_ROW_0_SDRAM 0x00
#define DRAM_ROW_0_EMPTY 0x07
#define DRAM_ROW_1 0x38
#define DRAM_ROW_1_SDRAM 0x00
#define DRAM_ROW_1_EMPTY 0x38
#define DRAM_ROW_CNTL_LO 0x51
#define DRAM_CAS_LATENCY 0x10
#define DRAM_RAS_TIMING 0x08
#define DRAM_RAS_PRECHARGE 0x04
#define DRAM_ROW_CNTL_HI 0x52
#define DRAM_EXT_CNTL 0x53
#define DRAM_REFRESH_RATE 0x03
#define DRAM_REFRESH_DISABLE 0x00
#define DRAM_REFRESH_60HZ 0x01
#define DRAM_REFRESH_FAST_TEST 0x02
#define DRAM_REFRESH_RESERVED 0x03
#define DRAM_TIMING 0x54
#define DRAM_ROW_BNDRY_0 0x55
#define DRAM_ROW_BNDRY_1 0x56
#define DPMS_SYNC_SELECT 0x61
#define VSYNC_CNTL 0x08
#define VSYNC_ON 0x00
#define VSYNC_OFF 0x08
#define HSYNC_CNTL 0x02
#define HSYNC_ON 0x00
#define HSYNC_OFF 0x02
#define PIXPIPE_CONFIG_0 0x80
#define DAC_8_BIT 0x80
#define DAC_6_BIT 0x00
#define HW_CURSOR_ENABLE 0x10
#define EXTENDED_PALETTE 0x01
#define PIXPIPE_CONFIG_1 0x81
#define DISPLAY_COLOR_MODE 0x0F
#define DISPLAY_VGA_MODE 0x00
#define DISPLAY_8BPP_MODE 0x02
#define DISPLAY_15BPP_MODE 0x04
#define DISPLAY_16BPP_MODE 0x05
#define DISPLAY_24BPP_MODE 0x06
#define DISPLAY_32BPP_MODE 0x07
#define PIXPIPE_CONFIG_2 0x82
#define DISPLAY_GAMMA_ENABLE 0x08
#define DISPLAY_GAMMA_DISABLE 0x00
#define OVERLAY_GAMMA_ENABLE 0x04
#define OVERLAY_GAMMA_DISABLE 0x00
#define CURSOR_CONTROL 0xA0
#define CURSOR_ORIGIN_SCREEN 0x00
#define CURSOR_ORIGIN_DISPLAY 0x10
#define CURSOR_MODE 0x07
#define CURSOR_MODE_DISABLE 0x00
#define CURSOR_MODE_32_4C_AX 0x01
#define CURSOR_MODE_128_2C 0x02
#define CURSOR_MODE_128_1C 0x03
#define CURSOR_MODE_64_3C 0x04
#define CURSOR_MODE_64_4C_AX 0x05
#define CURSOR_MODE_64_4C 0x06
#define CURSOR_MODE_RESERVED 0x07
#define CURSOR_BASEADDR_LO 0xA2
#define CURSOR_BASEADDR_HI 0xA3
#define CURSOR_X_LO 0xA4
#define CURSOR_X_HI 0xA5
#define CURSOR_X_POS 0x00
#define CURSOR_X_NEG 0x80
#define CURSOR_Y_LO 0xA6
#define CURSOR_Y_HI 0xA7
#define CURSOR_Y_POS 0x00
#define CURSOR_Y_NEG 0x80
#define VCLK2_VCO_M 0xC8
#define VCLK2_VCO_N 0xC9
#define VCLK2_VCO_MN_MSBS 0xCA
#define VCO_N_MSBS 0x30
#define VCO_M_MSBS 0x03
#define VCLK2_VCO_DIV_SEL 0xCB
#define POST_DIV_SELECT 0x70
#define POST_DIV_1 0x00
#define POST_DIV_2 0x10
#define POST_DIV_4 0x20
#define POST_DIV_8 0x30
#define POST_DIV_16 0x40
#define POST_DIV_32 0x50
#define VCO_LOOP_DIV_BY_4M 0x00
#define VCO_LOOP_DIV_BY_16M 0x04
#define REF_CLK_DIV_BY_5 0x02
#define REF_DIV_4 0x00
#define REF_DIV_1 0x01
#define PLL_CNTL 0xCE
#define PLL_MEMCLK_SEL 0x03
#define PLL_MEMCLK__66667KHZ 0x00
#define PLL_MEMCLK__75000KHZ 0x01
#define PLL_MEMCLK__88889KHZ 0x02
#define PLL_MEMCLK_100000KHZ 0x03
/* Multimedia Extension Registers (MRX) */
#define ACQ_CNTL_1 0x02
#define ACQ_CNTL_2 0x03
#define FRAME_CAP_MODE 0x01
#define CONT_CAP_MODE 0x00
#define SINGLE_CAP_MODE 0x01
#define ACQ_CNTL_3 0x04
#define COL_KEY_CNTL_1 0x3C
#define BLANK_DISP_OVERLAY 0x20
/* FIFOs */
#define LP_FIFO 0x1000
#define HP_FIFO 0x2000
#define INSTPNT 0x3040
#define LP_FIFO_COUNT 0x3040
#define HP_FIFO_COUNT 0x3041
/* FIFO Commands */
#define CLIENT 0xE0000000
#define CLIENT_2D 0x60000000
/* Command Parser Mode Register */
#define COMPARS 0x3038
#define TWO_D_INST_DISABLE 0x08
#define THREE_D_INST_DISABLE 0x04
#define STATE_VAR_UPDATE_DISABLE 0x02
#define PAL_STIP_DISABLE 0x01
/* Interrupt Control Registers */
#define IER 0x3030
#define IIR 0x3032
#define IMR 0x3034
#define ISR 0x3036
#define VMIINTB_EVENT 0x2000
#define GPIO4_INT 0x1000
#define DISP_FLIP_EVENT 0x0800
#define DVD_PORT_DMA 0x0400
#define DISP_VBLANK 0x0200
#define FIFO_EMPTY_DMA_DONE 0x0100
#define INST_PARSER_ERROR 0x0080
#define USER_DEFINED 0x0040
#define BREAKPOINT 0x0020
#define DISP_HORIZ_COUNT 0x0010
#define DISP_VSYNC 0x0008
#define CAPTURE_HORIZ_COUNT 0x0004
#define CAPTURE_VSYNC 0x0002
#define THREE_D_PIPE_FLUSHED 0x0001
/* FIFO Watermark and Burst Length Control Register */
#define FWATER_BLC 0x00006000
#define LMI_BURST_LENGTH 0x7F000000
#define LMI_FIFO_WATERMARK 0x003F0000
#define AGP_BURST_LENGTH 0x00007F00
#define AGP_FIFO_WATERMARK 0x0000003F
/* BitBLT Registers */
#define SRC_DST_PITCH 0x00040000
#define DST_PITCH 0x1FFF0000
#define SRC_PITCH 0x00001FFF
#define COLEXP_BG_COLOR 0x00040004
#define COLEXP_FG_COLOR 0x00040008
#define MONO_SRC_CNTL 0x0004000C
#define MONO_USE_COLEXP 0x00000000
#define MONO_USE_SRCEXP 0x08000000
#define MONO_DATA_ALIGN 0x07000000
#define MONO_BIT_ALIGN 0x01000000
#define MONO_BYTE_ALIGN 0x02000000
#define MONO_WORD_ALIGN 0x03000000
#define MONO_DWORD_ALIGN 0x04000000
#define MONO_QWORD_ALIGN 0x05000000
#define MONO_SRC_INIT_DSCRD 0x003F0000
#define MONO_SRC_RIGHT_CLIP 0x00003F00
#define MONO_SRC_LEFT_CLIP 0x0000003F
#define BITBLT_CONTROL 0x00040010
#define BLTR_STATUS 0x80000000
#define DYN_DEPTH 0x03000000
#define DYN_DEPTH_8BPP 0x00000000
#define DYN_DEPTH_16BPP 0x01000000
#define DYN_DEPTH_24BPP 0x02000000
#define DYN_DEPTH_32BPP 0x03000000 /* Unimplemented on the i740 */
#define DYN_DEPTH_ENABLE 0x00800000
#define PAT_VERT_ALIGN 0x00700000
#define SOLID_PAT_SELECT 0x00080000
#define PAT_IS_IN_COLOR 0x00000000
#define PAT_IS_MONO 0x00040000
#define MONO_PAT_TRANSP 0x00020000
#define COLOR_TRANSP_ROP 0x00000000
#define COLOR_TRANSP_DST 0x00008000
#define COLOR_TRANSP_EQ 0x00000000
#define COLOR_TRANSP_NOT_EQ 0x00010000
#define COLOR_TRANSP_ENABLE 0x00004000
#define MONO_SRC_TRANSP 0x00002000
#define SRC_IS_IN_COLOR 0x00000000
#define SRC_IS_MONO 0x00001000
#define SRC_USE_SRC_ADDR 0x00000000
#define SRC_USE_BLTDATA 0x00000400
#define BLT_TOP_TO_BOT 0x00000000
#define BLT_BOT_TO_TOP 0x00000200
#define BLT_LEFT_TO_RIGHT 0x00000000
#define BLT_RIGHT_TO_LEFT 0x00000100
#define BLT_ROP 0x000000FF
#define BLT_PAT_ADDR 0x00040014
#define BLT_SRC_ADDR 0x00040018
#define BLT_DST_ADDR 0x0004001C
#define BLT_DST_H_W 0x00040020
#define BLT_DST_HEIGHT 0x1FFF0000
#define BLT_DST_WIDTH 0x00001FFF
#define SRCEXP_BG_COLOR 0x00040024
#define SRCEXP_FG_COLOR 0x00040028
#define BLTDATA 0x00050000

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drivers/video/i740fb.c Normal file
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7
drivers/video/msm/mddi_client_nt35399.c
View File

@ -155,14 +155,10 @@ static int setup_vsync(struct panel_info *panel, int init)
ret = 0;
goto uninit;
}
ret = gpio_request(gpio, "vsync");
ret = gpio_request_one(gpio, GPIOF_IN, "vsync");
if (ret)
goto err_request_gpio_failed;
ret = gpio_direction_input(gpio);
if (ret)
goto err_gpio_direction_input_failed;
ret = irq = gpio_to_irq(gpio);
if (ret < 0)
goto err_get_irq_num_failed;
@ -180,7 +176,6 @@ uninit:
free_irq(gpio_to_irq(gpio), panel->client_data);
err_request_irq_failed:
err_get_irq_num_failed:
err_gpio_direction_input_failed:
gpio_free(gpio);
err_request_gpio_failed:
return ret;

7
drivers/video/msm/mddi_client_toshiba.c
View File

@ -186,14 +186,10 @@ static int setup_vsync(struct panel_info *panel,
ret = 0;
goto uninit;
}
ret = gpio_request(gpio, "vsync");
ret = gpio_request_one(gpio, GPIOF_IN, "vsync");
if (ret)
goto err_request_gpio_failed;
ret = gpio_direction_input(gpio);
if (ret)
goto err_gpio_direction_input_failed;
ret = irq = gpio_to_irq(gpio);
if (ret < 0)
goto err_get_irq_num_failed;
@ -210,7 +206,6 @@ uninit:
free_irq(gpio_to_irq(gpio), panel);
err_request_irq_failed:
err_get_irq_num_failed:
err_gpio_direction_input_failed:
gpio_free(gpio);
err_request_gpio_failed:
return ret;

16
drivers/video/omap/Kconfig
View File

@ -1,11 +1,10 @@
config FB_OMAP
tristate "OMAP frame buffer support (EXPERIMENTAL)"
depends on FB && (OMAP2_DSS = "n")
depends on ARCH_OMAP1 || ARCH_OMAP2 || ARCH_OMAP3
depends on FB
depends on ARCH_OMAP1
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
select TWL4030_CORE if MACH_OMAP_2430SDP
help
Frame buffer driver for OMAP based boards.
@ -23,13 +22,6 @@ config FB_OMAP_LCDC_HWA742
Say Y here if you want to have support for the external
Epson HWA742 LCD controller.
config FB_OMAP_LCDC_BLIZZARD
bool "Epson Blizzard LCD controller support"
depends on FB_OMAP && FB_OMAP_LCDC_EXTERNAL
help
Say Y here if you want to have support for the external
Epson Blizzard LCD controller.
config FB_OMAP_MANUAL_UPDATE
bool "Default to manual update mode"
depends on FB_OMAP && FB_OMAP_LCDC_EXTERNAL
@ -49,7 +41,7 @@ config FB_OMAP_LCD_MIPID
config FB_OMAP_BOOTLOADER_INIT
bool "Check bootloader initialization"
depends on FB_OMAP || FB_OMAP2
depends on FB_OMAP
help
Say Y here if you want to enable checking if the bootloader has
already initialized the display controller. In this case the
@ -68,7 +60,7 @@ config FB_OMAP_CONSISTENT_DMA_SIZE
config FB_OMAP_DMA_TUNE
bool "Set DMA SDRAM access priority high"
depends on FB_OMAP && ARCH_OMAP1
depends on FB_OMAP
help
On systems in which video memory is in system memory
(SDRAM) this will speed up graphics DMA operations.

12
drivers/video/omap/Makefile
View File

@ -1,20 +1,14 @@
#
# Makefile for the new OMAP framebuffer device driver
# Makefile for the OMAP1 framebuffer device driver
#
obj-$(CONFIG_FB_OMAP) += omapfb.o
objs-yy := omapfb_main.o
objs-yy := omapfb_main.o lcdc.o
objs-y$(CONFIG_ARCH_OMAP1) += lcdc.o
objs-y$(CONFIG_ARCH_OMAP2) += dispc.o
objs-y$(CONFIG_ARCH_OMAP3) += dispc.o
objs-$(CONFIG_ARCH_OMAP1)$(CONFIG_FB_OMAP_LCDC_EXTERNAL) += sossi.o
objs-$(CONFIG_ARCH_OMAP2)$(CONFIG_FB_OMAP_LCDC_EXTERNAL) += rfbi.o
objs-y$(CONFIG_FB_OMAP_LCDC_EXTERNAL) += sossi.o
objs-y$(CONFIG_FB_OMAP_LCDC_HWA742) += hwa742.o
objs-y$(CONFIG_FB_OMAP_LCDC_BLIZZARD) += blizzard.o
objs-y$(CONFIG_MACH_AMS_DELTA) += lcd_ams_delta.o
objs-y$(CONFIG_MACH_OMAP_H3) += lcd_h3.o

1648
drivers/video/omap/blizzard.c
View File

File diff suppressed because it is too large Load Diff

1547
drivers/video/omap/dispc.c
View File

File diff suppressed because it is too large Load Diff

46
drivers/video/omap/dispc.h
View File

@ -1,46 +0,0 @@
#ifndef _DISPC_H
#define _DISPC_H
#include <linux/interrupt.h>
#define DISPC_PLANE_GFX 0
#define DISPC_PLANE_VID1 1
#define DISPC_PLANE_VID2 2
#define DISPC_RGB_1_BPP 0x00
#define DISPC_RGB_2_BPP 0x01
#define DISPC_RGB_4_BPP 0x02
#define DISPC_RGB_8_BPP 0x03
#define DISPC_RGB_12_BPP 0x04
#define DISPC_RGB_16_BPP 0x06
#define DISPC_RGB_24_BPP 0x08
#define DISPC_RGB_24_BPP_UNPACK_32 0x09
#define DISPC_YUV2_422 0x0a
#define DISPC_UYVY_422 0x0b
#define DISPC_BURST_4x32 0
#define DISPC_BURST_8x32 1
#define DISPC_BURST_16x32 2
#define DISPC_LOAD_CLUT_AND_FRAME 0x00
#define DISPC_LOAD_CLUT_ONLY 0x01
#define DISPC_LOAD_FRAME_ONLY 0x02
#define DISPC_LOAD_CLUT_ONCE_FRAME 0x03
#define DISPC_TFT_DATA_LINES_12 0
#define DISPC_TFT_DATA_LINES_16 1
#define DISPC_TFT_DATA_LINES_18 2
#define DISPC_TFT_DATA_LINES_24 3
extern void omap_dispc_set_lcd_size(int width, int height);
extern void omap_dispc_enable_lcd_out(int enable);
extern void omap_dispc_enable_digit_out(int enable);
extern int omap_dispc_request_irq(unsigned long irq_mask,
void (*callback)(void *data), void *data);
extern void omap_dispc_free_irq(unsigned long irq_mask,
void (*callback)(void *data), void *data);
extern const struct lcd_ctrl omap2_int_ctrl;
#endif

21
drivers/video/omap/hwa742.c
View File

@ -28,7 +28,6 @@
#include <linux/interrupt.h>
#include <plat/dma.h>
#include <plat/hwa742.h>
#include "omapfb.h"
#define HWA742_REV_CODE_REG 0x0
@ -942,7 +941,6 @@ static int hwa742_init(struct omapfb_device *fbdev, int ext_mode,
unsigned long sys_clk, pix_clk;
int extif_mem_div;
struct omapfb_platform_data *omapfb_conf;
struct hwa742_platform_data *ctrl_conf;
BUG_ON(!fbdev->ext_if || !fbdev->int_ctrl);
@ -951,13 +949,6 @@ static int hwa742_init(struct omapfb_device *fbdev, int ext_mode,
hwa742.int_ctrl = fbdev->int_ctrl;
omapfb_conf = fbdev->dev->platform_data;
ctrl_conf = omapfb_conf->ctrl_platform_data;
if (ctrl_conf == NULL) {
dev_err(fbdev->dev, "HWA742: missing platform data\n");
r = -ENOENT;
goto err1;
}
hwa742.sys_ck = clk_get(NULL, "hwa_sys_ck");
@ -995,14 +986,12 @@ static int hwa742_init(struct omapfb_device *fbdev, int ext_mode,
goto err4;
}
if (ctrl_conf->te_connected) {
if ((r = setup_tearsync(pix_clk, extif_mem_div)) < 0) {
dev_err(hwa742.fbdev->dev,
"HWA742: can't setup tearing synchronization\n");
goto err4;
}
hwa742.te_connected = 1;
if ((r = setup_tearsync(pix_clk, extif_mem_div)) < 0) {
dev_err(hwa742.fbdev->dev,
"HWA742: can't setup tearing synchronization\n");
goto err4;
}
hwa742.te_connected = 1;
hwa742.max_transmit_size = hwa742.extif->max_transmit_size;

10
drivers/video/omap/lcd_inn1610.c
View File

@ -22,7 +22,7 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <asm/gpio.h>
#include <linux/gpio.h>
#include "omapfb.h"
#define MODULE_NAME "omapfb-lcd_h3"
@ -32,20 +32,18 @@ static int innovator1610_panel_init(struct lcd_panel *panel,
{
int r = 0;
if (gpio_request(14, "lcd_en0")) {
/* configure GPIO(14, 15) as outputs */
if (gpio_request_one(14, GPIOF_OUT_INIT_LOW, "lcd_en0")) {
pr_err(MODULE_NAME ": can't request GPIO 14\n");
r = -1;
goto exit;
}
if (gpio_request(15, "lcd_en1")) {
if (gpio_request_one(15, GPIOF_OUT_INIT_LOW, "lcd_en1")) {
pr_err(MODULE_NAME ": can't request GPIO 15\n");
gpio_free(14);
r = -1;
goto exit;
}
/* configure GPIO(14, 15) as outputs */
gpio_direction_output(14, 0);
gpio_direction_output(15, 0);
exit:
return r;
}

14
drivers/video/omap/lcd_mipid.c
View File

@ -609,19 +609,7 @@ static struct spi_driver mipid_spi_driver = {
.remove = __devexit_p(mipid_spi_remove),
};
static int __init mipid_drv_init(void)
{
spi_register_driver(&mipid_spi_driver);
return 0;
}
module_init(mipid_drv_init);
static void __exit mipid_drv_cleanup(void)
{
spi_unregister_driver(&mipid_spi_driver);
}
module_exit(mipid_drv_cleanup);
module_spi_driver(mipid_spi_driver);
MODULE_DESCRIPTION("MIPI display driver");
MODULE_LICENSE("GPL");

25
drivers/video/omap/omapfb.h
View File

@ -47,6 +47,27 @@
struct omapfb_device;
#define OMAPFB_PLANE_NUM 1
struct omapfb_mem_region {
u32 paddr;
void __iomem *vaddr;
unsigned long size;
u8 type; /* OMAPFB_PLANE_MEM_* */
enum omapfb_color_format format;/* OMAPFB_COLOR_* */
unsigned format_used:1; /* Must be set when format is set.
* Needed b/c of the badly chosen 0
* base for OMAPFB_COLOR_* values
*/
unsigned alloc:1; /* allocated by the driver */
unsigned map:1; /* kernel mapped by the driver */
};
struct omapfb_mem_desc {
int region_cnt;
struct omapfb_mem_region region[OMAPFB_PLANE_NUM];
};
struct lcd_panel {
const char *name;
int config; /* TFT/STN, signal inversion */
@ -207,11 +228,7 @@ struct omapfb_device {
struct platform_device *dssdev; /* dummy dev for clocks */
};
#ifdef CONFIG_ARCH_OMAP1
extern struct lcd_ctrl omap1_lcd_ctrl;
#else
extern struct lcd_ctrl omap2_disp_ctrl;
#endif
extern void omapfb_register_panel(struct lcd_panel *panel);
extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);

30
drivers/video/omap/omapfb_main.c
View File

@ -34,7 +34,6 @@
#include "omapfb.h"
#include "lcdc.h"
#include "dispc.h"
#define MODULE_NAME "omapfb"
@ -104,29 +103,17 @@ static struct platform_device omapdss_device = {
* ---------------------------------------------------------------------------
*/
extern struct lcd_ctrl hwa742_ctrl;
extern struct lcd_ctrl blizzard_ctrl;
static const struct lcd_ctrl *ctrls[] = {
#ifdef CONFIG_ARCH_OMAP1
&omap1_int_ctrl,
#else
&omap2_int_ctrl,
#endif
#ifdef CONFIG_FB_OMAP_LCDC_HWA742
&hwa742_ctrl,
#endif
#ifdef CONFIG_FB_OMAP_LCDC_BLIZZARD
&blizzard_ctrl,
#endif
};
#ifdef CONFIG_FB_OMAP_LCDC_EXTERNAL
#ifdef CONFIG_ARCH_OMAP1
extern struct lcd_ctrl_extif omap1_ext_if;
#else
extern struct lcd_ctrl_extif omap2_ext_if;
#endif
#endif
static void omapfb_rqueue_lock(struct omapfb_device *fbdev)
@ -170,11 +157,6 @@ static int ctrl_init(struct omapfb_device *fbdev)
fbdev->mem_desc.region[i].size =
PAGE_ALIGN(def_vram[i]);
fbdev->mem_desc.region_cnt = i;
} else {
struct omapfb_platform_data *conf;
conf = fbdev->dev->platform_data;
fbdev->mem_desc = conf->mem_desc;
}
if (!fbdev->mem_desc.region_cnt) {
@ -880,7 +862,7 @@ static int omapfb_setup_mem(struct fb_info *fbi, struct omapfb_mem_info *mi)
if (fbdev->ctrl->setup_mem == NULL)
return -ENODEV;
if (mi->type > OMAPFB_MEMTYPE_MAX)
if (mi->type != OMAPFB_MEMTYPE_SDRAM)
return -EINVAL;
size = PAGE_ALIGN(mi->size);
@ -1721,16 +1703,9 @@ static int omapfb_do_probe(struct platform_device *pdev,
mutex_init(&fbdev->rqueue_mutex);
#ifdef CONFIG_ARCH_OMAP1
fbdev->int_ctrl = &omap1_int_ctrl;
#ifdef CONFIG_FB_OMAP_LCDC_EXTERNAL
fbdev->ext_if = &omap1_ext_if;
#endif
#else /* OMAP2 */
fbdev->int_ctrl = &omap2_int_ctrl;
#ifdef CONFIG_FB_OMAP_LCDC_EXTERNAL
fbdev->ext_if = &omap2_ext_if;
#endif
#endif
if (omapfb_find_ctrl(fbdev) < 0) {
dev_err(fbdev->dev,
@ -1766,8 +1741,7 @@ static int omapfb_do_probe(struct platform_device *pdev,
#ifdef CONFIG_FB_OMAP_DMA_TUNE
/* Set DMA priority for EMIFF access to highest */
if (cpu_class_is_omap1())
omap_set_dma_priority(0, OMAP_DMA_PORT_EMIFF, 15);
omap_set_dma_priority(0, OMAP_DMA_PORT_EMIFF, 15);
#endif
r = ctrl_change_mode(fbdev->fb_info[0]);

598
drivers/video/omap/rfbi.c
View File

@ -1,598 +0,0 @@
/*
* OMAP2 Remote Frame Buffer Interface support
*
* Copyright (C) 2005 Nokia Corporation
* Author: Juha Yrjölä <juha.yrjola@nokia.com>
* Imre Deak <imre.deak@nokia.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include "omapfb.h"
#include "dispc.h"
/* To work around an RFBI transfer rate limitation */
#define OMAP_RFBI_RATE_LIMIT 1
#define RFBI_BASE 0x48050800
#define RFBI_REVISION 0x0000
#define RFBI_SYSCONFIG 0x0010
#define RFBI_SYSSTATUS 0x0014
#define RFBI_CONTROL 0x0040
#define RFBI_PIXEL_CNT 0x0044
#define RFBI_LINE_NUMBER 0x0048
#define RFBI_CMD 0x004c
#define RFBI_PARAM 0x0050
#define RFBI_DATA 0x0054
#define RFBI_READ 0x0058
#define RFBI_STATUS 0x005c
#define RFBI_CONFIG0 0x0060
#define RFBI_ONOFF_TIME0 0x0064
#define RFBI_CYCLE_TIME0 0x0068
#define RFBI_DATA_CYCLE1_0 0x006c
#define RFBI_DATA_CYCLE2_0 0x0070
#define RFBI_DATA_CYCLE3_0 0x0074
#define RFBI_VSYNC_WIDTH 0x0090
#define RFBI_HSYNC_WIDTH 0x0094
#define DISPC_BASE 0x48050400
#define DISPC_CONTROL 0x0040
#define DISPC_IRQ_FRAMEMASK 0x0001
static struct {
void __iomem *base;
void (*lcdc_callback)(void *data);
void *lcdc_callback_data;
unsigned long l4_khz;
int bits_per_cycle;
struct omapfb_device *fbdev;
struct clk *dss_ick;
struct clk *dss1_fck;
unsigned tearsync_pin_cnt;
unsigned tearsync_mode;
} rfbi;
static inline void rfbi_write_reg(int idx, u32 val)
{
__raw_writel(val, rfbi.base + idx);
}
static inline u32 rfbi_read_reg(int idx)
{
return __raw_readl(rfbi.base + idx);
}
static int rfbi_get_clocks(void)
{
rfbi.dss_ick = clk_get(&rfbi.fbdev->dssdev->dev, "ick");
if (IS_ERR(rfbi.dss_ick)) {
dev_err(rfbi.fbdev->dev, "can't get ick\n");
return PTR_ERR(rfbi.dss_ick);
}
rfbi.dss1_fck = clk_get(&rfbi.fbdev->dssdev->dev, "fck");
if (IS_ERR(rfbi.dss1_fck)) {
dev_err(rfbi.fbdev->dev, "can't get dss1_fck\n");
clk_put(rfbi.dss_ick);
return PTR_ERR(rfbi.dss1_fck);
}
return 0;
}
static void rfbi_put_clocks(void)
{
clk_put(rfbi.dss1_fck);
clk_put(rfbi.dss_ick);
}
static void rfbi_enable_clocks(int enable)
{
if (enable) {
clk_enable(rfbi.dss_ick);
clk_enable(rfbi.dss1_fck);
} else {
clk_disable(rfbi.dss1_fck);
clk_disable(rfbi.dss_ick);
}
}
#ifdef VERBOSE
static void rfbi_print_timings(void)
{
u32 l;
u32 time;
l = rfbi_read_reg(RFBI_CONFIG0);
time = 1000000000 / rfbi.l4_khz;
if (l & (1 << 4))
time *= 2;
dev_dbg(rfbi.fbdev->dev, "Tick time %u ps\n", time);
l = rfbi_read_reg(RFBI_ONOFF_TIME0);
dev_dbg(rfbi.fbdev->dev,
"CSONTIME %d, CSOFFTIME %d, WEONTIME %d, WEOFFTIME %d, "
"REONTIME %d, REOFFTIME %d\n",
l & 0x0f, (l >> 4) & 0x3f, (l >> 10) & 0x0f, (l >> 14) & 0x3f,
(l >> 20) & 0x0f, (l >> 24) & 0x3f);
l = rfbi_read_reg(RFBI_CYCLE_TIME0);
dev_dbg(rfbi.fbdev->dev,
"WECYCLETIME %d, RECYCLETIME %d, CSPULSEWIDTH %d, "
"ACCESSTIME %d\n",
(l & 0x3f), (l >> 6) & 0x3f, (l >> 12) & 0x3f,
(l >> 22) & 0x3f);
}
#else
static void rfbi_print_timings(void) {}
#endif
static void rfbi_set_timings(const struct extif_timings *t)
{
u32 l;
BUG_ON(!t->converted);
rfbi_enable_clocks(1);
rfbi_write_reg(RFBI_ONOFF_TIME0, t->tim[0]);
rfbi_write_reg(RFBI_CYCLE_TIME0, t->tim[1]);
l = rfbi_read_reg(RFBI_CONFIG0);
l &= ~(1 << 4);
l |= (t->tim[2] ? 1 : 0) << 4;
rfbi_write_reg(RFBI_CONFIG0, l);
rfbi_print_timings();
rfbi_enable_clocks(0);
}
static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div)
{
*clk_period = 1000000000 / rfbi.l4_khz;
*max_clk_div = 2;
}
static int ps_to_rfbi_ticks(int time, int div)
{
unsigned long tick_ps;
int ret;
/* Calculate in picosecs to yield more exact results */
tick_ps = 1000000000 / (rfbi.l4_khz) * div;
ret = (time + tick_ps - 1) / tick_ps;
return ret;
}
#ifdef OMAP_RFBI_RATE_LIMIT
static unsigned long rfbi_get_max_tx_rate(void)
{
unsigned long l4_rate, dss1_rate;
int min_l4_ticks = 0;
int i;
/* According to TI this can't be calculated so make the
* adjustments for a couple of known frequencies and warn for
* others.
*/
static const struct {
unsigned long l4_clk; /* HZ */
unsigned long dss1_clk; /* HZ */
unsigned long min_l4_ticks;
} ftab[] = {
{ 55, 132, 7, }, /* 7.86 MPix/s */
{ 110, 110, 12, }, /* 9.16 MPix/s */
{ 110, 132, 10, }, /* 11 Mpix/s */
{ 120, 120, 10, }, /* 12 Mpix/s */
{ 133, 133, 10, }, /* 13.3 Mpix/s */
};
l4_rate = rfbi.l4_khz / 1000;
dss1_rate = clk_get_rate(rfbi.dss1_fck) / 1000000;
for (i = 0; i < ARRAY_SIZE(ftab); i++) {
/* Use a window instead of an exact match, to account
* for different DPLL multiplier / divider pairs.
*/
if (abs(ftab[i].l4_clk - l4_rate) < 3 &&
abs(ftab[i].dss1_clk - dss1_rate) < 3) {
min_l4_ticks = ftab[i].min_l4_ticks;
break;
}
}
if (i == ARRAY_SIZE(ftab)) {
/* Can't be sure, return anyway the maximum not
* rate-limited. This might cause a problem only for the
* tearing synchronisation.
*/
dev_err(rfbi.fbdev->dev,
"can't determine maximum RFBI transfer rate\n");
return rfbi.l4_khz * 1000;
}
return rfbi.l4_khz * 1000 / min_l4_ticks;
}
#else
static int rfbi_get_max_tx_rate(void)
{
return rfbi.l4_khz * 1000;
}
#endif
static int rfbi_convert_timings(struct extif_timings *t)
{
u32 l;
int reon, reoff, weon, weoff, cson, csoff, cs_pulse;
int actim, recyc, wecyc;
int div = t->clk_div;
if (div <= 0 || div > 2)
return -1;
/* Make sure that after conversion it still holds that:
* weoff > weon, reoff > reon, recyc >= reoff, wecyc >= weoff,
* csoff > cson, csoff >= max(weoff, reoff), actim > reon
*/
weon = ps_to_rfbi_ticks(t->we_on_time, div);
weoff = ps_to_rfbi_ticks(t->we_off_time, div);
if (weoff <= weon)
weoff = weon + 1;
if (weon > 0x0f)
return -1;
if (weoff > 0x3f)
return -1;
reon = ps_to_rfbi_ticks(t->re_on_time, div);
reoff = ps_to_rfbi_ticks(t->re_off_time, div);
if (reoff <= reon)
reoff = reon + 1;
if (reon > 0x0f)
return -1;
if (reoff > 0x3f)
return -1;
cson = ps_to_rfbi_ticks(t->cs_on_time, div);
csoff = ps_to_rfbi_ticks(t->cs_off_time, div);
if (csoff <= cson)
csoff = cson + 1;
if (csoff < max(weoff, reoff))
csoff = max(weoff, reoff);
if (cson > 0x0f)
return -1;
if (csoff > 0x3f)
return -1;
l = cson;
l |= csoff << 4;
l |= weon << 10;
l |= weoff << 14;
l |= reon << 20;
l |= reoff << 24;
t->tim[0] = l;
actim = ps_to_rfbi_ticks(t->access_time, div);
if (actim <= reon)
actim = reon + 1;
if (actim > 0x3f)
return -1;
wecyc = ps_to_rfbi_ticks(t->we_cycle_time, div);
if (wecyc < weoff)
wecyc = weoff;
if (wecyc > 0x3f)
return -1;
recyc = ps_to_rfbi_ticks(t->re_cycle_time, div);
if (recyc < reoff)
recyc = reoff;
if (recyc > 0x3f)
return -1;
cs_pulse = ps_to_rfbi_ticks(t->cs_pulse_width, div);
if (cs_pulse > 0x3f)
return -1;
l = wecyc;
l |= recyc << 6;
l |= cs_pulse << 12;
l |= actim << 22;
t->tim[1] = l;
t->tim[2] = div - 1;
t->converted = 1;
return 0;
}
static int rfbi_setup_tearsync(unsigned pin_cnt,
unsigned hs_pulse_time, unsigned vs_pulse_time,
int hs_pol_inv, int vs_pol_inv, int extif_div)
{
int hs, vs;
int min;
u32 l;
if (pin_cnt != 1 && pin_cnt != 2)
return -EINVAL;
hs = ps_to_rfbi_ticks(hs_pulse_time, 1);
vs = ps_to_rfbi_ticks(vs_pulse_time, 1);
if (hs < 2)
return -EDOM;
if (pin_cnt == 2)
min = 2;
else
min = 4;
if (vs < min)
return -EDOM;
if (vs == hs)
return -EINVAL;
rfbi.tearsync_pin_cnt = pin_cnt;
dev_dbg(rfbi.fbdev->dev,
"setup_tearsync: pins %d hs %d vs %d hs_inv %d vs_inv %d\n",
pin_cnt, hs, vs, hs_pol_inv, vs_pol_inv);
rfbi_enable_clocks(1);
rfbi_write_reg(RFBI_HSYNC_WIDTH, hs);
rfbi_write_reg(RFBI_VSYNC_WIDTH, vs);
l = rfbi_read_reg(RFBI_CONFIG0);
if (hs_pol_inv)
l &= ~(1 << 21);
else
l |= 1 << 21;
if (vs_pol_inv)
l &= ~(1 << 20);
else
l |= 1 << 20;
rfbi_enable_clocks(0);
return 0;
}
static int rfbi_enable_tearsync(int enable, unsigned line)
{
u32 l;
dev_dbg(rfbi.fbdev->dev, "tearsync %d line %d mode %d\n",
enable, line, rfbi.tearsync_mode);
if (line > (1 << 11) - 1)
return -EINVAL;
rfbi_enable_clocks(1);
l = rfbi_read_reg(RFBI_CONFIG0);
l &= ~(0x3 << 2);
if (enable) {
rfbi.tearsync_mode = rfbi.tearsync_pin_cnt;
l |= rfbi.tearsync_mode << 2;
} else
rfbi.tearsync_mode = 0;
rfbi_write_reg(RFBI_CONFIG0, l);
rfbi_write_reg(RFBI_LINE_NUMBER, line);
rfbi_enable_clocks(0);
return 0;
}
static void rfbi_write_command(const void *buf, unsigned int len)
{
rfbi_enable_clocks(1);
if (rfbi.bits_per_cycle == 16) {
const u16 *w = buf;
BUG_ON(len & 1);
for (; len; len -= 2)
rfbi_write_reg(RFBI_CMD, *w++);
} else {
const u8 *b = buf;
BUG_ON(rfbi.bits_per_cycle != 8);
for (; len; len--)
rfbi_write_reg(RFBI_CMD, *b++);
}
rfbi_enable_clocks(0);
}
static void rfbi_read_data(void *buf, unsigned int len)
{
rfbi_enable_clocks(1);
if (rfbi.bits_per_cycle == 16) {
u16 *w = buf;
BUG_ON(len & ~1);
for (; len; len -= 2) {
rfbi_write_reg(RFBI_READ, 0);
*w++ = rfbi_read_reg(RFBI_READ);
}
} else {
u8 *b = buf;
BUG_ON(rfbi.bits_per_cycle != 8);
for (; len; len--) {
rfbi_write_reg(RFBI_READ, 0);
*b++ = rfbi_read_reg(RFBI_READ);
}
}
rfbi_enable_clocks(0);
}
static void rfbi_write_data(const void *buf, unsigned int len)
{
rfbi_enable_clocks(1);
if (rfbi.bits_per_cycle == 16) {
const u16 *w = buf;
BUG_ON(len & 1);
for (; len; len -= 2)
rfbi_write_reg(RFBI_PARAM, *w++);
} else {
const u8 *b = buf;
BUG_ON(rfbi.bits_per_cycle != 8);
for (; len; len--)
rfbi_write_reg(RFBI_PARAM, *b++);
}
rfbi_enable_clocks(0);
}
static void rfbi_transfer_area(int width, int height,
void (callback)(void * data), void *data)
{
u32 w;
BUG_ON(callback == NULL);
rfbi_enable_clocks(1);
omap_dispc_set_lcd_size(width, height);
rfbi.lcdc_callback = callback;
rfbi.lcdc_callback_data = data;
rfbi_write_reg(RFBI_PIXEL_CNT, width * height);
w = rfbi_read_reg(RFBI_CONTROL);
w |= 1; /* enable */
if (!rfbi.tearsync_mode)
w |= 1 << 4; /* internal trigger, reset by HW */
rfbi_write_reg(RFBI_CONTROL, w);
omap_dispc_enable_lcd_out(1);
}
static inline void _stop_transfer(void)
{
u32 w;
w = rfbi_read_reg(RFBI_CONTROL);
rfbi_write_reg(RFBI_CONTROL, w & ~(1 << 0));
rfbi_enable_clocks(0);
}
static void rfbi_dma_callback(void *data)
{
_stop_transfer();
rfbi.lcdc_callback(rfbi.lcdc_callback_data);
}
static void rfbi_set_bits_per_cycle(int bpc)
{
u32 l;
rfbi_enable_clocks(1);
l = rfbi_read_reg(RFBI_CONFIG0);
l &= ~(0x03 << 0);
switch (bpc) {
case 8:
break;
case 16:
l |= 3;
break;
default:
BUG();
}
rfbi_write_reg(RFBI_CONFIG0, l);
rfbi.bits_per_cycle = bpc;
rfbi_enable_clocks(0);
}
static int rfbi_init(struct omapfb_device *fbdev)
{
u32 l;
int r;
rfbi.fbdev = fbdev;
rfbi.base = ioremap(RFBI_BASE, SZ_1K);
if (!rfbi.base) {
dev_err(fbdev->dev, "can't ioremap RFBI\n");
return -ENOMEM;
}
if ((r = rfbi_get_clocks()) < 0)
return r;
rfbi_enable_clocks(1);
rfbi.l4_khz = clk_get_rate(rfbi.dss_ick) / 1000;
/* Reset */
rfbi_write_reg(RFBI_SYSCONFIG, 1 << 1);
while (!(rfbi_read_reg(RFBI_SYSSTATUS) & (1 << 0)));
l = rfbi_read_reg(RFBI_SYSCONFIG);
/* Enable autoidle and smart-idle */
l |= (1 << 0) | (2 << 3);
rfbi_write_reg(RFBI_SYSCONFIG, l);
/* 16-bit interface, ITE trigger mode, 16-bit data */
l = (0x03 << 0) | (0x00 << 2) | (0x01 << 5) | (0x02 << 7);
l |= (0 << 9) | (1 << 20) | (1 << 21);
rfbi_write_reg(RFBI_CONFIG0, l);
rfbi_write_reg(RFBI_DATA_CYCLE1_0, 0x00000010);
l = rfbi_read_reg(RFBI_CONTROL);
/* Select CS0, clear bypass mode */
l = (0x01 << 2);
rfbi_write_reg(RFBI_CONTROL, l);
r = omap_dispc_request_irq(DISPC_IRQ_FRAMEMASK, rfbi_dma_callback,
NULL);
if (r < 0) {
dev_err(fbdev->dev, "can't get DISPC irq\n");
rfbi_enable_clocks(0);
return r;
}
l = rfbi_read_reg(RFBI_REVISION);
pr_info("omapfb: RFBI version %d.%d initialized\n",
(l >> 4) & 0x0f, l & 0x0f);
rfbi_enable_clocks(0);
return 0;
}
static void rfbi_cleanup(void)
{
omap_dispc_free_irq(DISPC_IRQ_FRAMEMASK, rfbi_dma_callback, NULL);
rfbi_put_clocks();
iounmap(rfbi.base);
}
const struct lcd_ctrl_extif omap2_ext_if = {
.init = rfbi_init,
.cleanup = rfbi_cleanup,
.get_clk_info = rfbi_get_clk_info,
.get_max_tx_rate = rfbi_get_max_tx_rate,
.set_bits_per_cycle = rfbi_set_bits_per_cycle,
.convert_timings = rfbi_convert_timings,
.set_timings = rfbi_set_timings,
.write_command = rfbi_write_command,
.read_data = rfbi_read_data,
.write_data = rfbi_write_data,
.transfer_area = rfbi_transfer_area,
.setup_tearsync = rfbi_setup_tearsync,
.enable_tearsync = rfbi_enable_tearsync,
.max_transmit_size = (u32) ~0,
};

13
drivers/video/omap2/displays/panel-acx565akm.c
View File

@ -809,18 +809,7 @@ static struct spi_driver acx565akm_spi_driver = {
.remove = __devexit_p(acx565akm_spi_remove),
};
static int __init acx565akm_init(void)
{
return spi_register_driver(&acx565akm_spi_driver);
}
static void __exit acx565akm_exit(void)
{
spi_unregister_driver(&acx565akm_spi_driver);
}
module_init(acx565akm_init);
module_exit(acx565akm_exit);
module_spi_driver(acx565akm_spi_driver);
MODULE_AUTHOR("Nokia Corporation");
MODULE_DESCRIPTION("acx565akm LCD Driver");

23
drivers/video/omap2/displays/panel-generic-dpi.c
View File

@ -363,6 +363,29 @@ static struct panel_config generic_dpi_panels[] = {
.name = "ortustech_com43h4m10xtc",
},
/* Innolux AT080TN52 */
{
{
.x_res = 800,
.y_res = 600,
.pixel_clock = 41142,
.hsw = 20,
.hfp = 210,
.hbp = 46,
.vsw = 10,
.vfp = 12,
.vbp = 23,
},
.acb = 0x0,
.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IEO,
.name = "innolux_at080tn52",
},
};
struct panel_drv_data {

12
drivers/video/omap2/displays/panel-lgphilips-lb035q02.c
View File

@ -264,16 +264,6 @@ static struct spi_driver lb035q02_spi_driver = {
.remove = __devexit_p(lb035q02_panel_spi_remove),
};
static int __init lb035q02_panel_drv_init(void)
{
return spi_register_driver(&lb035q02_spi_driver);
}
module_spi_driver(lb035q02_spi_driver);
static void __exit lb035q02_panel_drv_exit(void)
{
spi_unregister_driver(&lb035q02_spi_driver);
}
module_init(lb035q02_panel_drv_init);
module_exit(lb035q02_panel_drv_exit);
MODULE_LICENSE("GPL");

12
drivers/video/omap2/displays/panel-nec-nl8048hl11-01b.c
View File

@ -350,18 +350,8 @@ static struct spi_driver nec_8048_spi_driver = {
},
};
static int __init nec_8048_lcd_init(void)
{
return spi_register_driver(&nec_8048_spi_driver);
}
module_spi_driver(nec_8048_spi_driver);
static void __exit nec_8048_lcd_exit(void)
{
return spi_unregister_driver(&nec_8048_spi_driver);
}
module_init(nec_8048_lcd_init);
module_exit(nec_8048_lcd_exit);
MODULE_AUTHOR("Erik Gilling <konkers@android.com>");
MODULE_DESCRIPTION("NEC-nl8048hl11-01b Driver");
MODULE_LICENSE("GPL");

4
drivers/video/omap2/displays/panel-taal.c
View File

@ -1019,14 +1019,12 @@ static int taal_probe(struct omap_dss_device *dssdev)
if (panel_data->use_ext_te) {
int gpio = panel_data->ext_te_gpio;
r = gpio_request(gpio, "taal irq");
r = gpio_request_one(gpio, GPIOF_IN, "taal irq");
if (r) {
dev_err(&dssdev->dev, "GPIO request failed\n");
goto err_gpio;
}
gpio_direction_input(gpio);
r = request_irq(gpio_to_irq(gpio), taal_te_isr,
IRQF_TRIGGER_RISING,
"taal vsync", dssdev);

179
drivers/video/omap2/displays/panel-tpo-td043mtea1.c
View File

@ -47,16 +47,20 @@
TPO_R03_EN_PRE_CHARGE | TPO_R03_SOFTWARE_CTL)
static const u16 tpo_td043_def_gamma[12] = {
106, 200, 289, 375, 460, 543, 625, 705, 785, 864, 942, 1020
105, 315, 381, 431, 490, 537, 579, 686, 780, 837, 880, 1023
};
struct tpo_td043_device {
struct spi_device *spi;
struct regulator *vcc_reg;
int nreset_gpio;
u16 gamma[12];
u32 mode;
u32 hmirror:1;
u32 vmirror:1;
u32 powered_on:1;
u32 spi_suspended:1;
u32 power_on_resume:1;
};
static int tpo_td043_write(struct spi_device *spi, u8 addr, u8 data)
@ -265,28 +269,16 @@ static const struct omap_video_timings tpo_td043_timings = {
.vbp = 34,
};
static int tpo_td043_power_on(struct omap_dss_device *dssdev)
static int tpo_td043_power_on(struct tpo_td043_device *tpo_td043)
{
struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev);
int nreset_gpio = dssdev->reset_gpio;
int r;
int nreset_gpio = tpo_td043->nreset_gpio;
if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE)
if (tpo_td043->powered_on)
return 0;
r = omapdss_dpi_display_enable(dssdev);
if (r)
goto err0;
if (dssdev->platform_enable) {
r = dssdev->platform_enable(dssdev);
if (r)
goto err1;
}
regulator_enable(tpo_td043->vcc_reg);
/* wait for power up */
/* wait for regulator to stabilize */
msleep(160);
if (gpio_is_valid(nreset_gpio))
@ -301,19 +293,15 @@ static int tpo_td043_power_on(struct omap_dss_device *dssdev)
tpo_td043->vmirror);
tpo_td043_write_gamma(tpo_td043->spi, tpo_td043->gamma);
tpo_td043->powered_on = 1;
return 0;
err1:
omapdss_dpi_display_disable(dssdev);
err0:
return r;
}
static void tpo_td043_power_off(struct omap_dss_device *dssdev)
static void tpo_td043_power_off(struct tpo_td043_device *tpo_td043)
{
struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev);
int nreset_gpio = dssdev->reset_gpio;
int nreset_gpio = tpo_td043->nreset_gpio;
if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
if (!tpo_td043->powered_on)
return;
tpo_td043_write(tpo_td043->spi, 3,
@ -329,54 +317,94 @@ static void tpo_td043_power_off(struct omap_dss_device *dssdev)
regulator_disable(tpo_td043->vcc_reg);
if (dssdev->platform_disable)
dssdev->platform_disable(dssdev);
omapdss_dpi_display_disable(dssdev);
tpo_td043->powered_on = 0;
}
static int tpo_td043_enable(struct omap_dss_device *dssdev)
static int tpo_td043_enable_dss(struct omap_dss_device *dssdev)
{
int ret;
struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev);
int r;
dev_dbg(&dssdev->dev, "enable\n");
if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE)
return 0;
ret = tpo_td043_power_on(dssdev);
if (ret)
return ret;
r = omapdss_dpi_display_enable(dssdev);
if (r)
goto err0;
if (dssdev->platform_enable) {
r = dssdev->platform_enable(dssdev);
if (r)
goto err1;
}
/*
* If we are resuming from system suspend, SPI clocks might not be
* enabled yet, so we'll program the LCD from SPI PM resume callback.
*/
if (!tpo_td043->spi_suspended) {
r = tpo_td043_power_on(tpo_td043);
if (r)
goto err1;
}
dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
return 0;
err1:
omapdss_dpi_display_disable(dssdev);
err0:
return r;
}
static void tpo_td043_disable_dss(struct omap_dss_device *dssdev)
{
struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev);
if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
return;
if (dssdev->platform_disable)
dssdev->platform_disable(dssdev);
omapdss_dpi_display_disable(dssdev);
if (!tpo_td043->spi_suspended)
tpo_td043_power_off(tpo_td043);
}
static int tpo_td043_enable(struct omap_dss_device *dssdev)
{
dev_dbg(&dssdev->dev, "enable\n");
return tpo_td043_enable_dss(dssdev);
}
static void tpo_td043_disable(struct omap_dss_device *dssdev)
{
dev_dbg(&dssdev->dev, "disable\n");
tpo_td043_power_off(dssdev);
tpo_td043_disable_dss(dssdev);
dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
}
static int tpo_td043_suspend(struct omap_dss_device *dssdev)
{
tpo_td043_power_off(dssdev);
dev_dbg(&dssdev->dev, "suspend\n");
tpo_td043_disable_dss(dssdev);
dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED;
return 0;
}
static int tpo_td043_resume(struct omap_dss_device *dssdev)
{
int r = 0;
dev_dbg(&dssdev->dev, "resume\n");
r = tpo_td043_power_on(dssdev);
if (r)
return r;
dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
return 0;
return tpo_td043_enable_dss(dssdev);
}
static int tpo_td043_probe(struct omap_dss_device *dssdev)
@ -408,17 +436,12 @@ static int tpo_td043_probe(struct omap_dss_device *dssdev)
}
if (gpio_is_valid(nreset_gpio)) {
ret = gpio_request(nreset_gpio, "lcd reset");
ret = gpio_request_one(nreset_gpio, GPIOF_OUT_INIT_LOW,
"lcd reset");
if (ret < 0) {
dev_err(&dssdev->dev, "couldn't request reset GPIO\n");
goto fail_gpio_req;
}
ret = gpio_direction_output(nreset_gpio, 0);
if (ret < 0) {
dev_err(&dssdev->dev, "couldn't set GPIO direction\n");
goto fail_gpio_direction;
}
}
ret = sysfs_create_group(&dssdev->dev.kobj, &tpo_td043_attr_group);
@ -427,8 +450,6 @@ static int tpo_td043_probe(struct omap_dss_device *dssdev)
return 0;
fail_gpio_direction:
gpio_free(nreset_gpio);
fail_gpio_req:
regulator_put(tpo_td043->vcc_reg);
fail_regulator:
@ -491,6 +512,7 @@ static int tpo_td043_spi_probe(struct spi_device *spi)
return -ENOMEM;
tpo_td043->spi = spi;
tpo_td043->nreset_gpio = dssdev->reset_gpio;
dev_set_drvdata(&spi->dev, tpo_td043);
dev_set_drvdata(&dssdev->dev, tpo_td043);
@ -509,27 +531,52 @@ static int __devexit tpo_td043_spi_remove(struct spi_device *spi)
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int tpo_td043_spi_suspend(struct device *dev)
{
struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev);
dev_dbg(dev, "tpo_td043_spi_suspend, tpo %p\n", tpo_td043);
tpo_td043->power_on_resume = tpo_td043->powered_on;
tpo_td043_power_off(tpo_td043);
tpo_td043->spi_suspended = 1;
return 0;
}
static int tpo_td043_spi_resume(struct device *dev)
{
struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev);
int ret;
dev_dbg(dev, "tpo_td043_spi_resume\n");
if (tpo_td043->power_on_resume) {
ret = tpo_td043_power_on(tpo_td043);
if (ret)
return ret;
}
tpo_td043->spi_suspended = 0;
return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(tpo_td043_spi_pm,
tpo_td043_spi_suspend, tpo_td043_spi_resume);
static struct spi_driver tpo_td043_spi_driver = {
.driver = {
.name = "tpo_td043mtea1_panel_spi",
.owner = THIS_MODULE,
.pm = &tpo_td043_spi_pm,
},
.probe = tpo_td043_spi_probe,
.remove = __devexit_p(tpo_td043_spi_remove),
};
static int __init tpo_td043_init(void)
{
return spi_register_driver(&tpo_td043_spi_driver);
}
static void __exit tpo_td043_exit(void)
{
spi_unregister_driver(&tpo_td043_spi_driver);
}
module_init(tpo_td043_init);
module_exit(tpo_td043_exit);
module_spi_driver(tpo_td043_spi_driver);
MODULE_AUTHOR("Gražvydas Ignotas <notasas@gmail.com>");
MODULE_DESCRIPTION("TPO TD043MTEA1 LCD Driver");

275
drivers/video/omap2/dss/apply.c
View File

@ -105,6 +105,9 @@ static struct {
struct ovl_priv_data ovl_priv_data_array[MAX_DSS_OVERLAYS];
struct mgr_priv_data mgr_priv_data_array[MAX_DSS_MANAGERS];
bool fifo_merge_dirty;
bool fifo_merge;
bool irq_enabled;
} dss_data;
@ -351,6 +354,7 @@ static void wait_pending_extra_info_updates(void)
bool updating;
unsigned long flags;
unsigned long t;
int r;
spin_lock_irqsave(&data_lock, flags);
@ -366,11 +370,11 @@ static void wait_pending_extra_info_updates(void)
spin_unlock_irqrestore(&data_lock, flags);
t = msecs_to_jiffies(500);
wait_for_completion_timeout(&extra_updated_completion, t);
updating = extra_info_update_ongoing();
WARN_ON(updating);
r = wait_for_completion_timeout(&extra_updated_completion, t);
if (r == 0)
DSSWARN("timeout in wait_pending_extra_info_updates\n");
else if (r < 0)
DSSERR("wait_pending_extra_info_updates failed: %d\n", r);
}
int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr)
@ -388,6 +392,10 @@ int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr)
if (mgr_manual_update(mgr))
return 0;
r = dispc_runtime_get();
if (r)
return r;
irq = dispc_mgr_get_vsync_irq(mgr->id);
mp = get_mgr_priv(mgr);
@ -428,6 +436,8 @@ int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr)
}
}
dispc_runtime_put();
return r;
}
@ -451,6 +461,10 @@ int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl)
if (ovl_manual_update(ovl))
return 0;
r = dispc_runtime_get();
if (r)
return r;
irq = dispc_mgr_get_vsync_irq(ovl->manager->id);
op = get_ovl_priv(ovl);
@ -491,6 +505,8 @@ int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl)
}
}
dispc_runtime_put();
return r;
}
@ -585,11 +601,40 @@ static void dss_mgr_write_regs(struct omap_overlay_manager *mgr)
}
}
static void dss_write_regs_common(void)
{
const int num_mgrs = omap_dss_get_num_overlay_managers();
int i;
if (!dss_data.fifo_merge_dirty)
return;
for (i = 0; i < num_mgrs; ++i) {
struct omap_overlay_manager *mgr;
struct mgr_priv_data *mp;
mgr = omap_dss_get_overlay_manager(i);
mp = get_mgr_priv(mgr);
if (mp->enabled) {
if (dss_data.fifo_merge_dirty) {
dispc_enable_fifomerge(dss_data.fifo_merge);
dss_data.fifo_merge_dirty = false;
}
if (mp->updating)
mp->shadow_info_dirty = true;
}
}
}
static void dss_write_regs(void)
{
const int num_mgrs = omap_dss_get_num_overlay_managers();
int i;
dss_write_regs_common();
for (i = 0; i < num_mgrs; ++i) {
struct omap_overlay_manager *mgr;
struct mgr_priv_data *mp;
@ -640,6 +685,22 @@ static void dss_set_go_bits(void)
}
static void mgr_clear_shadow_dirty(struct omap_overlay_manager *mgr)
{
struct omap_overlay *ovl;
struct mgr_priv_data *mp;
struct ovl_priv_data *op;
mp = get_mgr_priv(mgr);
mp->shadow_info_dirty = false;
list_for_each_entry(ovl, &mgr->overlays, list) {
op = get_ovl_priv(ovl);
op->shadow_info_dirty = false;
op->shadow_extra_info_dirty = false;
}
}
void dss_mgr_start_update(struct omap_overlay_manager *mgr)
{
struct mgr_priv_data *mp = get_mgr_priv(mgr);
@ -659,6 +720,8 @@ void dss_mgr_start_update(struct omap_overlay_manager *mgr)
dss_mgr_write_regs(mgr);
dss_write_regs_common();
mp->updating = true;
if (!dss_data.irq_enabled && need_isr())
@ -666,6 +729,8 @@ void dss_mgr_start_update(struct omap_overlay_manager *mgr)
dispc_mgr_enable(mgr->id, true);
mgr_clear_shadow_dirty(mgr);
spin_unlock_irqrestore(&data_lock, flags);
}
@ -709,22 +774,6 @@ static void dss_unregister_vsync_isr(void)
dss_data.irq_enabled = false;
}
static void mgr_clear_shadow_dirty(struct omap_overlay_manager *mgr)
{
struct omap_overlay *ovl;
struct mgr_priv_data *mp;
struct ovl_priv_data *op;
mp = get_mgr_priv(mgr);
mp->shadow_info_dirty = false;
list_for_each_entry(ovl, &mgr->overlays, list) {
op = get_ovl_priv(ovl);
op->shadow_info_dirty = false;
op->shadow_extra_info_dirty = false;
}
}
static void dss_apply_irq_handler(void *data, u32 mask)
{
const int num_mgrs = dss_feat_get_num_mgrs();
@ -754,9 +803,6 @@ static void dss_apply_irq_handler(void *data, u32 mask)
if (was_busy && !mp->busy)
mgr_clear_shadow_dirty(mgr);
} else {
if (was_updating && !mp->updating)
mgr_clear_shadow_dirty(mgr);
}
}
@ -859,11 +905,20 @@ static void dss_apply_ovl_fifo_thresholds(struct omap_overlay *ovl,
op->extra_info_dirty = true;
}
static void dss_ovl_setup_fifo(struct omap_overlay *ovl)
static void dss_apply_fifo_merge(bool use_fifo_merge)
{
if (dss_data.fifo_merge == use_fifo_merge)
return;
dss_data.fifo_merge = use_fifo_merge;
dss_data.fifo_merge_dirty = true;
}
static void dss_ovl_setup_fifo(struct omap_overlay *ovl,
bool use_fifo_merge)
{
struct ovl_priv_data *op = get_ovl_priv(ovl);
struct omap_dss_device *dssdev;
u32 size, burst_size;
u32 fifo_low, fifo_high;
if (!op->enabled && !op->enabling)
@ -871,33 +926,14 @@ static void dss_ovl_setup_fifo(struct omap_overlay *ovl)
dssdev = ovl->manager->device;
size = dispc_ovl_get_fifo_size(ovl->id);
burst_size = dispc_ovl_get_burst_size(ovl->id);
switch (dssdev->type) {
case OMAP_DISPLAY_TYPE_DPI:
case OMAP_DISPLAY_TYPE_DBI:
case OMAP_DISPLAY_TYPE_SDI:
case OMAP_DISPLAY_TYPE_VENC:
case OMAP_DISPLAY_TYPE_HDMI:
default_get_overlay_fifo_thresholds(ovl->id, size,
burst_size, &fifo_low, &fifo_high);
break;
#ifdef CONFIG_OMAP2_DSS_DSI
case OMAP_DISPLAY_TYPE_DSI:
dsi_get_overlay_fifo_thresholds(ovl->id, size,
burst_size, &fifo_low, &fifo_high);
break;
#endif
default:
BUG();
}
dispc_ovl_compute_fifo_thresholds(ovl->id, &fifo_low, &fifo_high,
use_fifo_merge);
dss_apply_ovl_fifo_thresholds(ovl, fifo_low, fifo_high);
}
static void dss_mgr_setup_fifos(struct omap_overlay_manager *mgr)
static void dss_mgr_setup_fifos(struct omap_overlay_manager *mgr,
bool use_fifo_merge)
{
struct omap_overlay *ovl;
struct mgr_priv_data *mp;
@ -908,10 +944,10 @@ static void dss_mgr_setup_fifos(struct omap_overlay_manager *mgr)
return;
list_for_each_entry(ovl, &mgr->overlays, list)
dss_ovl_setup_fifo(ovl);
dss_ovl_setup_fifo(ovl, use_fifo_merge);
}
static void dss_setup_fifos(void)
static void dss_setup_fifos(bool use_fifo_merge)
{
const int num_mgrs = omap_dss_get_num_overlay_managers();
struct omap_overlay_manager *mgr;
@ -919,15 +955,91 @@ static void dss_setup_fifos(void)
for (i = 0; i < num_mgrs; ++i) {
mgr = omap_dss_get_overlay_manager(i);
dss_mgr_setup_fifos(mgr);
dss_mgr_setup_fifos(mgr, use_fifo_merge);
}
}
static int get_num_used_managers(void)
{
const int num_mgrs = omap_dss_get_num_overlay_managers();
struct omap_overlay_manager *mgr;
struct mgr_priv_data *mp;
int i;
int enabled_mgrs;
enabled_mgrs = 0;
for (i = 0; i < num_mgrs; ++i) {
mgr = omap_dss_get_overlay_manager(i);
mp = get_mgr_priv(mgr);
if (!mp->enabled)
continue;
enabled_mgrs++;
}
return enabled_mgrs;
}
static int get_num_used_overlays(void)
{
const int num_ovls = omap_dss_get_num_overlays();
struct omap_overlay *ovl;
struct ovl_priv_data *op;
struct mgr_priv_data *mp;
int i;
int enabled_ovls;
enabled_ovls = 0;
for (i = 0; i < num_ovls; ++i) {
ovl = omap_dss_get_overlay(i);
op = get_ovl_priv(ovl);
if (!op->enabled && !op->enabling)
continue;
mp = get_mgr_priv(ovl->manager);
if (!mp->enabled)
continue;
enabled_ovls++;
}
return enabled_ovls;
}
static bool get_use_fifo_merge(void)
{
int enabled_mgrs = get_num_used_managers();
int enabled_ovls = get_num_used_overlays();
if (!dss_has_feature(FEAT_FIFO_MERGE))
return false;
/*
* In theory the only requirement for fifomerge is enabled_ovls <= 1.
* However, if we have two managers enabled and set/unset the fifomerge,
* we need to set the GO bits in particular sequence for the managers,
* and wait in between.
*
* This is rather difficult as new apply calls can happen at any time,
* so we simplify the problem by requiring also that enabled_mgrs <= 1.
* In practice this shouldn't matter, because when only one overlay is
* enabled, most likely only one output is enabled.
*/
return enabled_mgrs <= 1 && enabled_ovls <= 1;
}
int dss_mgr_enable(struct omap_overlay_manager *mgr)
{
struct mgr_priv_data *mp = get_mgr_priv(mgr);
unsigned long flags;
int r;
bool fifo_merge;
mutex_lock(&apply_lock);
@ -945,11 +1057,23 @@ int dss_mgr_enable(struct omap_overlay_manager *mgr)
goto err;
}
dss_setup_fifos();
/* step 1: setup fifos/fifomerge before enabling the manager */
fifo_merge = get_use_fifo_merge();
dss_setup_fifos(fifo_merge);
dss_apply_fifo_merge(fifo_merge);
dss_write_regs();
dss_set_go_bits();
spin_unlock_irqrestore(&data_lock, flags);
/* wait until fifo config is in */
wait_pending_extra_info_updates();
/* step 2: enable the manager */
spin_lock_irqsave(&data_lock, flags);
if (!mgr_manual_update(mgr))
mp->updating = true;
@ -974,6 +1098,7 @@ void dss_mgr_disable(struct omap_overlay_manager *mgr)
{
struct mgr_priv_data *mp = get_mgr_priv(mgr);
unsigned long flags;
bool fifo_merge;
mutex_lock(&apply_lock);
@ -988,8 +1113,16 @@ void dss_mgr_disable(struct omap_overlay_manager *mgr)
mp->updating = false;
mp->enabled = false;
fifo_merge = get_use_fifo_merge();
dss_setup_fifos(fifo_merge);
dss_apply_fifo_merge(fifo_merge);
dss_write_regs();
dss_set_go_bits();
spin_unlock_irqrestore(&data_lock, flags);
wait_pending_extra_info_updates();
out:
mutex_unlock(&apply_lock);
}
@ -1241,6 +1374,7 @@ int dss_ovl_enable(struct omap_overlay *ovl)
{
struct ovl_priv_data *op = get_ovl_priv(ovl);
unsigned long flags;
bool fifo_merge;
int r;
mutex_lock(&apply_lock);
@ -1266,7 +1400,22 @@ int dss_ovl_enable(struct omap_overlay *ovl)
goto err2;
}
dss_setup_fifos();
/* step 1: configure fifos/fifomerge for currently enabled ovls */
fifo_merge = get_use_fifo_merge();
dss_setup_fifos(fifo_merge);
dss_apply_fifo_merge(fifo_merge);
dss_write_regs();
dss_set_go_bits();
spin_unlock_irqrestore(&data_lock, flags);
/* wait for fifo configs to go in */
wait_pending_extra_info_updates();
/* step 2: enable the overlay */
spin_lock_irqsave(&data_lock, flags);
op->enabling = false;
dss_apply_ovl_enable(ovl, true);
@ -1294,6 +1443,7 @@ int dss_ovl_disable(struct omap_overlay *ovl)
{
struct ovl_priv_data *op = get_ovl_priv(ovl);
unsigned long flags;
bool fifo_merge;
int r;
mutex_lock(&apply_lock);
@ -1308,9 +1458,11 @@ int dss_ovl_disable(struct omap_overlay *ovl)
goto err;
}
/* step 1: disable the overlay */
spin_lock_irqsave(&data_lock, flags);
dss_apply_ovl_enable(ovl, false);
dss_write_regs();
dss_set_go_bits();
@ -1319,6 +1471,21 @@ int dss_ovl_disable(struct omap_overlay *ovl)
/* wait for the overlay to be disabled */
wait_pending_extra_info_updates();
/* step 2: configure fifos/fifomerge */
spin_lock_irqsave(&data_lock, flags);
fifo_merge = get_use_fifo_merge();
dss_setup_fifos(fifo_merge);
dss_apply_fifo_merge(fifo_merge);
dss_write_regs();
dss_set_go_bits();
spin_unlock_irqrestore(&data_lock, flags);
/* wait for fifo config to go in */
wait_pending_extra_info_updates();
mutex_unlock(&apply_lock);
return 0;

135
drivers/video/omap2/dss/core.c
View File

@ -183,42 +183,6 @@ static int omap_dss_probe(struct platform_device *pdev)
dss_init_overlay_managers(pdev);
dss_init_overlays(pdev);
r = dss_init_platform_driver();
if (r) {
DSSERR("Failed to initialize DSS platform driver\n");
goto err_dss;
}
r = dispc_init_platform_driver();
if (r) {
DSSERR("Failed to initialize dispc platform driver\n");
goto err_dispc;
}
r = rfbi_init_platform_driver();
if (r) {
DSSERR("Failed to initialize rfbi platform driver\n");
goto err_rfbi;
}
r = venc_init_platform_driver();
if (r) {
DSSERR("Failed to initialize venc platform driver\n");
goto err_venc;
}
r = dsi_init_platform_driver();
if (r) {
DSSERR("Failed to initialize DSI platform driver\n");
goto err_dsi;
}
r = hdmi_init_platform_driver();
if (r) {
DSSERR("Failed to initialize hdmi\n");
goto err_hdmi;
}
r = dss_initialize_debugfs();
if (r)
goto err_debugfs;
@ -246,18 +210,6 @@ static int omap_dss_probe(struct platform_device *pdev)
err_register:
dss_uninitialize_debugfs();
err_debugfs:
hdmi_uninit_platform_driver();
err_hdmi:
dsi_uninit_platform_driver();
err_dsi:
venc_uninit_platform_driver();
err_venc:
dispc_uninit_platform_driver();
err_dispc:
rfbi_uninit_platform_driver();
err_rfbi:
dss_uninit_platform_driver();
err_dss:
return r;
}
@ -269,13 +221,6 @@ static int omap_dss_remove(struct platform_device *pdev)
dss_uninitialize_debugfs();
hdmi_uninit_platform_driver();
dsi_uninit_platform_driver();
venc_uninit_platform_driver();
rfbi_uninit_platform_driver();
dispc_uninit_platform_driver();
dss_uninit_platform_driver();
dss_uninit_overlays(pdev);
dss_uninit_overlay_managers(pdev);
@ -525,6 +470,80 @@ static int omap_dss_bus_register(void)
/* INIT */
static int __init omap_dss_register_drivers(void)
{
int r;
r = platform_driver_register(&omap_dss_driver);
if (r)
return r;
r = dss_init_platform_driver();
if (r) {
DSSERR("Failed to initialize DSS platform driver\n");
goto err_dss;
}
r = dispc_init_platform_driver();
if (r) {
DSSERR("Failed to initialize dispc platform driver\n");
goto err_dispc;
}
r = rfbi_init_platform_driver();
if (r) {
DSSERR("Failed to initialize rfbi platform driver\n");
goto err_rfbi;
}
r = venc_init_platform_driver();
if (r) {
DSSERR("Failed to initialize venc platform driver\n");
goto err_venc;
}
r = dsi_init_platform_driver();
if (r) {
DSSERR("Failed to initialize DSI platform driver\n");
goto err_dsi;
}
r = hdmi_init_platform_driver();
if (r) {
DSSERR("Failed to initialize hdmi\n");
goto err_hdmi;
}
return 0;
err_hdmi:
dsi_uninit_platform_driver();
err_dsi:
venc_uninit_platform_driver();
err_venc:
rfbi_uninit_platform_driver();
err_rfbi:
dispc_uninit_platform_driver();
err_dispc:
dss_uninit_platform_driver();
err_dss:
platform_driver_unregister(&omap_dss_driver);
return r;
}
static void __exit omap_dss_unregister_drivers(void)
{
hdmi_uninit_platform_driver();
dsi_uninit_platform_driver();
venc_uninit_platform_driver();
rfbi_uninit_platform_driver();
dispc_uninit_platform_driver();
dss_uninit_platform_driver();
platform_driver_unregister(&omap_dss_driver);
}
#ifdef CONFIG_OMAP2_DSS_MODULE
static void omap_dss_bus_unregister(void)
{
@ -541,7 +560,7 @@ static int __init omap_dss_init(void)
if (r)
return r;
r = platform_driver_register(&omap_dss_driver);
r = omap_dss_register_drivers();
if (r) {
omap_dss_bus_unregister();
return r;
@ -562,7 +581,7 @@ static void __exit omap_dss_exit(void)
core.vdds_sdi_reg = NULL;
}
platform_driver_unregister(&omap_dss_driver);
omap_dss_unregister_drivers();
omap_dss_bus_unregister();
}
@ -577,7 +596,7 @@ static int __init omap_dss_init(void)
static int __init omap_dss_init2(void)
{
return platform_driver_register(&omap_dss_driver);
return omap_dss_register_drivers();
}
core_initcall(omap_dss_init);

121
drivers/video/omap2/dss/dispc.c
View File

@ -37,7 +37,6 @@
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <plat/sram.h>
#include <plat/clock.h>
#include <video/omapdss.h>
@ -736,11 +735,11 @@ static void dispc_ovl_set_color_mode(enum omap_plane plane,
switch (color_mode) {
case OMAP_DSS_COLOR_NV12:
m = 0x0; break;
case OMAP_DSS_COLOR_RGB12U:
case OMAP_DSS_COLOR_RGBX16:
m = 0x1; break;
case OMAP_DSS_COLOR_RGBA16:
m = 0x2; break;
case OMAP_DSS_COLOR_RGBX16:
case OMAP_DSS_COLOR_RGB12U:
m = 0x4; break;
case OMAP_DSS_COLOR_ARGB16:
m = 0x5; break;
@ -789,9 +788,9 @@ static void dispc_ovl_set_color_mode(enum omap_plane plane,
m = 0x8; break;
case OMAP_DSS_COLOR_RGB24P:
m = 0x9; break;
case OMAP_DSS_COLOR_YUV2:
case OMAP_DSS_COLOR_RGBX16:
m = 0xa; break;
case OMAP_DSS_COLOR_UYVY:
case OMAP_DSS_COLOR_RGBA16:
m = 0xb; break;
case OMAP_DSS_COLOR_ARGB32:
m = 0xc; break;
@ -909,7 +908,7 @@ static void dispc_configure_burst_sizes(void)
dispc_ovl_set_burst_size(i, burst_size);
}
u32 dispc_ovl_get_burst_size(enum omap_plane plane)
static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
{
unsigned unit = dss_feat_get_burst_size_unit();
/* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
@ -1018,7 +1017,7 @@ static void dispc_read_plane_fifo_sizes(void)
}
}
u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
{
return dispc.fifo_size[plane];
}
@ -1039,13 +1038,13 @@ void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
plane,
REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
lo_start, lo_end),
lo_start, lo_end) * unit,
REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
hi_start, hi_end),
low, high);
hi_start, hi_end) * unit,
low * unit, high * unit);
dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
FLD_VAL(high, hi_start, hi_end) |
@ -1054,10 +1053,53 @@ void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
void dispc_enable_fifomerge(bool enable)
{
if (!dss_has_feature(FEAT_FIFO_MERGE)) {
WARN_ON(enable);
return;
}
DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
}
void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
u32 *fifo_low, u32 *fifo_high, bool use_fifomerge)
{
/*
* All sizes are in bytes. Both the buffer and burst are made of
* buffer_units, and the fifo thresholds must be buffer_unit aligned.
*/
unsigned buf_unit = dss_feat_get_buffer_size_unit();
unsigned ovl_fifo_size, total_fifo_size, burst_size;
int i;
burst_size = dispc_ovl_get_burst_size(plane);
ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
if (use_fifomerge) {
total_fifo_size = 0;
for (i = 0; i < omap_dss_get_num_overlays(); ++i)
total_fifo_size += dispc_ovl_get_fifo_size(i);
} else {
total_fifo_size = ovl_fifo_size;
}
/*
* We use the same low threshold for both fifomerge and non-fifomerge
* cases, but for fifomerge we calculate the high threshold using the
* combined fifo size
*/
if (dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
*fifo_low = ovl_fifo_size - burst_size * 2;
*fifo_high = total_fifo_size - burst_size;
} else {
*fifo_low = ovl_fifo_size - burst_size;
*fifo_high = total_fifo_size - buf_unit;
}
}
static void dispc_ovl_set_fir(enum omap_plane plane,
int hinc, int vinc,
enum omap_color_component color_comp)
@ -1651,6 +1693,7 @@ static unsigned long calc_fclk(enum omap_channel channel, u16 width,
u16 height, u16 out_width, u16 out_height)
{
unsigned int hf, vf;
unsigned long pclk = dispc_mgr_pclk_rate(channel);
/*
* FIXME how to determine the 'A' factor
@ -1673,13 +1716,16 @@ static unsigned long calc_fclk(enum omap_channel channel, u16 width,
if (cpu_is_omap24xx()) {
if (vf > 1 && hf > 1)
return dispc_mgr_pclk_rate(channel) * 4;
return pclk * 4;
else
return dispc_mgr_pclk_rate(channel) * 2;
return pclk * 2;
} else if (cpu_is_omap34xx()) {
return dispc_mgr_pclk_rate(channel) * vf * hf;
return pclk * vf * hf;
} else {
return dispc_mgr_pclk_rate(channel) * hf;
if (hf > 1)
return DIV_ROUND_UP(pclk, out_width) * width;
else
return pclk;
}
}
@ -3298,15 +3344,6 @@ static int omap_dispchw_probe(struct platform_device *pdev)
dispc.pdev = pdev;
clk = clk_get(&pdev->dev, "fck");
if (IS_ERR(clk)) {
DSSERR("can't get fck\n");
r = PTR_ERR(clk);
goto err_get_clk;
}
dispc.dss_clk = clk;
spin_lock_init(&dispc.irq_lock);
#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
@ -3319,29 +3356,38 @@ static int omap_dispchw_probe(struct platform_device *pdev)
dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
if (!dispc_mem) {
DSSERR("can't get IORESOURCE_MEM DISPC\n");
r = -EINVAL;
goto err_ioremap;
return -EINVAL;
}
dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
resource_size(dispc_mem));
if (!dispc.base) {
DSSERR("can't ioremap DISPC\n");
r = -ENOMEM;
goto err_ioremap;
return -ENOMEM;
}
dispc.irq = platform_get_irq(dispc.pdev, 0);
if (dispc.irq < 0) {
DSSERR("platform_get_irq failed\n");
r = -ENODEV;
goto err_irq;
return -ENODEV;
}
r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
"OMAP DISPC", dispc.pdev);
r = devm_request_irq(&pdev->dev, dispc.irq, omap_dispc_irq_handler,
IRQF_SHARED, "OMAP DISPC", dispc.pdev);
if (r < 0) {
DSSERR("request_irq failed\n");
goto err_irq;
return r;
}
clk = clk_get(&pdev->dev, "fck");
if (IS_ERR(clk)) {
DSSERR("can't get fck\n");
r = PTR_ERR(clk);
return r;
}
dispc.dss_clk = clk;
pm_runtime_enable(&pdev->dev);
r = dispc_runtime_get();
@ -3362,12 +3408,7 @@ static int omap_dispchw_probe(struct platform_device *pdev)
err_runtime_get:
pm_runtime_disable(&pdev->dev);
free_irq(dispc.irq, dispc.pdev);
err_irq:
iounmap(dispc.base);
err_ioremap:
clk_put(dispc.dss_clk);
err_get_clk:
return r;
}
@ -3377,8 +3418,6 @@ static int omap_dispchw_remove(struct platform_device *pdev)
clk_put(dispc.dss_clk);
free_irq(dispc.irq, dispc.pdev);
iounmap(dispc.base);
return 0;
}

9
drivers/video/omap2/dss/dispc_coefs.c
View File

@ -19,14 +19,13 @@
#include <linux/kernel.h>
#include <video/omapdss.h>
#include "dispc.h"
#define ARRAY_LEN(array) (sizeof(array) / sizeof(array[0]))
#include "dispc.h"
static const struct dispc_coef coef3_M8[8] = {
{ 0, 0, 128, 0, 0 },
{ 0, -4, 123, 9, 0 },
{ 0, -4, 108, 87, 0 },
{ 0, -4, 108, 24, 0 },
{ 0, -2, 87, 43, 0 },
{ 0, 64, 64, 0, 0 },
{ 0, 43, 87, -2, 0 },
@ -168,7 +167,7 @@ static const struct dispc_coef coef5_M8[8] = {
static const struct dispc_coef coef5_M9[8] = {
{ -3, 10, 114, 10, -3 },
{ -6, 24, 110, 0, -1 },
{ -6, 24, 111, 0, -1 },
{ -8, 40, 103, -7, 0 },
{ -11, 58, 91, -11, 1 },
{ 0, -12, 76, 76, -12 },
@ -319,7 +318,7 @@ const struct dispc_coef *dispc_ovl_get_scale_coef(int inc, int five_taps)
};
inc /= 128;
for (i = 0; i < ARRAY_LEN(coefs); ++i)
for (i = 0; i < ARRAY_SIZE(coefs); ++i)
if (inc >= coefs[i].Mmin && inc <= coefs[i].Mmax)
return five_taps ? coefs[i].coef_5 : coefs[i].coef_3;
return NULL;

10
drivers/video/omap2/dss/display.c
View File

@ -279,16 +279,6 @@ void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
}
EXPORT_SYMBOL(omapdss_default_get_resolution);
void default_get_overlay_fifo_thresholds(enum omap_plane plane,
u32 fifo_size, u32 burst_size,
u32 *fifo_low, u32 *fifo_high)
{
unsigned buf_unit = dss_feat_get_buffer_size_unit();
*fifo_high = fifo_size - buf_unit;
*fifo_low = fifo_size - burst_size;
}
int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev)
{
switch (dssdev->type) {

65
drivers/video/omap2/dss/dsi.c
View File

@ -4524,14 +4524,6 @@ int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
}
EXPORT_SYMBOL(omapdss_dsi_enable_te);
void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
u32 fifo_size, u32 burst_size,
u32 *fifo_low, u32 *fifo_high)
{
*fifo_high = fifo_size - burst_size;
*fifo_low = fifo_size - burst_size * 2;
}
int dsi_init_display(struct omap_dss_device *dssdev)
{
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
@ -4695,11 +4687,9 @@ static int omap_dsihw_probe(struct platform_device *dsidev)
struct resource *dsi_mem;
struct dsi_data *dsi;
dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
if (!dsi) {
r = -ENOMEM;
goto err_alloc;
}
dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL);
if (!dsi)
return -ENOMEM;
dsi->pdev = dsidev;
dsi_pdev_map[dsi_module] = dsidev;
@ -4722,12 +4712,6 @@ static int omap_dsihw_probe(struct platform_device *dsidev)
mutex_init(&dsi->lock);
sema_init(&dsi->bus_lock, 1);
r = dsi_get_clocks(dsidev);
if (r)
goto err_get_clk;
pm_runtime_enable(&dsidev->dev);
INIT_DELAYED_WORK_DEFERRABLE(&dsi->framedone_timeout_work,
dsi_framedone_timeout_work_callback);
@ -4739,27 +4723,27 @@ static int omap_dsihw_probe(struct platform_device *dsidev)
dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0);
if (!dsi_mem) {
DSSERR("can't get IORESOURCE_MEM DSI\n");
r = -EINVAL;
goto err_ioremap;
return -EINVAL;
}
dsi->base = ioremap(dsi_mem->start, resource_size(dsi_mem));
dsi->base = devm_ioremap(&dsidev->dev, dsi_mem->start,
resource_size(dsi_mem));
if (!dsi->base) {
DSSERR("can't ioremap DSI\n");
r = -ENOMEM;
goto err_ioremap;
return -ENOMEM;
}
dsi->irq = platform_get_irq(dsi->pdev, 0);
if (dsi->irq < 0) {
DSSERR("platform_get_irq failed\n");
r = -ENODEV;
goto err_get_irq;
return -ENODEV;
}
r = request_irq(dsi->irq, omap_dsi_irq_handler, IRQF_SHARED,
dev_name(&dsidev->dev), dsi->pdev);
r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler,
IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev);
if (r < 0) {
DSSERR("request_irq failed\n");
goto err_get_irq;
return r;
}
/* DSI VCs initialization */
@ -4771,9 +4755,15 @@ static int omap_dsihw_probe(struct platform_device *dsidev)
dsi_calc_clock_param_ranges(dsidev);
r = dsi_get_clocks(dsidev);
if (r)
return r;
pm_runtime_enable(&dsidev->dev);
r = dsi_runtime_get(dsidev);
if (r)
goto err_get_dsi;
goto err_runtime_get;
rev = dsi_read_reg(dsidev, DSI_REVISION);
dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
@ -4791,15 +4781,9 @@ static int omap_dsihw_probe(struct platform_device *dsidev)
return 0;
err_get_dsi:
free_irq(dsi->irq, dsi->pdev);
err_get_irq:
iounmap(dsi->base);
err_ioremap:
err_runtime_get:
pm_runtime_disable(&dsidev->dev);
err_get_clk:
kfree(dsi);
err_alloc:
dsi_put_clocks(dsidev);
return r;
}
@ -4823,11 +4807,6 @@ static int omap_dsihw_remove(struct platform_device *dsidev)
dsi->vdds_dsi_reg = NULL;
}
free_irq(dsi->irq, dsi->pdev);
iounmap(dsi->base);
kfree(dsi);
return 0;
}

17
drivers/video/omap2/dss/dss.c
View File

@ -748,19 +748,19 @@ static int omap_dsshw_probe(struct platform_device *pdev)
dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
if (!dss_mem) {
DSSERR("can't get IORESOURCE_MEM DSS\n");
r = -EINVAL;
goto err_ioremap;
return -EINVAL;
}
dss.base = ioremap(dss_mem->start, resource_size(dss_mem));
dss.base = devm_ioremap(&pdev->dev, dss_mem->start,
resource_size(dss_mem));
if (!dss.base) {
DSSERR("can't ioremap DSS\n");
r = -ENOMEM;
goto err_ioremap;
return -ENOMEM;
}
r = dss_get_clocks();
if (r)
goto err_clocks;
return r;
pm_runtime_enable(&pdev->dev);
@ -808,9 +808,6 @@ err_dpi:
err_runtime_get:
pm_runtime_disable(&pdev->dev);
dss_put_clocks();
err_clocks:
iounmap(dss.base);
err_ioremap:
return r;
}
@ -819,8 +816,6 @@ static int omap_dsshw_remove(struct platform_device *pdev)
dpi_exit();
sdi_exit();
iounmap(dss.base);
pm_runtime_disable(&pdev->dev);
dss_put_clocks();

10
drivers/video/omap2/dss/dss.h
View File

@ -202,9 +202,6 @@ void dss_uninit_device(struct platform_device *pdev,
struct omap_dss_device *dssdev);
bool dss_use_replication(struct omap_dss_device *dssdev,
enum omap_color_mode mode);
void default_get_overlay_fifo_thresholds(enum omap_plane plane,
u32 fifo_size, u32 burst_size,
u32 *fifo_low, u32 *fifo_high);
/* manager */
int dss_init_overlay_managers(struct platform_device *pdev);
@ -313,9 +310,6 @@ int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
bool enable_hsdiv);
void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes);
void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
u32 fifo_size, u32 burst_size,
u32 *fifo_low, u32 *fifo_high);
void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev);
void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev);
struct platform_device *dsi_get_dsidev_from_id(int module);
@ -429,8 +423,8 @@ int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
u32 dispc_ovl_get_fifo_size(enum omap_plane plane);
u32 dispc_ovl_get_burst_size(enum omap_plane plane);
void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
u32 *fifo_low, u32 *fifo_high, bool use_fifomerge);
int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
bool ilace, bool replication);
int dispc_ovl_enable(enum omap_plane plane, bool enable);

181
drivers/video/omap2/dss/dss_features.c
View File

@ -41,7 +41,8 @@ struct omap_dss_features {
const struct dss_reg_field *reg_fields;
const int num_reg_fields;
const u32 has_feature;
const enum dss_feat_id *features;
const int num_features;
const int num_mgrs;
const int num_ovls;
@ -189,7 +190,8 @@ static const enum omap_color_mode omap4_dss_supported_color_modes[] = {
OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32 |
OMAP_DSS_COLOR_ARGB16_1555,
OMAP_DSS_COLOR_ARGB16_1555 | OMAP_DSS_COLOR_RGBX16 |
OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_XRGB16_1555,
/* OMAP_DSS_VIDEO1 */
OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
@ -337,15 +339,110 @@ static const struct dss_param_range omap4_dss_param_range[] = {
[FEAT_PARAM_LINEWIDTH] = { 1, 2048 },
};
static const enum dss_feat_id omap2_dss_feat_list[] = {
FEAT_LCDENABLEPOL,
FEAT_LCDENABLESIGNAL,
FEAT_PCKFREEENABLE,
FEAT_FUNCGATED,
FEAT_ROWREPEATENABLE,
FEAT_RESIZECONF,
};
static const enum dss_feat_id omap3430_dss_feat_list[] = {
FEAT_LCDENABLEPOL,
FEAT_LCDENABLESIGNAL,
FEAT_PCKFREEENABLE,
FEAT_FUNCGATED,
FEAT_LINEBUFFERSPLIT,
FEAT_ROWREPEATENABLE,
FEAT_RESIZECONF,
FEAT_DSI_PLL_FREQSEL,
FEAT_DSI_REVERSE_TXCLKESC,
FEAT_VENC_REQUIRES_TV_DAC_CLK,
FEAT_CPR,
FEAT_PRELOAD,
FEAT_FIR_COEF_V,
FEAT_ALPHA_FIXED_ZORDER,
FEAT_FIFO_MERGE,
FEAT_OMAP3_DSI_FIFO_BUG,
};
static const enum dss_feat_id omap3630_dss_feat_list[] = {
FEAT_LCDENABLEPOL,
FEAT_LCDENABLESIGNAL,
FEAT_PCKFREEENABLE,
FEAT_FUNCGATED,
FEAT_LINEBUFFERSPLIT,
FEAT_ROWREPEATENABLE,
FEAT_RESIZECONF,
FEAT_DSI_PLL_PWR_BUG,
FEAT_DSI_PLL_FREQSEL,
FEAT_CPR,
FEAT_PRELOAD,
FEAT_FIR_COEF_V,
FEAT_ALPHA_FIXED_ZORDER,
FEAT_FIFO_MERGE,
FEAT_OMAP3_DSI_FIFO_BUG,
};
static const enum dss_feat_id omap4430_es1_0_dss_feat_list[] = {
FEAT_MGR_LCD2,
FEAT_CORE_CLK_DIV,
FEAT_LCD_CLK_SRC,
FEAT_DSI_DCS_CMD_CONFIG_VC,
FEAT_DSI_VC_OCP_WIDTH,
FEAT_DSI_GNQ,
FEAT_HANDLE_UV_SEPARATE,
FEAT_ATTR2,
FEAT_CPR,
FEAT_PRELOAD,
FEAT_FIR_COEF_V,
FEAT_ALPHA_FREE_ZORDER,
FEAT_FIFO_MERGE,
};
static const enum dss_feat_id omap4430_es2_0_1_2_dss_feat_list[] = {
FEAT_MGR_LCD2,
FEAT_CORE_CLK_DIV,
FEAT_LCD_CLK_SRC,
FEAT_DSI_DCS_CMD_CONFIG_VC,
FEAT_DSI_VC_OCP_WIDTH,
FEAT_DSI_GNQ,
FEAT_HDMI_CTS_SWMODE,
FEAT_HANDLE_UV_SEPARATE,
FEAT_ATTR2,
FEAT_CPR,
FEAT_PRELOAD,
FEAT_FIR_COEF_V,
FEAT_ALPHA_FREE_ZORDER,
FEAT_FIFO_MERGE,
};
static const enum dss_feat_id omap4_dss_feat_list[] = {
FEAT_MGR_LCD2,
FEAT_CORE_CLK_DIV,
FEAT_LCD_CLK_SRC,
FEAT_DSI_DCS_CMD_CONFIG_VC,
FEAT_DSI_VC_OCP_WIDTH,
FEAT_DSI_GNQ,
FEAT_HDMI_CTS_SWMODE,
FEAT_HDMI_AUDIO_USE_MCLK,
FEAT_HANDLE_UV_SEPARATE,
FEAT_ATTR2,
FEAT_CPR,
FEAT_PRELOAD,
FEAT_FIR_COEF_V,
FEAT_ALPHA_FREE_ZORDER,
FEAT_FIFO_MERGE,
};
/* OMAP2 DSS Features */
static const struct omap_dss_features omap2_dss_features = {
.reg_fields = omap2_dss_reg_fields,
.num_reg_fields = ARRAY_SIZE(omap2_dss_reg_fields),
.has_feature =
FEAT_LCDENABLEPOL | FEAT_LCDENABLESIGNAL |
FEAT_PCKFREEENABLE | FEAT_FUNCGATED |
FEAT_ROWREPEATENABLE | FEAT_RESIZECONF,
.features = omap2_dss_feat_list,
.num_features = ARRAY_SIZE(omap2_dss_feat_list),
.num_mgrs = 2,
.num_ovls = 3,
@ -363,14 +460,8 @@ static const struct omap_dss_features omap3430_dss_features = {
.reg_fields = omap3_dss_reg_fields,
.num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
.has_feature =
FEAT_LCDENABLEPOL |
FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
FEAT_FUNCGATED | FEAT_ROWREPEATENABLE |
FEAT_LINEBUFFERSPLIT | FEAT_RESIZECONF |
FEAT_DSI_PLL_FREQSEL | FEAT_DSI_REVERSE_TXCLKESC |
FEAT_VENC_REQUIRES_TV_DAC_CLK | FEAT_CPR | FEAT_PRELOAD |
FEAT_FIR_COEF_V | FEAT_ALPHA_FIXED_ZORDER,
.features = omap3430_dss_feat_list,
.num_features = ARRAY_SIZE(omap3430_dss_feat_list),
.num_mgrs = 2,
.num_ovls = 3,
@ -387,14 +478,8 @@ static const struct omap_dss_features omap3630_dss_features = {
.reg_fields = omap3_dss_reg_fields,
.num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
.has_feature =
FEAT_LCDENABLEPOL |
FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
FEAT_FUNCGATED |
FEAT_ROWREPEATENABLE | FEAT_LINEBUFFERSPLIT |
FEAT_RESIZECONF | FEAT_DSI_PLL_PWR_BUG |
FEAT_DSI_PLL_FREQSEL | FEAT_CPR | FEAT_PRELOAD |
FEAT_FIR_COEF_V | FEAT_ALPHA_FIXED_ZORDER,
.features = omap3630_dss_feat_list,
.num_features = ARRAY_SIZE(omap3630_dss_feat_list),
.num_mgrs = 2,
.num_ovls = 3,
@ -413,13 +498,27 @@ static const struct omap_dss_features omap4430_es1_0_dss_features = {
.reg_fields = omap4_dss_reg_fields,
.num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
.has_feature =
FEAT_MGR_LCD2 |
FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC |
FEAT_DSI_DCS_CMD_CONFIG_VC | FEAT_DSI_VC_OCP_WIDTH |
FEAT_DSI_GNQ | FEAT_HANDLE_UV_SEPARATE | FEAT_ATTR2 |
FEAT_CPR | FEAT_PRELOAD | FEAT_FIR_COEF_V |
FEAT_ALPHA_FREE_ZORDER,
.features = omap4430_es1_0_dss_feat_list,
.num_features = ARRAY_SIZE(omap4430_es1_0_dss_feat_list),
.num_mgrs = 3,
.num_ovls = 4,
.supported_displays = omap4_dss_supported_displays,
.supported_color_modes = omap4_dss_supported_color_modes,
.overlay_caps = omap4_dss_overlay_caps,
.clksrc_names = omap4_dss_clk_source_names,
.dss_params = omap4_dss_param_range,
.buffer_size_unit = 16,
.burst_size_unit = 16,
};
/* For OMAP4430 ES 2.0, 2.1 and 2.2 revisions */
static const struct omap_dss_features omap4430_es2_0_1_2_dss_features = {
.reg_fields = omap4_dss_reg_fields,
.num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
.features = omap4430_es2_0_1_2_dss_feat_list,
.num_features = ARRAY_SIZE(omap4430_es2_0_1_2_dss_feat_list),
.num_mgrs = 3,
.num_ovls = 4,
@ -437,13 +536,8 @@ static const struct omap_dss_features omap4_dss_features = {
.reg_fields = omap4_dss_reg_fields,
.num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
.has_feature =
FEAT_MGR_LCD2 |
FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC |
FEAT_DSI_DCS_CMD_CONFIG_VC | FEAT_DSI_VC_OCP_WIDTH |
FEAT_DSI_GNQ | FEAT_HDMI_CTS_SWMODE |
FEAT_HANDLE_UV_SEPARATE | FEAT_ATTR2 | FEAT_CPR |
FEAT_PRELOAD | FEAT_FIR_COEF_V | FEAT_ALPHA_FREE_ZORDER,
.features = omap4_dss_feat_list,
.num_features = ARRAY_SIZE(omap4_dss_feat_list),
.num_mgrs = 3,
.num_ovls = 4,
@ -547,7 +641,16 @@ u32 dss_feat_get_burst_size_unit(void)
/* DSS has_feature check */
bool dss_has_feature(enum dss_feat_id id)
{
return omap_current_dss_features->has_feature & id;
int i;
const enum dss_feat_id *features = omap_current_dss_features->features;
const int num_features = omap_current_dss_features->num_features;
for (i = 0; i < num_features; i++) {
if (features[i] == id)
return true;
}
return false;
}
void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end)
@ -569,6 +672,10 @@ void dss_features_init(void)
omap_current_dss_features = &omap3430_dss_features;
else if (omap_rev() == OMAP4430_REV_ES1_0)
omap_current_dss_features = &omap4430_es1_0_dss_features;
else if (omap_rev() == OMAP4430_REV_ES2_0 ||
omap_rev() == OMAP4430_REV_ES2_1 ||
omap_rev() == OMAP4430_REV_ES2_2)
omap_current_dss_features = &omap4430_es2_0_1_2_dss_features;
else if (cpu_is_omap44xx())
omap_current_dss_features = &omap4_dss_features;
else

54
drivers/video/omap2/dss/dss_features.h
View File

@ -31,33 +31,37 @@
/* DSS has feature id */
enum dss_feat_id {
FEAT_LCDENABLEPOL = 1 << 3,
FEAT_LCDENABLESIGNAL = 1 << 4,
FEAT_PCKFREEENABLE = 1 << 5,
FEAT_FUNCGATED = 1 << 6,
FEAT_MGR_LCD2 = 1 << 7,
FEAT_LINEBUFFERSPLIT = 1 << 8,
FEAT_ROWREPEATENABLE = 1 << 9,
FEAT_RESIZECONF = 1 << 10,
FEAT_LCDENABLEPOL,
FEAT_LCDENABLESIGNAL,
FEAT_PCKFREEENABLE,
FEAT_FUNCGATED,
FEAT_MGR_LCD2,
FEAT_LINEBUFFERSPLIT,
FEAT_ROWREPEATENABLE,
FEAT_RESIZECONF,
/* Independent core clk divider */
FEAT_CORE_CLK_DIV = 1 << 11,
FEAT_LCD_CLK_SRC = 1 << 12,
FEAT_CORE_CLK_DIV,
FEAT_LCD_CLK_SRC,
/* DSI-PLL power command 0x3 is not working */
FEAT_DSI_PLL_PWR_BUG = 1 << 13,
FEAT_DSI_PLL_FREQSEL = 1 << 14,
FEAT_DSI_DCS_CMD_CONFIG_VC = 1 << 15,
FEAT_DSI_VC_OCP_WIDTH = 1 << 16,
FEAT_DSI_REVERSE_TXCLKESC = 1 << 17,
FEAT_DSI_GNQ = 1 << 18,
FEAT_HDMI_CTS_SWMODE = 1 << 19,
FEAT_HANDLE_UV_SEPARATE = 1 << 20,
FEAT_ATTR2 = 1 << 21,
FEAT_VENC_REQUIRES_TV_DAC_CLK = 1 << 22,
FEAT_CPR = 1 << 23,
FEAT_PRELOAD = 1 << 24,
FEAT_FIR_COEF_V = 1 << 25,
FEAT_ALPHA_FIXED_ZORDER = 1 << 26,
FEAT_ALPHA_FREE_ZORDER = 1 << 27,
FEAT_DSI_PLL_PWR_BUG,
FEAT_DSI_PLL_FREQSEL,
FEAT_DSI_DCS_CMD_CONFIG_VC,
FEAT_DSI_VC_OCP_WIDTH,
FEAT_DSI_REVERSE_TXCLKESC,
FEAT_DSI_GNQ,
FEAT_HDMI_CTS_SWMODE,
FEAT_HDMI_AUDIO_USE_MCLK,
FEAT_HANDLE_UV_SEPARATE,
FEAT_ATTR2,
FEAT_VENC_REQUIRES_TV_DAC_CLK,
FEAT_CPR,
FEAT_PRELOAD,
FEAT_FIR_COEF_V,
FEAT_ALPHA_FIXED_ZORDER,
FEAT_ALPHA_FREE_ZORDER,
FEAT_FIFO_MERGE,
/* An unknown HW bug causing the normal FIFO thresholds not to work */
FEAT_OMAP3_DSI_FIFO_BUG,
};
/* DSS register field id */

282
drivers/video/omap2/dss/hdmi.c
View File

@ -58,8 +58,6 @@
#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
#define OMAP_HDMI_TIMINGS_NB 34
#define HDMI_DEFAULT_REGN 16
#define HDMI_DEFAULT_REGM2 1
@ -68,8 +66,6 @@ static struct {
struct omap_display_platform_data *pdata;
struct platform_device *pdev;
struct hdmi_ip_data ip_data;
int code;
int mode;
struct clk *sys_clk;
} hdmi;
@ -88,77 +84,46 @@ static struct {
* map it to corresponding CEA or VESA index.
*/
static const struct hdmi_timings cea_vesa_timings[OMAP_HDMI_TIMINGS_NB] = {
{ {640, 480, 25200, 96, 16, 48, 2, 10, 33} , 0 , 0},
{ {1280, 720, 74250, 40, 440, 220, 5, 5, 20}, 1, 1},
{ {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1},
{ {720, 480, 27027, 62, 16, 60, 6, 9, 30}, 0, 0},
{ {2880, 576, 108000, 256, 48, 272, 5, 5, 39}, 0, 0},
{ {1440, 240, 27027, 124, 38, 114, 3, 4, 15}, 0, 0},
{ {1440, 288, 27000, 126, 24, 138, 3, 2, 19}, 0, 0},
{ {1920, 540, 74250, 44, 528, 148, 5, 2, 15}, 1, 1},
{ {1920, 540, 74250, 44, 88, 148, 5, 2, 15}, 1, 1},
{ {1920, 1080, 148500, 44, 88, 148, 5, 4, 36}, 1, 1},
{ {720, 576, 27000, 64, 12, 68, 5, 5, 39}, 0, 0},
{ {1440, 576, 54000, 128, 24, 136, 5, 5, 39}, 0, 0},
{ {1920, 1080, 148500, 44, 528, 148, 5, 4, 36}, 1, 1},
{ {2880, 480, 108108, 248, 64, 240, 6, 9, 30}, 0, 0},
{ {1920, 1080, 74250, 44, 638, 148, 5, 4, 36}, 1, 1},
/* VESA From Here */
{ {640, 480, 25175, 96, 16, 48, 2 , 11, 31}, 0, 0},
{ {800, 600, 40000, 128, 40, 88, 4 , 1, 23}, 1, 1},
{ {848, 480, 33750, 112, 16, 112, 8 , 6, 23}, 1, 1},
{ {1280, 768, 79500, 128, 64, 192, 7 , 3, 20}, 1, 0},
{ {1280, 800, 83500, 128, 72, 200, 6 , 3, 22}, 1, 0},
{ {1360, 768, 85500, 112, 64, 256, 6 , 3, 18}, 1, 1},
{ {1280, 960, 108000, 112, 96, 312, 3 , 1, 36}, 1, 1},
{ {1280, 1024, 108000, 112, 48, 248, 3 , 1, 38}, 1, 1},
{ {1024, 768, 65000, 136, 24, 160, 6, 3, 29}, 0, 0},
{ {1400, 1050, 121750, 144, 88, 232, 4, 3, 32}, 1, 0},
{ {1440, 900, 106500, 152, 80, 232, 6, 3, 25}, 1, 0},
{ {1680, 1050, 146250, 176 , 104, 280, 6, 3, 30}, 1, 0},
{ {1366, 768, 85500, 143, 70, 213, 3, 3, 24}, 1, 1},
{ {1920, 1080, 148500, 44, 148, 80, 5, 4, 36}, 1, 1},
{ {1280, 768, 68250, 32, 48, 80, 7, 3, 12}, 0, 1},
{ {1400, 1050, 101000, 32, 48, 80, 4, 3, 23}, 0, 1},
{ {1680, 1050, 119000, 32, 48, 80, 6, 3, 21}, 0, 1},
{ {1280, 800, 79500, 32, 48, 80, 6, 3, 14}, 0, 1},
{ {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1}
static const struct hdmi_config cea_timings[] = {
{ {640, 480, 25200, 96, 16, 48, 2, 10, 33, 0, 0, 0}, {1, HDMI_HDMI} },
{ {720, 480, 27027, 62, 16, 60, 6, 9, 30, 0, 0, 0}, {2, HDMI_HDMI} },
{ {1280, 720, 74250, 40, 110, 220, 5, 5, 20, 1, 1, 0}, {4, HDMI_HDMI} },
{ {1920, 540, 74250, 44, 88, 148, 5, 2, 15, 1, 1, 1}, {5, HDMI_HDMI} },
{ {1440, 240, 27027, 124, 38, 114, 3, 4, 15, 0, 0, 1}, {6, HDMI_HDMI} },
{ {1920, 1080, 148500, 44, 88, 148, 5, 4, 36, 1, 1, 0}, {16, HDMI_HDMI} },
{ {720, 576, 27000, 64, 12, 68, 5, 5, 39, 0, 0, 0}, {17, HDMI_HDMI} },
{ {1280, 720, 74250, 40, 440, 220, 5, 5, 20, 1, 1, 0}, {19, HDMI_HDMI} },
{ {1920, 540, 74250, 44, 528, 148, 5, 2, 15, 1, 1, 1}, {20, HDMI_HDMI} },
{ {1440, 288, 27000, 126, 24, 138, 3, 2, 19, 0, 0, 1}, {21, HDMI_HDMI} },
{ {1440, 576, 54000, 128, 24, 136, 5, 5, 39, 0, 0, 0}, {29, HDMI_HDMI} },
{ {1920, 1080, 148500, 44, 528, 148, 5, 4, 36, 1, 1, 0}, {31, HDMI_HDMI} },
{ {1920, 1080, 74250, 44, 638, 148, 5, 4, 36, 1, 1, 0}, {32, HDMI_HDMI} },
{ {2880, 480, 108108, 248, 64, 240, 6, 9, 30, 0, 0, 0}, {35, HDMI_HDMI} },
{ {2880, 576, 108000, 256, 48, 272, 5, 5, 39, 0, 0, 0}, {37, HDMI_HDMI} },
};
/*
* This is a static mapping array which maps the timing values
* with corresponding CEA / VESA code
*/
static const int code_index[OMAP_HDMI_TIMINGS_NB] = {
1, 19, 4, 2, 37, 6, 21, 20, 5, 16, 17, 29, 31, 35, 32,
/* <--15 CEA 17--> vesa*/
4, 9, 0xE, 0x17, 0x1C, 0x27, 0x20, 0x23, 0x10, 0x2A,
0X2F, 0x3A, 0X51, 0X52, 0x16, 0x29, 0x39, 0x1B
static const struct hdmi_config vesa_timings[] = {
/* VESA From Here */
{ {640, 480, 25175, 96, 16, 48, 2 , 11, 31, 0, 0, 0}, {4, HDMI_DVI} },
{ {800, 600, 40000, 128, 40, 88, 4 , 1, 23, 1, 1, 0}, {9, HDMI_DVI} },
{ {848, 480, 33750, 112, 16, 112, 8 , 6, 23, 1, 1, 0}, {0xE, HDMI_DVI} },
{ {1280, 768, 79500, 128, 64, 192, 7 , 3, 20, 1, 0, 0}, {0x17, HDMI_DVI} },
{ {1280, 800, 83500, 128, 72, 200, 6 , 3, 22, 1, 0, 0}, {0x1C, HDMI_DVI} },
{ {1360, 768, 85500, 112, 64, 256, 6 , 3, 18, 1, 1, 0}, {0x27, HDMI_DVI} },
{ {1280, 960, 108000, 112, 96, 312, 3 , 1, 36, 1, 1, 0}, {0x20, HDMI_DVI} },
{ {1280, 1024, 108000, 112, 48, 248, 3 , 1, 38, 1, 1, 0}, {0x23, HDMI_DVI} },
{ {1024, 768, 65000, 136, 24, 160, 6, 3, 29, 0, 0, 0}, {0x10, HDMI_DVI} },
{ {1400, 1050, 121750, 144, 88, 232, 4, 3, 32, 1, 0, 0}, {0x2A, HDMI_DVI} },
{ {1440, 900, 106500, 152, 80, 232, 6, 3, 25, 1, 0, 0}, {0x2F, HDMI_DVI} },
{ {1680, 1050, 146250, 176 , 104, 280, 6, 3, 30, 1, 0, 0}, {0x3A, HDMI_DVI} },
{ {1366, 768, 85500, 143, 70, 213, 3, 3, 24, 1, 1, 0}, {0x51, HDMI_DVI} },
{ {1920, 1080, 148500, 44, 148, 80, 5, 4, 36, 1, 1, 0}, {0x52, HDMI_DVI} },
{ {1280, 768, 68250, 32, 48, 80, 7, 3, 12, 0, 1, 0}, {0x16, HDMI_DVI} },
{ {1400, 1050, 101000, 32, 48, 80, 4, 3, 23, 0, 1, 0}, {0x29, HDMI_DVI} },
{ {1680, 1050, 119000, 32, 48, 80, 6, 3, 21, 0, 1, 0}, {0x39, HDMI_DVI} },
{ {1280, 800, 79500, 32, 48, 80, 6, 3, 14, 0, 1, 0}, {0x1B, HDMI_DVI} },
{ {1280, 720, 74250, 40, 110, 220, 5, 5, 20, 1, 1, 0}, {0x55, HDMI_DVI} }
};
/*
* This is reverse static mapping which maps the CEA / VESA code
* to the corresponding timing values
*/
static const int code_cea[39] = {
-1, 0, 3, 3, 2, 8, 5, 5, -1, -1,
-1, -1, -1, -1, -1, -1, 9, 10, 10, 1,
7, 6, 6, -1, -1, -1, -1, -1, -1, 11,
11, 12, 14, -1, -1, 13, 13, 4, 4
};
static const int code_vesa[85] = {
-1, -1, -1, -1, 15, -1, -1, -1, -1, 16,
-1, -1, -1, -1, 17, -1, 23, -1, -1, -1,
-1, -1, 29, 18, -1, -1, -1, 32, 19, -1,
-1, -1, 21, -1, -1, 22, -1, -1, -1, 20,
-1, 30, 24, -1, -1, -1, -1, 25, -1, -1,
-1, -1, -1, -1, -1, -1, -1, 31, 26, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, 27, 28, -1, 33};
static int hdmi_runtime_get(void)
{
int r;
@ -210,88 +175,89 @@ int hdmi_init_display(struct omap_dss_device *dssdev)
return 0;
}
static int get_timings_index(void)
static const struct hdmi_config *hdmi_find_timing(
const struct hdmi_config *timings_arr,
int len)
{
int code;
int i;
if (hdmi.mode == 0)
code = code_vesa[hdmi.code];
else
code = code_cea[hdmi.code];
if (code == -1) {
/* HDMI code 4 corresponds to 640 * 480 VGA */
hdmi.code = 4;
/* DVI mode 1 corresponds to HDMI 0 to DVI */
hdmi.mode = HDMI_DVI;
code = code_vesa[hdmi.code];
for (i = 0; i < len; i++) {
if (timings_arr[i].cm.code == hdmi.ip_data.cfg.cm.code)
return &timings_arr[i];
}
return code;
return NULL;
}
static const struct hdmi_config *hdmi_get_timings(void)
{
const struct hdmi_config *arr;
int len;
if (hdmi.ip_data.cfg.cm.mode == HDMI_DVI) {
arr = vesa_timings;
len = ARRAY_SIZE(vesa_timings);
} else {
arr = cea_timings;
len = ARRAY_SIZE(cea_timings);
}
return hdmi_find_timing(arr, len);
}
static bool hdmi_timings_compare(struct omap_video_timings *timing1,
const struct hdmi_video_timings *timing2)
{
int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync;
if ((timing2->pixel_clock == timing1->pixel_clock) &&
(timing2->x_res == timing1->x_res) &&
(timing2->y_res == timing1->y_res)) {
timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp;
timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp;
timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
DSSDBG("timing1_hsync = %d timing1_vsync = %d"\
"timing2_hsync = %d timing2_vsync = %d\n",
timing1_hsync, timing1_vsync,
timing2_hsync, timing2_vsync);
if ((timing1_hsync == timing2_hsync) &&
(timing1_vsync == timing2_vsync)) {
return true;
}
}
return false;
}
static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
{
int i = 0, code = -1, temp_vsync = 0, temp_hsync = 0;
int timing_vsync = 0, timing_hsync = 0;
struct hdmi_video_timings temp;
int i;
struct hdmi_cm cm = {-1};
DSSDBG("hdmi_get_code\n");
for (i = 0; i < OMAP_HDMI_TIMINGS_NB; i++) {
temp = cea_vesa_timings[i].timings;
if ((temp.pixel_clock == timing->pixel_clock) &&
(temp.x_res == timing->x_res) &&
(temp.y_res == timing->y_res)) {
temp_hsync = temp.hfp + temp.hsw + temp.hbp;
timing_hsync = timing->hfp + timing->hsw + timing->hbp;
temp_vsync = temp.vfp + temp.vsw + temp.vbp;
timing_vsync = timing->vfp + timing->vsw + timing->vbp;
DSSDBG("temp_hsync = %d , temp_vsync = %d"
"timing_hsync = %d, timing_vsync = %d\n",
temp_hsync, temp_hsync,
timing_hsync, timing_vsync);
if ((temp_hsync == timing_hsync) &&
(temp_vsync == timing_vsync)) {
code = i;
cm.code = code_index[i];
if (code < 14)
cm.mode = HDMI_HDMI;
else
cm.mode = HDMI_DVI;
DSSDBG("Hdmi_code = %d mode = %d\n",
cm.code, cm.mode);
break;
}
for (i = 0; i < ARRAY_SIZE(cea_timings); i++) {
if (hdmi_timings_compare(timing, &cea_timings[i].timings)) {
cm = cea_timings[i].cm;
goto end;
}
}
for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) {
if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) {
cm = vesa_timings[i].cm;
goto end;
}
}
return cm;
}
end: return cm;
static void update_hdmi_timings(struct hdmi_config *cfg,
struct omap_video_timings *timings, int code)
{
cfg->timings.timings.x_res = timings->x_res;
cfg->timings.timings.y_res = timings->y_res;
cfg->timings.timings.hbp = timings->hbp;
cfg->timings.timings.hfp = timings->hfp;
cfg->timings.timings.hsw = timings->hsw;
cfg->timings.timings.vbp = timings->vbp;
cfg->timings.timings.vfp = timings->vfp;
cfg->timings.timings.vsw = timings->vsw;
cfg->timings.timings.pixel_clock = timings->pixel_clock;
cfg->timings.vsync_pol = cea_vesa_timings[code].vsync_pol;
cfg->timings.hsync_pol = cea_vesa_timings[code].hsync_pol;
}
unsigned long hdmi_get_pixel_clock(void)
{
/* HDMI Pixel Clock in Mhz */
return hdmi.ip_data.cfg.timings.timings.pixel_clock * 1000;
return hdmi.ip_data.cfg.timings.pixel_clock * 1000;
}
static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
@ -312,24 +278,24 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
refclk = clkin / pi->regn;
/*
* multiplier is pixel_clk/ref_clk
* Multiplying by 100 to avoid fractional part removal
*/
pi->regm = (phy * 100 / (refclk)) / 100;
if (dssdev->clocks.hdmi.regm2 == 0)
pi->regm2 = HDMI_DEFAULT_REGM2;
else
pi->regm2 = dssdev->clocks.hdmi.regm2;
/*
* multiplier is pixel_clk/ref_clk
* Multiplying by 100 to avoid fractional part removal
*/
pi->regm = phy * pi->regm2 / refclk;
/*
* fractional multiplier is remainder of the difference between
* multiplier and actual phy(required pixel clock thus should be
* multiplied by 2^18(262144) divided by the reference clock
*/
mf = (phy - pi->regm * refclk) * 262144;
pi->regmf = mf / (refclk);
mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
pi->regmf = pi->regm2 * mf / refclk;
/*
* Dcofreq should be set to 1 if required pixel clock
@ -347,7 +313,8 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
static int hdmi_power_on(struct omap_dss_device *dssdev)
{
int r, code = 0;
int r;
const struct hdmi_config *timing;
struct omap_video_timings *p;
unsigned long phy;
@ -363,9 +330,16 @@ static int hdmi_power_on(struct omap_dss_device *dssdev)
dssdev->panel.timings.x_res,
dssdev->panel.timings.y_res);
code = get_timings_index();
update_hdmi_timings(&hdmi.ip_data.cfg, p, code);
timing = hdmi_get_timings();
if (timing == NULL) {
/* HDMI code 4 corresponds to 640 * 480 VGA */
hdmi.ip_data.cfg.cm.code = 4;
/* DVI mode 1 corresponds to HDMI 0 to DVI */
hdmi.ip_data.cfg.cm.mode = HDMI_DVI;
hdmi.ip_data.cfg = vesa_timings[0];
} else {
hdmi.ip_data.cfg = *timing;
}
phy = p->pixel_clock;
hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);
@ -385,8 +359,6 @@ static int hdmi_power_on(struct omap_dss_device *dssdev)
goto err;
}
hdmi.ip_data.cfg.cm.mode = hdmi.mode;
hdmi.ip_data.cfg.cm.code = hdmi.code;
hdmi.ip_data.ops->video_configure(&hdmi.ip_data);
/* Make selection of HDMI in DSS */
@ -453,8 +425,8 @@ void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev)
struct hdmi_cm cm;
cm = hdmi_get_code(&dssdev->panel.timings);
hdmi.code = cm.code;
hdmi.mode = cm.mode;
hdmi.ip_data.cfg.cm.code = cm.code;
hdmi.ip_data.cfg.cm.mode = cm.mode;
if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
int r;
@ -717,13 +689,15 @@ static int hdmi_audio_hw_params(struct snd_pcm_substream *substream,
if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) {
core_cfg.aud_par_busclk = 0;
core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_SW;
core_cfg.use_mclk = false;
core_cfg.use_mclk = dss_has_feature(FEAT_HDMI_AUDIO_USE_MCLK);
} else {
core_cfg.aud_par_busclk = (((128 * 31) - 1) << 8);
core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_HW;
core_cfg.use_mclk = true;
core_cfg.mclk_mode = HDMI_AUDIO_MCLK_128FS;
}
if (core_cfg.use_mclk)
core_cfg.mclk_mode = HDMI_AUDIO_MCLK_128FS;
core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH;
core_cfg.en_spdif = false;
/* Use sample frequency from channel status word */
@ -756,7 +730,7 @@ static int hdmi_audio_hw_params(struct snd_pcm_substream *substream,
static int hdmi_audio_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
if (!hdmi.mode) {
if (!hdmi.ip_data.cfg.cm.mode) {
pr_err("Current video settings do not support audio.\n");
return -EIO;
}

12
drivers/video/omap2/dss/manager.c
View File

@ -494,6 +494,11 @@ static int dss_mgr_wait_for_vsync(struct omap_overlay_manager *mgr)
{
unsigned long timeout = msecs_to_jiffies(500);
u32 irq;
int r;
r = dispc_runtime_get();
if (r)
return r;
if (mgr->device->type == OMAP_DISPLAY_TYPE_VENC) {
irq = DISPC_IRQ_EVSYNC_ODD;
@ -505,7 +510,12 @@ static int dss_mgr_wait_for_vsync(struct omap_overlay_manager *mgr)
else
irq = DISPC_IRQ_VSYNC2;
}
return omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout);
r = omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout);
dispc_runtime_put();
return r;
}
int dss_init_overlay_managers(struct platform_device *pdev)

36
drivers/video/omap2/dss/rfbi.c
View File

@ -922,35 +922,34 @@ static int omap_rfbihw_probe(struct platform_device *pdev)
rfbi_mem = platform_get_resource(rfbi.pdev, IORESOURCE_MEM, 0);
if (!rfbi_mem) {
DSSERR("can't get IORESOURCE_MEM RFBI\n");
r = -EINVAL;
goto err_ioremap;
return -EINVAL;
}
rfbi.base = ioremap(rfbi_mem->start, resource_size(rfbi_mem));
rfbi.base = devm_ioremap(&pdev->dev, rfbi_mem->start,
resource_size(rfbi_mem));
if (!rfbi.base) {
DSSERR("can't ioremap RFBI\n");
r = -ENOMEM;
goto err_ioremap;
return -ENOMEM;
}
pm_runtime_enable(&pdev->dev);
r = rfbi_runtime_get();
if (r)
goto err_get_rfbi;
msleep(10);
clk = clk_get(&pdev->dev, "ick");
if (IS_ERR(clk)) {
DSSERR("can't get ick\n");
r = PTR_ERR(clk);
goto err_get_ick;
return PTR_ERR(clk);
}
rfbi.l4_khz = clk_get_rate(clk) / 1000;
clk_put(clk);
pm_runtime_enable(&pdev->dev);
r = rfbi_runtime_get();
if (r)
goto err_runtime_get;
msleep(10);
rev = rfbi_read_reg(RFBI_REVISION);
dev_dbg(&pdev->dev, "OMAP RFBI rev %d.%d\n",
FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
@ -959,19 +958,14 @@ static int omap_rfbihw_probe(struct platform_device *pdev)
return 0;
err_get_ick:
rfbi_runtime_put();
err_get_rfbi:
err_runtime_get:
pm_runtime_disable(&pdev->dev);
iounmap(rfbi.base);
err_ioremap:
return r;
}
static int omap_rfbihw_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
iounmap(rfbi.base);
return 0;
}

56
drivers/video/omap2/dss/ti_hdmi.h
View File

@ -42,6 +42,7 @@ enum hdmi_clk_refsel {
HDMI_REFSEL_SYSCLK = 3
};
/* HDMI timing structure */
struct hdmi_video_timings {
u16 x_res;
u16 y_res;
@ -53,13 +54,9 @@ struct hdmi_video_timings {
u16 vsw;
u16 vfp;
u16 vbp;
};
/* HDMI timing structure */
struct hdmi_timings {
struct hdmi_video_timings timings;
int vsync_pol;
int hsync_pol;
bool vsync_pol;
bool hsync_pol;
bool interlace;
};
struct hdmi_cm {
@ -68,8 +65,7 @@ struct hdmi_cm {
};
struct hdmi_config {
struct hdmi_timings timings;
u16 interlace;
struct hdmi_video_timings timings;
struct hdmi_cm cm;
};
@ -117,6 +113,47 @@ struct ti_hdmi_ip_ops {
};
/*
* Refer to section 8.2 in HDMI 1.3 specification for
* details about infoframe databytes
*/
struct hdmi_core_infoframe_avi {
/* Y0, Y1 rgb,yCbCr */
u8 db1_format;
/* A0 Active information Present */
u8 db1_active_info;
/* B0, B1 Bar info data valid */
u8 db1_bar_info_dv;
/* S0, S1 scan information */
u8 db1_scan_info;
/* C0, C1 colorimetry */
u8 db2_colorimetry;
/* M0, M1 Aspect ratio (4:3, 16:9) */
u8 db2_aspect_ratio;
/* R0...R3 Active format aspect ratio */
u8 db2_active_fmt_ar;
/* ITC IT content. */
u8 db3_itc;
/* EC0, EC1, EC2 Extended colorimetry */
u8 db3_ec;
/* Q1, Q0 Quantization range */
u8 db3_q_range;
/* SC1, SC0 Non-uniform picture scaling */
u8 db3_nup_scaling;
/* VIC0..6 Video format identification */
u8 db4_videocode;
/* PR0..PR3 Pixel repetition factor */
u8 db5_pixel_repeat;
/* Line number end of top bar */
u16 db6_7_line_eoftop;
/* Line number start of bottom bar */
u16 db8_9_line_sofbottom;
/* Pixel number end of left bar */
u16 db10_11_pixel_eofleft;
/* Pixel number start of right bar */
u16 db12_13_pixel_sofright;
};
struct hdmi_ip_data {
void __iomem *base_wp; /* HDMI wrapper */
unsigned long core_sys_offset;
@ -126,6 +163,7 @@ struct hdmi_ip_data {
const struct ti_hdmi_ip_ops *ops;
struct hdmi_config cfg;
struct hdmi_pll_info pll_data;
struct hdmi_core_infoframe_avi avi_cfg;
/* ti_hdmi_4xxx_ip private data. These should be in a separate struct */
int hpd_gpio;

94
drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
View File

@ -587,12 +587,12 @@ static void hdmi_core_video_config(struct hdmi_ip_data *ip_data,
HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5);
}
static void hdmi_core_aux_infoframe_avi_config(struct hdmi_ip_data *ip_data,
struct hdmi_core_infoframe_avi info_avi)
static void hdmi_core_aux_infoframe_avi_config(struct hdmi_ip_data *ip_data)
{
u32 val;
char sum = 0, checksum = 0;
void __iomem *av_base = hdmi_av_base(ip_data);
struct hdmi_core_infoframe_avi info_avi = ip_data->avi_cfg;
sum += 0x82 + 0x002 + 0x00D;
hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_TYPE, 0x082);
@ -682,8 +682,7 @@ static void hdmi_core_av_packet_config(struct hdmi_ip_data *ip_data,
}
static void hdmi_wp_init(struct omap_video_timings *timings,
struct hdmi_video_format *video_fmt,
struct hdmi_video_interface *video_int)
struct hdmi_video_format *video_fmt)
{
pr_debug("Enter hdmi_wp_init\n");
@ -698,12 +697,6 @@ static void hdmi_wp_init(struct omap_video_timings *timings,
video_fmt->y_res = 0;
video_fmt->x_res = 0;
video_int->vsp = 0;
video_int->hsp = 0;
video_int->interlacing = 0;
video_int->tm = 0; /* HDMI_TIMING_SLAVE */
}
void ti_hdmi_4xxx_wp_video_start(struct hdmi_ip_data *ip_data, bool start)
@ -716,15 +709,15 @@ static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt,
{
pr_debug("Enter hdmi_wp_video_init_format\n");
video_fmt->y_res = param->timings.timings.y_res;
video_fmt->x_res = param->timings.timings.x_res;
video_fmt->y_res = param->timings.y_res;
video_fmt->x_res = param->timings.x_res;
timings->hbp = param->timings.timings.hbp;
timings->hfp = param->timings.timings.hfp;
timings->hsw = param->timings.timings.hsw;
timings->vbp = param->timings.timings.vbp;
timings->vfp = param->timings.timings.vfp;
timings->vsw = param->timings.timings.vsw;
timings->hbp = param->timings.hbp;
timings->hfp = param->timings.hfp;
timings->hsw = param->timings.hsw;
timings->vbp = param->timings.vbp;
timings->vfp = param->timings.vfp;
timings->vsw = param->timings.vsw;
}
static void hdmi_wp_video_config_format(struct hdmi_ip_data *ip_data,
@ -740,17 +733,16 @@ static void hdmi_wp_video_config_format(struct hdmi_ip_data *ip_data,
hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_SIZE, l);
}
static void hdmi_wp_video_config_interface(struct hdmi_ip_data *ip_data,
struct hdmi_video_interface *video_int)
static void hdmi_wp_video_config_interface(struct hdmi_ip_data *ip_data)
{
u32 r;
pr_debug("Enter hdmi_wp_video_config_interface\n");
r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG);
r = FLD_MOD(r, video_int->vsp, 7, 7);
r = FLD_MOD(r, video_int->hsp, 6, 6);
r = FLD_MOD(r, video_int->interlacing, 3, 3);
r = FLD_MOD(r, video_int->tm, 1, 0);
r = FLD_MOD(r, ip_data->cfg.timings.vsync_pol, 7, 7);
r = FLD_MOD(r, ip_data->cfg.timings.hsync_pol, 6, 6);
r = FLD_MOD(r, ip_data->cfg.timings.interlace, 3, 3);
r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */
hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, r);
}
@ -778,15 +770,13 @@ void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data)
/* HDMI */
struct omap_video_timings video_timing;
struct hdmi_video_format video_format;
struct hdmi_video_interface video_interface;
/* HDMI core */
struct hdmi_core_infoframe_avi avi_cfg;
struct hdmi_core_infoframe_avi avi_cfg = ip_data->avi_cfg;
struct hdmi_core_video_config v_core_cfg;
struct hdmi_core_packet_enable_repeat repeat_cfg;
struct hdmi_config *cfg = &ip_data->cfg;
hdmi_wp_init(&video_timing, &video_format,
&video_interface);
hdmi_wp_init(&video_timing, &video_format);
hdmi_core_init(&v_core_cfg,
&avi_cfg,
@ -801,12 +791,7 @@ void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data)
hdmi_wp_video_config_format(ip_data, &video_format);
video_interface.vsp = cfg->timings.vsync_pol;
video_interface.hsp = cfg->timings.hsync_pol;
video_interface.interlacing = cfg->interlace;
video_interface.tm = 1 ; /* HDMI_TIMING_MASTER_24BIT */
hdmi_wp_video_config_interface(ip_data, &video_interface);
hdmi_wp_video_config_interface(ip_data);
/*
* configure core video part
@ -848,7 +833,7 @@ void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data)
avi_cfg.db10_11_pixel_eofleft = 0;
avi_cfg.db12_13_pixel_sofright = 0;
hdmi_core_aux_infoframe_avi_config(ip_data, avi_cfg);
hdmi_core_aux_infoframe_avi_config(ip_data);
/* enable/repeat the infoframe */
repeat_cfg.avi_infoframe = HDMI_PACKETENABLE;
@ -1076,13 +1061,9 @@ void hdmi_core_audio_config(struct hdmi_ip_data *ip_data,
u32 r;
void __iomem *av_base = hdmi_av_base(ip_data);
/* audio clock recovery parameters */
r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL);
r = FLD_MOD(r, cfg->use_mclk, 2, 2);
r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1);
r = FLD_MOD(r, cfg->cts_mode, 0, 0);
hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r);
/*
* Parameters for generation of Audio Clock Recovery packets
*/
REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0);
REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0);
REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0);
@ -1094,14 +1075,6 @@ void hdmi_core_audio_config(struct hdmi_ip_data *ip_data,
REG_FLD_MOD(av_base,
HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0);
} else {
/*
* HDMI IP uses this configuration to divide the MCLK to
* update CTS value.
*/
REG_FLD_MOD(av_base,
HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0);
/* Configure clock for audio packets */
REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1,
cfg->aud_par_busclk, 7, 0);
REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2,
@ -1110,6 +1083,25 @@ void hdmi_core_audio_config(struct hdmi_ip_data *ip_data,
(cfg->aud_par_busclk >> 16), 7, 0);
}
/* Set ACR clock divisor */
REG_FLD_MOD(av_base,
HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0);
r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL);
/*
* Use TMDS clock for ACR packets. For devices that use
* the MCLK, this is the first part of the MCLK initialization.
*/
r = FLD_MOD(r, 0, 2, 2);
r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1);
r = FLD_MOD(r, cfg->cts_mode, 0, 0);
hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r);
/* For devices using MCLK, this completes its initialization. */
if (cfg->use_mclk)
REG_FLD_MOD(av_base, HDMI_CORE_AV_ACR_CTRL, 1, 2, 2);
/* Override of SPDIF sample frequency with value in I2S_CHST4 */
REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL,
cfg->fs_override, 1, 1);
@ -1205,7 +1197,7 @@ int hdmi_config_audio_acr(struct hdmi_ip_data *ip_data,
{
u32 r;
u32 deep_color = 0;
u32 pclk = ip_data->cfg.timings.timings.pixel_clock;
u32 pclk = ip_data->cfg.timings.pixel_clock;
if (n == NULL || cts == NULL)
return -EINVAL;

47
drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
View File

@ -446,46 +446,6 @@ struct hdmi_core_video_config {
enum hdmi_core_tclkselclkmult tclk_sel_clkmult;
};
/*
* Refer to section 8.2 in HDMI 1.3 specification for
* details about infoframe databytes
*/
struct hdmi_core_infoframe_avi {
/* Y0, Y1 rgb,yCbCr */
u8 db1_format;
/* A0 Active information Present */
u8 db1_active_info;
/* B0, B1 Bar info data valid */
u8 db1_bar_info_dv;
/* S0, S1 scan information */
u8 db1_scan_info;
/* C0, C1 colorimetry */
u8 db2_colorimetry;
/* M0, M1 Aspect ratio (4:3, 16:9) */
u8 db2_aspect_ratio;
/* R0...R3 Active format aspect ratio */
u8 db2_active_fmt_ar;
/* ITC IT content. */
u8 db3_itc;
/* EC0, EC1, EC2 Extended colorimetry */
u8 db3_ec;
/* Q1, Q0 Quantization range */
u8 db3_q_range;
/* SC1, SC0 Non-uniform picture scaling */
u8 db3_nup_scaling;
/* VIC0..6 Video format identification */
u8 db4_videocode;
/* PR0..PR3 Pixel repetition factor */
u8 db5_pixel_repeat;
/* Line number end of top bar */
u16 db6_7_line_eoftop;
/* Line number start of bottom bar */
u16 db8_9_line_sofbottom;
/* Pixel number end of left bar */
u16 db10_11_pixel_eofleft;
/* Pixel number start of right bar */
u16 db12_13_pixel_sofright;
};
/*
* Refer to section 8.2 in HDMI 1.3 specification for
* details about infoframe databytes
@ -517,13 +477,6 @@ struct hdmi_video_format {
u32 x_res; /* pixel per line */
};
struct hdmi_video_interface {
int vsp; /* Vsync polarity */
int hsp; /* Hsync polarity */
int interlacing;
int tm; /* Timing mode */
};
struct hdmi_audio_format {
enum hdmi_stereo_channels stereo_channels;
u8 active_chnnls_msk;

32
drivers/video/omap2/dss/venc.c
View File

@ -699,6 +699,11 @@ void venc_dump_regs(struct seq_file *s)
{
#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r))
if (cpu_is_omap44xx()) {
seq_printf(s, "VENC currently disabled on OMAP44xx\n");
return;
}
if (venc_runtime_get())
return;
@ -790,39 +795,41 @@ static int omap_venchw_probe(struct platform_device *pdev)
venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0);
if (!venc_mem) {
DSSERR("can't get IORESOURCE_MEM VENC\n");
r = -EINVAL;
goto err_ioremap;
return -EINVAL;
}
venc.base = ioremap(venc_mem->start, resource_size(venc_mem));
venc.base = devm_ioremap(&pdev->dev, venc_mem->start,
resource_size(venc_mem));
if (!venc.base) {
DSSERR("can't ioremap VENC\n");
r = -ENOMEM;
goto err_ioremap;
return -ENOMEM;
}
r = venc_get_clocks(pdev);
if (r)
goto err_get_clk;
return r;
pm_runtime_enable(&pdev->dev);
r = venc_runtime_get();
if (r)
goto err_get_venc;
goto err_runtime_get;
rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id);
venc_runtime_put();
return omap_dss_register_driver(&venc_driver);
r = omap_dss_register_driver(&venc_driver);
if (r)
goto err_reg_panel_driver;
err_get_venc:
return 0;
err_reg_panel_driver:
err_runtime_get:
pm_runtime_disable(&pdev->dev);
venc_put_clocks();
err_get_clk:
iounmap(venc.base);
err_ioremap:
return r;
}
@ -837,7 +844,6 @@ static int omap_venchw_remove(struct platform_device *pdev)
pm_runtime_disable(&pdev->dev);
venc_put_clocks();
iounmap(venc.base);
return 0;
}

2
drivers/video/omap2/omapfb/omapfb-ioctl.c
View File

@ -215,7 +215,7 @@ static int omapfb_setup_mem(struct fb_info *fbi, struct omapfb_mem_info *mi)
int r = 0, i;
size_t size;
if (mi->type > OMAPFB_MEMTYPE_MAX)
if (mi->type != OMAPFB_MEMTYPE_SDRAM)
return -EINVAL;
size = PAGE_ALIGN(mi->size);

101
drivers/video/omap2/omapfb/omapfb-main.c
View File

@ -1399,7 +1399,7 @@ static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size,
if (!paddr) {
DBG("allocating %lu bytes for fb %d\n", size, ofbi->id);
r = omap_vram_alloc(OMAP_VRAM_MEMTYPE_SDRAM, size, &paddr);
r = omap_vram_alloc(size, &paddr);
} else {
DBG("reserving %lu bytes at %lx for fb %d\n", size, paddr,
ofbi->id);
@ -1487,60 +1487,6 @@ static int omapfb_alloc_fbmem_display(struct fb_info *fbi, unsigned long size,
return omapfb_alloc_fbmem(fbi, size, paddr);
}
static enum omap_color_mode fb_format_to_dss_mode(enum omapfb_color_format fmt)
{
enum omap_color_mode mode;
switch (fmt) {
case OMAPFB_COLOR_RGB565:
mode = OMAP_DSS_COLOR_RGB16;
break;
case OMAPFB_COLOR_YUV422:
mode = OMAP_DSS_COLOR_YUV2;
break;
case OMAPFB_COLOR_CLUT_8BPP:
mode = OMAP_DSS_COLOR_CLUT8;
break;
case OMAPFB_COLOR_CLUT_4BPP:
mode = OMAP_DSS_COLOR_CLUT4;
break;
case OMAPFB_COLOR_CLUT_2BPP:
mode = OMAP_DSS_COLOR_CLUT2;
break;
case OMAPFB_COLOR_CLUT_1BPP:
mode = OMAP_DSS_COLOR_CLUT1;
break;
case OMAPFB_COLOR_RGB444:
mode = OMAP_DSS_COLOR_RGB12U;
break;
case OMAPFB_COLOR_YUY422:
mode = OMAP_DSS_COLOR_UYVY;
break;
case OMAPFB_COLOR_ARGB16:
mode = OMAP_DSS_COLOR_ARGB16;
break;
case OMAPFB_COLOR_RGB24U:
mode = OMAP_DSS_COLOR_RGB24U;
break;
case OMAPFB_COLOR_RGB24P:
mode = OMAP_DSS_COLOR_RGB24P;
break;
case OMAPFB_COLOR_ARGB32:
mode = OMAP_DSS_COLOR_ARGB32;
break;
case OMAPFB_COLOR_RGBA32:
mode = OMAP_DSS_COLOR_RGBA32;
break;
case OMAPFB_COLOR_RGBX32:
mode = OMAP_DSS_COLOR_RGBX32;
break;
default:
mode = -EINVAL;
}
return mode;
}
static int omapfb_parse_vram_param(const char *param, int max_entries,
unsigned long *sizes, unsigned long *paddrs)
{
@ -1614,23 +1560,6 @@ static int omapfb_allocate_all_fbs(struct omapfb2_device *fbdev)
memset(&vram_paddrs, 0, sizeof(vram_paddrs));
}
if (fbdev->dev->platform_data) {
struct omapfb_platform_data *opd;
opd = fbdev->dev->platform_data;
for (i = 0; i < opd->mem_desc.region_cnt; ++i) {
if (!vram_sizes[i]) {
unsigned long size;
unsigned long paddr;
size = opd->mem_desc.region[i].size;
paddr = opd->mem_desc.region[i].paddr;
vram_sizes[i] = size;
vram_paddrs[i] = paddr;
}
}
}
for (i = 0; i < fbdev->num_fbs; i++) {
/* allocate memory automatically only for fb0, or if
* excplicitly defined with vram or plat data option */
@ -1669,7 +1598,7 @@ int omapfb_realloc_fbmem(struct fb_info *fbi, unsigned long size, int type)
int old_type = rg->type;
int r;
if (type > OMAPFB_MEMTYPE_MAX)
if (type != OMAPFB_MEMTYPE_SDRAM)
return -EINVAL;
size = PAGE_ALIGN(size);
@ -1828,32 +1757,6 @@ static int omapfb_fb_init(struct omapfb2_device *fbdev, struct fb_info *fbi)
var->rotate = def_rotate;
/*
* Check if there is a default color format set in the board file,
* and use this format instead the default deducted from the
* display bpp.
*/
if (fbdev->dev->platform_data) {
struct omapfb_platform_data *opd;
int id = ofbi->id;
opd = fbdev->dev->platform_data;
if (opd->mem_desc.region[id].format_used) {
enum omap_color_mode mode;
enum omapfb_color_format format;
format = opd->mem_desc.region[id].format;
mode = fb_format_to_dss_mode(format);
if (mode < 0) {
r = mode;
goto err;
}
r = dss_mode_to_fb_mode(mode, var);
if (r < 0)
goto err;
}
}
if (display) {
u16 w, h;
int rotation = (var->rotate + ofbi->rotation[0]) % 4;

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