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mlx5-cleanup-2020-05-29 

Accumulated cleanup patches and sparse warning fixes for mlx5 driver.
 
 1) sync with mlx5-next branch
 
 2) Eli Cohen declares mpls_entry_encode() helper in mpls.h as suggested
 by Jakub Kicinski and David Ahern, and use it in mlx5
 
 3) Jesper Fixes xdp data_meta setup in mlx5
 
 4) Many sparse and build warnings cleanup
 -----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCAAdFiEEGhZs6bAKwk/OTgTpSD+KveBX+j4FAl7R3wcACgkQSD+KveBX
 +j6/ZQf/QD39naPeImfLjemkRK9L+TKbS4nU6wpUwf1jC33Wdm4HhkhsWEnR6C4l
 OwU/Pae3I9EtKP4gRE0W1o8h7zC9h4hY7+IKZOdyQ32iUY55PX/H25oqAiCj1NCM
 xzWpXOTwK/vkqmkCedAd+YpNdYlbOhfycr+KVPSsvFdaPqjzfNO1PJcLsUbAbzrX
 A+8pYdhUYTtx1N3YHJL5abLN6WzMAKxgwlm9GG8YCXACTJT6CBWWHGebVsC5TDUk
 Lj5hJj38mI8/3dcu6vWP0kLGVfRZo0HS/gpPGxbKQFpP+1uBYaRENAQONxkY++6S
 GDPix7ccvN+yNMlON893PC/Cogw3Yg==
 =WaCJ
 -----END PGP SIGNATURE-----

Merge tag 'mlx5-cleanup-2020-05-29' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux

Saeed Mahameed says:

====================
mlx5-cleanup-2020-05-29

Accumulated cleanup patches and sparse warning fixes for mlx5 driver.

1) sync with mlx5-next branch

2) Eli Cohen declares mpls_entry_encode() helper in mpls.h as suggested
by Jakub Kicinski and David Ahern, and use it in mlx5

3) Jesper Fixes xdp data_meta setup in mlx5

4) Many sparse and build warnings cleanup
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2020-05-30 17:53:57 -07:00
parent da4e15e31b eb24387183
commit 4300c7e7fe
28 changed files with 237 additions and 194 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/infiniband/hw/mlx5/flow.c
View File

@ -404,7 +404,10 @@ static bool mlx5_ib_modify_header_supported(struct mlx5_ib_dev *dev)
{
return MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
max_modify_header_actions) ||
MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, max_modify_header_actions);
MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
max_modify_header_actions) ||
MLX5_CAP_FLOWTABLE_RDMA_TX(dev->mdev,
max_modify_header_actions);
}
static int UVERBS_HANDLER(MLX5_IB_METHOD_FLOW_ACTION_CREATE_MODIFY_HEADER)(

47
drivers/infiniband/hw/mlx5/main.c
View File

@ -3698,12 +3698,13 @@ static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
if (!dest_num)
rule_dst = NULL;
} else {
if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)
flow_act.action |=
MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
if (is_egress)
flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
else
flow_act.action |=
dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
else if (dest_num)
flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
}
if ((spec->flow_context.flags & FLOW_CONTEXT_HAS_TAG) &&
@ -3747,30 +3748,6 @@ static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
}
static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
struct mlx5_ib_flow_prio *ft_prio,
struct ib_flow_attr *flow_attr,
struct mlx5_flow_destination *dst)
{
struct mlx5_ib_flow_handler *handler_dst = NULL;
struct mlx5_ib_flow_handler *handler = NULL;
handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
if (!IS_ERR(handler)) {
handler_dst = create_flow_rule(dev, ft_prio,
flow_attr, dst);
if (IS_ERR(handler_dst)) {
mlx5_del_flow_rules(handler->rule);
ft_prio->refcount--;
kfree(handler);
handler = handler_dst;
} else {
list_add(&handler_dst->list, &handler->list);
}
}
return handler;
}
enum {
LEFTOVERS_MC,
LEFTOVERS_UC,
@ -3974,15 +3951,11 @@ static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
}
if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
handler = create_dont_trap_rule(dev, ft_prio,
flow_attr, dst);
} else {
underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
mqp->underlay_qpn : 0;
handler = _create_flow_rule(dev, ft_prio, flow_attr,
dst, underlay_qpn, ucmd);
}
underlay_qpn = (mqp->flags & IB_QP_CREATE_SOURCE_QPN) ?
mqp->underlay_qpn :
0;
handler = _create_flow_rule(dev, ft_prio, flow_attr, dst,
underlay_qpn, ucmd);
} else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
handler = create_leftovers_rule(dev, ft_prio, flow_attr,

2
drivers/net/ethernet/mellanox/mlx5/core/Kconfig
View File

@ -84,7 +84,7 @@ config MLX5_CLS_ACT
default y
help
mlx5 ConnectX offloads support for TC classifier action (NET_CLS_ACT),
works in both native NIC mdoe and Switchdev SRIOV mode.
works in both native NIC mode and Switchdev SRIOV mode.
Actions get attached to a Hardware offloaded classifiers and are
invoked after a successful classification. Actions are used to
overwrite the classification result, instantly drop or redirect and/or

4
drivers/net/ethernet/mellanox/mlx5/core/accel/tls.c
View File

@ -56,8 +56,8 @@ void mlx5_accel_tls_del_flow(struct mlx5_core_dev *mdev, u32 swid,
mlx5_fpga_tls_del_flow(mdev, swid, GFP_KERNEL, direction_sx);
}
int mlx5_accel_tls_resync_rx(struct mlx5_core_dev *mdev, u32 handle, u32 seq,
u64 rcd_sn)
int mlx5_accel_tls_resync_rx(struct mlx5_core_dev *mdev, __be32 handle,
u32 seq, __be64 rcd_sn)
{
return mlx5_fpga_tls_resync_rx(mdev, handle, seq, rcd_sn);
}

8
drivers/net/ethernet/mellanox/mlx5/core/accel/tls.h
View File

@ -109,8 +109,8 @@ int mlx5_accel_tls_add_flow(struct mlx5_core_dev *mdev, void *flow,
bool direction_sx);
void mlx5_accel_tls_del_flow(struct mlx5_core_dev *mdev, u32 swid,
bool direction_sx);
int mlx5_accel_tls_resync_rx(struct mlx5_core_dev *mdev, u32 handle, u32 seq,
u64 rcd_sn);
int mlx5_accel_tls_resync_rx(struct mlx5_core_dev *mdev, __be32 handle,
u32 seq, __be64 rcd_sn);
bool mlx5_accel_is_tls_device(struct mlx5_core_dev *mdev);
u32 mlx5_accel_tls_device_caps(struct mlx5_core_dev *mdev);
int mlx5_accel_tls_init(struct mlx5_core_dev *mdev);
@ -125,8 +125,8 @@ mlx5_accel_tls_add_flow(struct mlx5_core_dev *mdev, void *flow,
bool direction_sx) { return -ENOTSUPP; }
static inline void mlx5_accel_tls_del_flow(struct mlx5_core_dev *mdev, u32 swid,
bool direction_sx) { }
static inline int mlx5_accel_tls_resync_rx(struct mlx5_core_dev *mdev, u32 handle,
u32 seq, u64 rcd_sn) { return 0; }
static inline int mlx5_accel_tls_resync_rx(struct mlx5_core_dev *mdev, __be32 handle,
u32 seq, __be64 rcd_sn) { return 0; }
static inline bool mlx5_accel_is_tls_device(struct mlx5_core_dev *mdev)
{
return mlx5_accel_is_ktls_device(mdev);

25
drivers/net/ethernet/mellanox/mlx5/core/cmd.c
View File

@ -1072,7 +1072,7 @@ static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
ds = ent->ts2 - ent->ts1;
op = MLX5_GET(mbox_in, in->first.data, opcode);
if (op < ARRAY_SIZE(cmd->stats)) {
if (op < MLX5_CMD_OP_MAX) {
stats = &cmd->stats[op];
spin_lock_irq(&stats->lock);
stats->sum += ds;
@ -1551,7 +1551,7 @@ static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool force
if (ent->callback) {
ds = ent->ts2 - ent->ts1;
if (ent->op < ARRAY_SIZE(cmd->stats)) {
if (ent->op < MLX5_CMD_OP_MAX) {
stats = &cmd->stats[ent->op];
spin_lock_irqsave(&stats->lock, flags);
stats->sum += ds;
@ -1936,6 +1936,11 @@ static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
cmd->alloc_dma);
}
static u16 cmdif_rev(struct mlx5_core_dev *dev)
{
return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
}
int mlx5_cmd_init(struct mlx5_core_dev *dev)
{
int size = sizeof(struct mlx5_cmd_prot_block);
@ -1955,10 +1960,16 @@ int mlx5_cmd_init(struct mlx5_core_dev *dev)
return -EINVAL;
}
cmd->pool = dma_pool_create("mlx5_cmd", dev->device, size, align, 0);
if (!cmd->pool)
cmd->stats = kvzalloc(MLX5_CMD_OP_MAX * sizeof(*cmd->stats), GFP_KERNEL);
if (!cmd->stats)
return -ENOMEM;
cmd->pool = dma_pool_create("mlx5_cmd", dev->device, size, align, 0);
if (!cmd->pool) {
err = -ENOMEM;
goto dma_pool_err;
}
err = alloc_cmd_page(dev, cmd);
if (err)
goto err_free_pool;
@ -1994,7 +2005,7 @@ int mlx5_cmd_init(struct mlx5_core_dev *dev)
spin_lock_init(&cmd->alloc_lock);
spin_lock_init(&cmd->token_lock);
for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
for (i = 0; i < MLX5_CMD_OP_MAX; i++)
spin_lock_init(&cmd->stats[i].lock);
sema_init(&cmd->sem, cmd->max_reg_cmds);
@ -2041,7 +2052,8 @@ err_free_page:
err_free_pool:
dma_pool_destroy(cmd->pool);
dma_pool_err:
kvfree(cmd->stats);
return err;
}
EXPORT_SYMBOL(mlx5_cmd_init);
@ -2055,6 +2067,7 @@ void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
destroy_msg_cache(dev);
free_cmd_page(dev, cmd);
dma_pool_destroy(cmd->pool);
kvfree(cmd->stats);
}
EXPORT_SYMBOL(mlx5_cmd_cleanup);

14
drivers/net/ethernet/mellanox/mlx5/core/debugfs.c
View File

@ -171,7 +171,7 @@ void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev)
cmd = &dev->priv.cmdif_debugfs;
*cmd = debugfs_create_dir("commands", dev->priv.dbg_root);
for (i = 0; i < ARRAY_SIZE(dev->cmd.stats); i++) {
for (i = 0; i < MLX5_CMD_OP_MAX; i++) {
stats = &dev->cmd.stats[i];
namep = mlx5_command_str(i);
if (strcmp(namep, "unknown command opcode")) {
@ -202,18 +202,23 @@ void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev)
static u64 qp_read_field(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp,
int index, int *is_str)
{
u32 out[MLX5_ST_SZ_BYTES(query_qp_out)] = {};
int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
u32 in[MLX5_ST_SZ_DW(query_qp_in)] = {};
u64 param = 0;
u32 *out;
int state;
u32 *qpc;
int err;
out = kzalloc(outlen, GFP_KERNEL);
if (!out)
return 0;
MLX5_SET(query_qp_in, in, opcode, MLX5_CMD_OP_QUERY_QP);
MLX5_SET(query_qp_in, in, qpn, qp->qpn);
err = mlx5_cmd_exec_inout(dev, query_qp, in, out);
if (err)
return 0;
goto out;
*is_str = 0;
@ -269,7 +274,8 @@ static u64 qp_read_field(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp,
param = MLX5_GET(qpc, qpc, remote_qpn);
break;
}
out:
kfree(out);
return param;
}

20
drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_mplsoudp.c
View File

@ -25,35 +25,21 @@ static int init_encap_attr(struct net_device *tunnel_dev,
return 0;
}
static inline __be32 mpls_label_id_field(__be32 label, u8 tos, u8 ttl)
{
u32 res;
/* mpls label is 32 bits long and construction as follows:
* 20 bits label
* 3 bits tos
* 1 bit bottom of stack. Since we support only one label, this bit is
* always set.
* 8 bits TTL
*/
res = be32_to_cpu(label) << 12 | 1 << 8 | (tos & 7) << 9 | ttl;
return cpu_to_be32(res);
}
static int generate_ip_tun_hdr(char buf[],
__u8 *ip_proto,
struct mlx5e_encap_entry *r)
{
const struct ip_tunnel_key *tun_key = &r->tun_info->key;
__be32 tun_id = tunnel_id_to_key32(tun_key->tun_id);
struct udphdr *udp = (struct udphdr *)(buf);
struct mpls_shim_hdr *mpls;
u32 tun_id;
tun_id = be32_to_cpu(tunnel_id_to_key32(tun_key->tun_id));
mpls = (struct mpls_shim_hdr *)(udp + 1);
*ip_proto = IPPROTO_UDP;
udp->dest = tun_key->tp_dst;
mpls->label_stack_entry = mpls_label_id_field(tun_id, tun_key->tos, tun_key->ttl);
*mpls = mpls_entry_encode(tun_id, tun_key->ttl, tun_key->tos, true);
return 0;
}

2
drivers/net/ethernet/mellanox/mlx5/core/en_accel/tls.c
View File

@ -167,7 +167,7 @@ static int mlx5e_tls_resync(struct net_device *netdev, struct sock *sk,
struct tls_context *tls_ctx = tls_get_ctx(sk);
struct mlx5e_priv *priv = netdev_priv(netdev);
struct mlx5e_tls_offload_context_rx *rx_ctx;
u64 rcd_sn = *(u64 *)rcd_sn_data;
__be64 rcd_sn = *(__be64 *)rcd_sn_data;
if (WARN_ON_ONCE(direction != TLS_OFFLOAD_CTX_DIR_RX))
return -EINVAL;

2
drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c
View File

@ -985,7 +985,7 @@ static int mlx5e_dcbnl_setbuffer(struct net_device *dev,
return err;
}
const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops = {
static const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops = {
.ieee_getets = mlx5e_dcbnl_ieee_getets,
.ieee_setets = mlx5e_dcbnl_ieee_setets,
.ieee_getmaxrate = mlx5e_dcbnl_ieee_getmaxrate,

2
drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
View File

@ -1056,8 +1056,8 @@ static void mlx5e_fill_xdp_buff(struct mlx5e_rq *rq, void *va, u16 headroom,
u32 len, struct xdp_buff *xdp)
{
xdp->data_hard_start = va;
xdp_set_data_meta_invalid(xdp);
xdp->data = va + headroom;
xdp_set_data_meta_invalid(xdp);
xdp->data_end = xdp->data + len;
xdp->rxq = &rq->xdp_rxq;
xdp->frame_sz = rq->buff.frame0_sz;

12
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
View File

@ -210,8 +210,8 @@ mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
fmask = headers_c + soffset;
fval = headers_v + soffset;
mask = cpu_to_be32(mask) >> (32 - (match_len * 8));
data = cpu_to_be32(data) >> (32 - (match_len * 8));
mask = (__force u32)(cpu_to_be32(mask)) >> (32 - (match_len * 8));
data = (__force u32)(cpu_to_be32(data)) >> (32 - (match_len * 8));
memcpy(fmask, &mask, match_len);
memcpy(fval, &data, match_len);
@ -1873,7 +1873,7 @@ enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
memchr_inv(opt->opt_data, 0, opt->length * 4)) {
*dont_care = false;
if (opt->opt_class != U16_MAX ||
if (opt->opt_class != htons(U16_MAX) ||
opt->type != U8_MAX) {
NL_SET_ERR_MSG(extack,
"Partial match of tunnel options in chain > 0 isn't supported");
@ -2815,10 +2815,10 @@ static int offload_pedit_fields(struct mlx5e_priv *priv,
continue;
if (f->field_bsize == 32) {
mask_be32 = (__be32)mask;
mask_be32 = (__force __be32)(mask);
mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
} else if (f->field_bsize == 16) {
mask_be32 = (__be32)mask;
mask_be32 = (__force __be32)(mask);
mask_be16 = *(__be16 *)&mask_be32;
mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
}
@ -3667,7 +3667,7 @@ static int mlx5e_attach_decap(struct mlx5e_priv *priv,
struct mlx5e_decap_entry *d;
struct mlx5e_decap_key key;
uintptr_t hash_key;
int err;
int err = 0;
parse_attr = attr->parse_attr;
if (sizeof(parse_attr->eth) > MLX5_CAP_ESW(priv->mdev, max_encap_header_size)) {

4
drivers/net/ethernet/mellanox/mlx5/core/fpga/tls.c
View File

@ -194,8 +194,8 @@ static void mlx5_fpga_tls_flow_to_cmd(void *flow, void *cmd)
MLX5_GET(tls_flow, flow, direction_sx));
}
int mlx5_fpga_tls_resync_rx(struct mlx5_core_dev *mdev, u32 handle, u32 seq,
u64 rcd_sn)
int mlx5_fpga_tls_resync_rx(struct mlx5_core_dev *mdev, __be32 handle,
u32 seq, __be64 rcd_sn)
{
struct mlx5_fpga_dma_buf *buf;
int size = sizeof(*buf) + MLX5_TLS_COMMAND_SIZE;

4
drivers/net/ethernet/mellanox/mlx5/core/fpga/tls.h
View File

@ -68,7 +68,7 @@ static inline u32 mlx5_fpga_tls_device_caps(struct mlx5_core_dev *mdev)
return mdev->fpga->tls->caps;
}
int mlx5_fpga_tls_resync_rx(struct mlx5_core_dev *mdev, u32 handle, u32 seq,
u64 rcd_sn);
int mlx5_fpga_tls_resync_rx(struct mlx5_core_dev *mdev, __be32 handle,
u32 seq, __be64 rcd_sn);
#endif /* __MLX5_FPGA_TLS_H__ */

4
drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c
View File

@ -781,6 +781,10 @@ static int mlx5_cmd_modify_header_alloc(struct mlx5_flow_root_namespace *ns,
max_actions = MLX5_CAP_ESW_INGRESS_ACL(dev, max_modify_header_actions);
table_type = FS_FT_ESW_INGRESS_ACL;
break;
case MLX5_FLOW_NAMESPACE_RDMA_TX:
max_actions = MLX5_CAP_FLOWTABLE_RDMA_TX(dev, max_modify_header_actions);
table_type = FS_FT_RDMA_TX;
break;
default:
return -EOPNOTSUPP;
}

116
drivers/net/ethernet/mellanox/mlx5/core/fs_core.c
View File

@ -254,7 +254,7 @@ static void del_sw_flow_group(struct fs_node *node);
static void del_sw_fte(struct fs_node *node);
static void del_sw_prio(struct fs_node *node);
static void del_sw_ns(struct fs_node *node);
/* Delete rule (destination) is special case that
/* Delete rule (destination) is special case that
* requires to lock the FTE for all the deletion process.
*/
static void del_sw_hw_rule(struct fs_node *node);
@ -379,6 +379,12 @@ static struct fs_prio *find_prio(struct mlx5_flow_namespace *ns,
return NULL;
}
static bool is_fwd_next_action(u32 action)
{
return action & (MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO |
MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_NS);
}
static bool check_valid_spec(const struct mlx5_flow_spec *spec)
{
int i;
@ -499,7 +505,7 @@ static void del_sw_hw_rule(struct fs_node *node)
fs_get_obj(rule, node);
fs_get_obj(fte, rule->node.parent);
trace_mlx5_fs_del_rule(rule);
if (rule->sw_action == MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO) {
if (is_fwd_next_action(rule->sw_action)) {
mutex_lock(&rule->dest_attr.ft->lock);
list_del(&rule->next_ft);
mutex_unlock(&rule->dest_attr.ft->lock);
@ -823,6 +829,36 @@ static struct mlx5_flow_table *find_prev_chained_ft(struct fs_prio *prio)
return find_closest_ft(prio, true);
}
static struct fs_prio *find_fwd_ns_prio(struct mlx5_flow_root_namespace *root,
struct mlx5_flow_namespace *ns)
{
struct mlx5_flow_namespace *root_ns = &root->ns;
struct fs_prio *iter_prio;
struct fs_prio *prio;
fs_get_obj(prio, ns->node.parent);
list_for_each_entry(iter_prio, &root_ns->node.children, node.list) {
if (iter_prio == prio &&
!list_is_last(&prio->node.children, &iter_prio->node.list))
return list_next_entry(iter_prio, node.list);
}
return NULL;
}
static struct mlx5_flow_table *find_next_fwd_ft(struct mlx5_flow_table *ft,
struct mlx5_flow_act *flow_act)
{
struct mlx5_flow_root_namespace *root = find_root(&ft->node);
struct fs_prio *prio;
if (flow_act->action & MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_NS)
prio = find_fwd_ns_prio(root, ft->ns);
else
fs_get_obj(prio, ft->node.parent);
return (prio) ? find_next_chained_ft(prio) : NULL;
}
static int connect_fts_in_prio(struct mlx5_core_dev *dev,
struct fs_prio *prio,
struct mlx5_flow_table *ft)
@ -973,6 +1009,10 @@ static int connect_fwd_rules(struct mlx5_core_dev *dev,
list_splice_init(&old_next_ft->fwd_rules, &new_next_ft->fwd_rules);
mutex_unlock(&old_next_ft->lock);
list_for_each_entry(iter, &new_next_ft->fwd_rules, next_ft) {
if ((iter->sw_action & MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_NS) &&
iter->ft->ns == new_next_ft->ns)
continue;
err = _mlx5_modify_rule_destination(iter, &dest);
if (err)
pr_err("mlx5_core: failed to modify rule to point on flow table %d\n",
@ -1074,6 +1114,7 @@ static struct mlx5_flow_table *__mlx5_create_flow_table(struct mlx5_flow_namespa
next_ft = unmanaged ? ft_attr->next_ft :
find_next_chained_ft(fs_prio);
ft->def_miss_action = ns->def_miss_action;
ft->ns = ns;
err = root->cmds->create_flow_table(root, ft, log_table_sz, next_ft);
if (err)
goto free_ft;
@ -1898,48 +1939,59 @@ mlx5_add_flow_rules(struct mlx5_flow_table *ft,
{
struct mlx5_flow_root_namespace *root = find_root(&ft->node);
static const struct mlx5_flow_spec zero_spec = {};
struct mlx5_flow_destination gen_dest = {};
struct mlx5_flow_destination *gen_dest = NULL;
struct mlx5_flow_table *next_ft = NULL;
struct mlx5_flow_handle *handle = NULL;
u32 sw_action = flow_act->action;
struct fs_prio *prio;
int i;
if (!spec)
spec = &zero_spec;
fs_get_obj(prio, ft->node.parent);
if (flow_act->action == MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO) {
if (!fwd_next_prio_supported(ft))
return ERR_PTR(-EOPNOTSUPP);
if (num_dest)
return ERR_PTR(-EINVAL);
mutex_lock(&root->chain_lock);
next_ft = find_next_chained_ft(prio);
if (next_ft) {
gen_dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
gen_dest.ft = next_ft;
dest = &gen_dest;
num_dest = 1;
flow_act->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
} else {
mutex_unlock(&root->chain_lock);
return ERR_PTR(-EOPNOTSUPP);
}
if (!is_fwd_next_action(sw_action))
return _mlx5_add_flow_rules(ft, spec, flow_act, dest, num_dest);
if (!fwd_next_prio_supported(ft))
return ERR_PTR(-EOPNOTSUPP);
mutex_lock(&root->chain_lock);
next_ft = find_next_fwd_ft(ft, flow_act);
if (!next_ft) {
handle = ERR_PTR(-EOPNOTSUPP);
goto unlock;
}
gen_dest = kcalloc(num_dest + 1, sizeof(*dest),
GFP_KERNEL);
if (!gen_dest) {
handle = ERR_PTR(-ENOMEM);
goto unlock;
}
for (i = 0; i < num_dest; i++)
gen_dest[i] = dest[i];
gen_dest[i].type =
MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
gen_dest[i].ft = next_ft;
dest = gen_dest;
num_dest++;
flow_act->action &= ~(MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO |
MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_NS);
flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
handle = _mlx5_add_flow_rules(ft, spec, flow_act, dest, num_dest);
if (IS_ERR(handle))
goto unlock;
if (sw_action == MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO) {
if (!IS_ERR_OR_NULL(handle) &&
(list_empty(&handle->rule[0]->next_ft))) {
mutex_lock(&next_ft->lock);
list_add(&handle->rule[0]->next_ft,
&next_ft->fwd_rules);
mutex_unlock(&next_ft->lock);
handle->rule[0]->sw_action = MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
}
mutex_unlock(&root->chain_lock);
if (list_empty(&handle->rule[num_dest - 1]->next_ft)) {
mutex_lock(&next_ft->lock);
list_add(&handle->rule[num_dest - 1]->next_ft,
&next_ft->fwd_rules);
mutex_unlock(&next_ft->lock);
handle->rule[num_dest - 1]->sw_action = sw_action;
handle->rule[num_dest - 1]->ft = ft;
}
unlock:
mutex_unlock(&root->chain_lock);
kfree(gen_dest);
return handle;
}
EXPORT_SYMBOL(mlx5_add_flow_rules);

2
drivers/net/ethernet/mellanox/mlx5/core/fs_core.h
View File

@ -138,6 +138,7 @@ struct fs_node {
struct mlx5_flow_rule {
struct fs_node node;
struct mlx5_flow_table *ft;
struct mlx5_flow_destination dest_attr;
/* next_ft should be accessed under chain_lock and only of
* destination type is FWD_NEXT_fT.
@ -175,6 +176,7 @@ struct mlx5_flow_table {
u32 flags;
struct rhltable fgs_hash;
enum mlx5_flow_table_miss_action def_miss_action;
struct mlx5_flow_namespace *ns;
};
struct mlx5_ft_underlay_qp {

5
drivers/net/ethernet/mellanox/mlx5/core/main.c
View File

@ -177,6 +177,11 @@ static struct mlx5_profile profile[] = {
#define FW_PRE_INIT_TIMEOUT_MILI 120000
#define FW_INIT_WARN_MESSAGE_INTERVAL 20000
static int fw_initializing(struct mlx5_core_dev *dev)
{
return ioread32be(&dev->iseg->initializing) >> 31;
}
static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
u32 warn_time_mili)
{

2
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c
View File

@ -1662,7 +1662,7 @@ dr_action_modify_check_field_limitation(struct mlx5dr_action *action,
}
static bool
dr_action_modify_check_is_ttl_modify(const u64 *sw_action)
dr_action_modify_check_is_ttl_modify(const void *sw_action)
{
u16 sw_field = MLX5_GET(set_action_in, sw_action, field);

5
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c
View File

@ -112,7 +112,7 @@ static u32 dr_ste_crc32_calc(const void *input_data, size_t length)
{
u32 crc = crc32(0, input_data, length);
return htonl(crc);
return (__force u32)htonl(crc);
}
u32 mlx5dr_ste_calc_hash_index(u8 *hw_ste_p, struct mlx5dr_ste_htbl *htbl)
@ -869,7 +869,7 @@ static void dr_ste_copy_mask_misc(char *mask, struct mlx5dr_match_misc *spec)
static void dr_ste_copy_mask_spec(char *mask, struct mlx5dr_match_spec *spec)
{
u32 raw_ip[4];
__be32 raw_ip[4];
spec->smac_47_16 = MLX5_GET(fte_match_set_lyr_2_4, mask, smac_47_16);
@ -961,7 +961,6 @@ static void dr_ste_copy_mask_misc2(char *mask, struct mlx5dr_match_misc2 *spec)
spec->metadata_reg_c_1 = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_c_1);
spec->metadata_reg_c_0 = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_c_0);
spec->metadata_reg_a = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_a);
spec->metadata_reg_b = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_b);
}
static void dr_ste_copy_mask_misc3(char *mask, struct mlx5dr_match_misc3 *spec)

3
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h
View File

@ -554,8 +554,7 @@ struct mlx5dr_match_misc2 {
u32 metadata_reg_c_1; /* metadata_reg_c_1 */
u32 metadata_reg_c_0; /* metadata_reg_c_0 */
u32 metadata_reg_a; /* metadata_reg_a */
u32 metadata_reg_b; /* metadata_reg_b */
u8 reserved_auto2[8];
u8 reserved_auto2[12];
};
struct mlx5dr_match_misc3 {

2
include/linux/mlx5/accel.h
View File

@ -76,7 +76,7 @@ struct aes_gcm_keymat {
struct mlx5_accel_esp_xfrm_attrs {
enum mlx5_accel_esp_action action;
u32 esn;
u32 spi;
__be32 spi;
u32 seq;
u32 tfc_pad;
u32 flags;

14
include/linux/mlx5/driver.h
View File

@ -201,7 +201,7 @@ struct mlx5_rsc_debug {
void *object;
enum dbg_rsc_type type;
struct dentry *root;
struct mlx5_field_desc fields[0];
struct mlx5_field_desc fields[];
};
enum mlx5_dev_event {
@ -298,7 +298,7 @@ struct mlx5_cmd {
struct mlx5_cmd_debug dbg;
struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
int checksum_disabled;
struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
struct mlx5_cmd_stats *stats;
};
struct mlx5_port_caps {
@ -832,11 +832,6 @@ static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
}
static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
{
return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
}
static inline u32 mlx5_base_mkey(const u32 key)
{
return key & 0xffffff00u;
@ -1028,11 +1023,6 @@ int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
u8 roce_version, u8 roce_l3_type, const u8 *gid,
const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
static inline int fw_initializing(struct mlx5_core_dev *dev)
{
return ioread32be(&dev->iseg->initializing) >> 31;
}
static inline u32 mlx5_mkey_to_idx(u32 mkey)
{
return mkey >> 8;

1
include/linux/mlx5/fs.h
View File

@ -42,6 +42,7 @@ enum {
MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO = 1 << 16,
MLX5_FLOW_CONTEXT_ACTION_ENCRYPT = 1 << 17,
MLX5_FLOW_CONTEXT_ACTION_DECRYPT = 1 << 18,
MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_NS = 1 << 19,
};
enum {

96
include/linux/mlx5/mlx5_ifc.h
View File

@ -584,9 +584,7 @@ struct mlx5_ifc_fte_match_set_misc2_bits {
u8 metadata_reg_a[0x20];
u8 metadata_reg_b[0x20];
u8 reserved_at_1c0[0x40];
u8 reserved_at_1a0[0x60];
};
struct mlx5_ifc_fte_match_set_misc3_bits {
@ -1210,7 +1208,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 reserved_at_99[0x2];
u8 log_max_qp[0x5];
u8 reserved_at_a0[0xb];
u8 reserved_at_a0[0x3];
u8 ece_support[0x1];
u8 reserved_at_a4[0x7];
u8 log_max_srq[0x5];
u8 reserved_at_b0[0x10];
@ -1703,7 +1703,7 @@ struct mlx5_ifc_wq_bits {
u8 reserved_at_140[0x4c0];
struct mlx5_ifc_cmd_pas_bits pas[0];
struct mlx5_ifc_cmd_pas_bits pas[];
};
struct mlx5_ifc_rq_num_bits {
@ -1921,7 +1921,7 @@ struct mlx5_ifc_resource_dump_menu_segment_bits {
u8 reserved_at_20[0x10];
u8 num_of_records[0x10];
struct mlx5_ifc_resource_dump_menu_record_bits record[0];
struct mlx5_ifc_resource_dump_menu_record_bits record[];
};
struct mlx5_ifc_resource_dump_resource_segment_bits {
@ -1933,7 +1933,7 @@ struct mlx5_ifc_resource_dump_resource_segment_bits {
u8 index2[0x20];
u8 payload[0][0x20];
u8 payload[][0x20];
};
struct mlx5_ifc_resource_dump_terminate_segment_bits {
@ -3010,7 +3010,7 @@ struct mlx5_ifc_flow_context_bits {
u8 reserved_at_1200[0x600];
union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
};
enum {
@ -3303,7 +3303,7 @@ struct mlx5_ifc_rqtc_bits {
u8 reserved_at_e0[0x6a0];
struct mlx5_ifc_rq_num_bits rq_num[0];
struct mlx5_ifc_rq_num_bits rq_num[];
};
enum {
@ -3415,7 +3415,7 @@ struct mlx5_ifc_nic_vport_context_bits {
u8 reserved_at_7e0[0x20];
u8 current_uc_mac_address[0][0x40];
u8 current_uc_mac_address[][0x40];
};
enum {
@ -4218,7 +4218,8 @@ struct mlx5_ifc_rts2rts_qp_out_bits {
u8 syndrome[0x20];
u8 reserved_at_40[0x40];
u8 reserved_at_40[0x20];
u8 ece[0x20];
};
struct mlx5_ifc_rts2rts_qp_in_bits {
@ -4235,7 +4236,7 @@ struct mlx5_ifc_rts2rts_qp_in_bits {
u8 opt_param_mask[0x20];
u8 reserved_at_a0[0x20];
u8 ece[0x20];
struct mlx5_ifc_qpc_bits qpc;
@ -4248,7 +4249,8 @@ struct mlx5_ifc_rtr2rts_qp_out_bits {
u8 syndrome[0x20];
u8 reserved_at_40[0x40];
u8 reserved_at_40[0x20];
u8 ece[0x20];
};
struct mlx5_ifc_rtr2rts_qp_in_bits {
@ -4265,7 +4267,7 @@ struct mlx5_ifc_rtr2rts_qp_in_bits {
u8 opt_param_mask[0x20];
u8 reserved_at_a0[0x20];
u8 ece[0x20];
struct mlx5_ifc_qpc_bits qpc;
@ -4338,7 +4340,7 @@ struct mlx5_ifc_query_xrc_srq_out_bits {
u8 reserved_at_280[0x600];
u8 pas[0][0x40];
u8 pas[][0x40];
};
struct mlx5_ifc_query_xrc_srq_in_bits {
@ -4616,7 +4618,7 @@ struct mlx5_ifc_query_srq_out_bits {
u8 reserved_at_280[0x600];
u8 pas[0][0x40];
u8 pas[][0x40];
};
struct mlx5_ifc_query_srq_in_bits {
@ -4817,7 +4819,8 @@ struct mlx5_ifc_query_qp_out_bits {
u8 syndrome[0x20];
u8 reserved_at_40[0x40];
u8 reserved_at_40[0x20];
u8 ece[0x20];
u8 opt_param_mask[0x20];
@ -4827,7 +4830,7 @@ struct mlx5_ifc_query_qp_out_bits {
u8 reserved_at_800[0x80];
u8 pas[0][0x40];
u8 pas[][0x40];
};
struct mlx5_ifc_query_qp_in_bits {
@ -5160,7 +5163,7 @@ struct mlx5_ifc_query_hca_vport_pkey_out_bits {
u8 reserved_at_40[0x40];
struct mlx5_ifc_pkey_bits pkey[0];
struct mlx5_ifc_pkey_bits pkey[];
};
struct mlx5_ifc_query_hca_vport_pkey_in_bits {
@ -5196,7 +5199,7 @@ struct mlx5_ifc_query_hca_vport_gid_out_bits {
u8 gids_num[0x10];
u8 reserved_at_70[0x10];
struct mlx5_ifc_array128_auto_bits gid[0];
struct mlx5_ifc_array128_auto_bits gid[];
};
struct mlx5_ifc_query_hca_vport_gid_in_bits {
@ -5464,7 +5467,7 @@ struct mlx5_ifc_query_flow_counter_out_bits {
u8 reserved_at_40[0x40];
struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
struct mlx5_ifc_traffic_counter_bits flow_statistics[];
};
struct mlx5_ifc_query_flow_counter_in_bits {
@ -5558,7 +5561,7 @@ struct mlx5_ifc_query_eq_out_bits {
u8 reserved_at_300[0x580];
u8 pas[0][0x40];
u8 pas[][0x40];
};
struct mlx5_ifc_query_eq_in_bits {
@ -5583,7 +5586,7 @@ struct mlx5_ifc_packet_reformat_context_in_bits {
u8 reserved_at_20[0x10];
u8 reformat_data[2][0x8];
u8 more_reformat_data[0][0x8];
u8 more_reformat_data[][0x8];
};
struct mlx5_ifc_query_packet_reformat_context_out_bits {
@ -5594,7 +5597,7 @@ struct mlx5_ifc_query_packet_reformat_context_out_bits {
u8 reserved_at_40[0xa0];
struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
};
struct mlx5_ifc_query_packet_reformat_context_in_bits {
@ -5833,7 +5836,7 @@ struct mlx5_ifc_query_cq_out_bits {
u8 reserved_at_280[0x600];
u8 pas[0][0x40];
u8 pas[][0x40];
};
struct mlx5_ifc_query_cq_in_bits {
@ -6440,7 +6443,7 @@ struct mlx5_ifc_modify_cq_in_bits {
u8 reserved_at_300[0x580];
u8 pas[0][0x40];
u8 pas[][0x40];
};
struct mlx5_ifc_modify_cong_status_out_bits {
@ -6504,7 +6507,7 @@ struct mlx5_ifc_manage_pages_out_bits {
u8 reserved_at_60[0x20];
u8 pas[0][0x40];
u8 pas[][0x40];
};
enum {
@ -6526,7 +6529,7 @@ struct mlx5_ifc_manage_pages_in_bits {
u8 input_num_entries[0x20];
u8 pas[0][0x40];
u8 pas[][0x40];
};
struct mlx5_ifc_mad_ifc_out_bits {
@ -6582,7 +6585,8 @@ struct mlx5_ifc_init2rtr_qp_out_bits {
u8 syndrome[0x20];
u8 reserved_at_40[0x40];
u8 reserved_at_40[0x20];
u8 ece[0x20];
};
struct mlx5_ifc_init2rtr_qp_in_bits {
@ -6599,7 +6603,7 @@ struct mlx5_ifc_init2rtr_qp_in_bits {
u8 opt_param_mask[0x20];
u8 reserved_at_a0[0x20];
u8 ece[0x20];
struct mlx5_ifc_qpc_bits qpc;
@ -7481,7 +7485,7 @@ struct mlx5_ifc_create_xrc_srq_in_bits {
u8 reserved_at_300[0x580];
u8 pas[0][0x40];
u8 pas[][0x40];
};
struct mlx5_ifc_create_tis_out_bits {
@ -7557,7 +7561,7 @@ struct mlx5_ifc_create_srq_in_bits {
u8 reserved_at_280[0x600];
u8 pas[0][0x40];
u8 pas[][0x40];
};
struct mlx5_ifc_create_sq_out_bits {
@ -7695,7 +7699,7 @@ struct mlx5_ifc_create_qp_out_bits {
u8 reserved_at_40[0x8];
u8 qpn[0x18];
u8 reserved_at_60[0x20];
u8 ece[0x20];
};
struct mlx5_ifc_create_qp_in_bits {
@ -7709,7 +7713,7 @@ struct mlx5_ifc_create_qp_in_bits {
u8 opt_param_mask[0x20];
u8 reserved_at_a0[0x20];
u8 ece[0x20];
struct mlx5_ifc_qpc_bits qpc;
@ -7718,7 +7722,7 @@ struct mlx5_ifc_create_qp_in_bits {
u8 wq_umem_valid[0x1];
u8 reserved_at_861[0x1f];
u8 pas[0][0x40];
u8 pas[][0x40];
};
struct mlx5_ifc_create_psv_out_bits {
@ -7789,7 +7793,7 @@ struct mlx5_ifc_create_mkey_in_bits {
u8 reserved_at_320[0x560];
u8 klm_pas_mtt[0][0x20];
u8 klm_pas_mtt[][0x20];
};
enum {
@ -7922,7 +7926,7 @@ struct mlx5_ifc_create_eq_in_bits {
u8 reserved_at_3c0[0x4c0];
u8 pas[0][0x40];
u8 pas[][0x40];
};
struct mlx5_ifc_create_dct_out_bits {
@ -7979,7 +7983,7 @@ struct mlx5_ifc_create_cq_in_bits {
u8 cq_umem_valid[0x1];
u8 reserved_at_2e1[0x59f];
u8 pas[0][0x40];
u8 pas[][0x40];
};
struct mlx5_ifc_config_int_moderation_out_bits {
@ -8335,7 +8339,7 @@ struct mlx5_ifc_access_register_out_bits {
u8 reserved_at_40[0x40];
u8 register_data[0][0x20];
u8 register_data[][0x20];
};
enum {
@ -8355,7 +8359,7 @@ struct mlx5_ifc_access_register_in_bits {
u8 argument[0x20];
u8 register_data[0][0x20];
u8 register_data[][0x20];
};
struct mlx5_ifc_sltp_reg_bits {
@ -9372,7 +9376,7 @@ struct mlx5_ifc_cmd_in_bits {
u8 reserved_at_20[0x10];
u8 op_mod[0x10];
u8 command[0][0x20];
u8 command[][0x20];
};
struct mlx5_ifc_cmd_if_box_bits {
@ -9666,7 +9670,7 @@ struct mlx5_ifc_mcqi_reg_bits {
u8 reserved_at_a0[0x10];
u8 data_size[0x10];
union mlx5_ifc_mcqi_reg_data_bits data[0];
union mlx5_ifc_mcqi_reg_data_bits data[];
};
struct mlx5_ifc_mcc_reg_bits {
@ -10252,7 +10256,7 @@ struct mlx5_ifc_umem_bits {
u8 num_of_mtt[0x40];
struct mlx5_ifc_mtt_bits mtt[0];
struct mlx5_ifc_mtt_bits mtt[];
};
struct mlx5_ifc_uctx_bits {
@ -10377,7 +10381,7 @@ struct mlx5_ifc_mtrc_stdb_bits {
u8 reserved_at_4[0x4];
u8 read_size[0x18];
u8 start_offset[0x20];
u8 string_db_data[0];
u8 string_db_data[];
};
struct mlx5_ifc_mtrc_ctrl_bits {
@ -10431,7 +10435,7 @@ struct mlx5_ifc_query_esw_functions_out_bits {
struct mlx5_ifc_host_params_context_bits host_params_context;
u8 reserved_at_280[0x180];
u8 host_sf_enable[0][0x40];
u8 host_sf_enable[][0x40];
};
struct mlx5_ifc_sf_partition_bits {
@ -10451,7 +10455,7 @@ struct mlx5_ifc_query_sf_partitions_out_bits {
u8 reserved_at_60[0x20];
struct mlx5_ifc_sf_partition_bits sf_partition[0];
struct mlx5_ifc_sf_partition_bits sf_partition[];
};
struct mlx5_ifc_query_sf_partitions_in_bits {

2
include/linux/mlx5/qp.h
View File

@ -408,7 +408,7 @@ struct mlx5_wqe_signature_seg {
struct mlx5_wqe_inline_seg {
__be32 byte_count;
__be32 data[0];
__be32 data[];
};
enum mlx5_sig_type {

17
include/net/mpls.h
View File

@ -8,6 +8,7 @@
#include <linux/if_ether.h>
#include <linux/netdevice.h>
#include <linux/mpls.h>
#define MPLS_HLEN 4
@ -25,4 +26,20 @@ static inline struct mpls_shim_hdr *mpls_hdr(const struct sk_buff *skb)
{
return (struct mpls_shim_hdr *)skb_network_header(skb);
}
static inline struct mpls_shim_hdr mpls_entry_encode(u32 label,
unsigned int ttl,
unsigned int tc,
bool bos)
{
struct mpls_shim_hdr result;
result.label_stack_entry =
cpu_to_be32((label << MPLS_LS_LABEL_SHIFT) |
(tc << MPLS_LS_TC_SHIFT) |
(bos ? (1 << MPLS_LS_S_SHIFT) : 0) |
(ttl << MPLS_LS_TTL_SHIFT));
return result;
}
#endif

11
net/mpls/internal.h
View File

@ -172,17 +172,6 @@ struct mpls_route { /* next hop label forwarding entry */
#define endfor_nexthops(rt) }
static inline struct mpls_shim_hdr mpls_entry_encode(u32 label, unsigned ttl, unsigned tc, bool bos)
{
struct mpls_shim_hdr result;
result.label_stack_entry =
cpu_to_be32((label << MPLS_LS_LABEL_SHIFT) |
(tc << MPLS_LS_TC_SHIFT) |
(bos ? (1 << MPLS_LS_S_SHIFT) : 0) |
(ttl << MPLS_LS_TTL_SHIFT));
return result;
}
static inline struct mpls_entry_decoded mpls_entry_decode(struct mpls_shim_hdr *hdr)
{
struct mpls_entry_decoded result;