tile: PCI: Use PCI Express Capability accessors
Use PCI Express Capability access functions to simplify Tile PCIe code. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Chris Metcalf <cmetcalf@tilera.com>
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@ -246,16 +246,13 @@ static void __devinit fixup_read_and_payload_sizes(void)
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/* Scan for the smallest maximum payload size. */
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/* Scan for the smallest maximum payload size. */
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while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
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while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
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int pcie_caps_offset;
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u32 devcap;
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u32 devcap;
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int max_payload;
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int max_payload;
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pcie_caps_offset = pci_find_capability(dev, PCI_CAP_ID_EXP);
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if (!pci_is_pcie(dev))
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if (pcie_caps_offset == 0)
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continue;
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continue;
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pci_read_config_dword(dev, pcie_caps_offset + PCI_EXP_DEVCAP,
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pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &devcap);
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&devcap);
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max_payload = devcap & PCI_EXP_DEVCAP_PAYLOAD;
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max_payload = devcap & PCI_EXP_DEVCAP_PAYLOAD;
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if (max_payload < smallest_max_payload)
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if (max_payload < smallest_max_payload)
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smallest_max_payload = max_payload;
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smallest_max_payload = max_payload;
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@ -263,21 +260,10 @@ static void __devinit fixup_read_and_payload_sizes(void)
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/* Now, set the max_payload_size for all devices to that value. */
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/* Now, set the max_payload_size for all devices to that value. */
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new_values = (max_read_size << 12) | (smallest_max_payload << 5);
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new_values = (max_read_size << 12) | (smallest_max_payload << 5);
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while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
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while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL)
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int pcie_caps_offset;
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pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
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u16 devctl;
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PCI_EXP_DEVCTL_PAYLOAD | PCI_EXP_DEVCTL_READRQ,
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new_values);
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pcie_caps_offset = pci_find_capability(dev, PCI_CAP_ID_EXP);
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if (pcie_caps_offset == 0)
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continue;
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pci_read_config_word(dev, pcie_caps_offset + PCI_EXP_DEVCTL,
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&devctl);
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devctl &= ~(PCI_EXP_DEVCTL_PAYLOAD | PCI_EXP_DEVCTL_READRQ);
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devctl |= new_values;
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pci_write_config_word(dev, pcie_caps_offset + PCI_EXP_DEVCTL,
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devctl);
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}
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}
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}
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