drivers/gpio: Switch gpio-mpc8xxx to use gpio-generic
The new Layerscape platforms has the same ip block/controller as GPIO on PowerPC platforms(MPC8XXX), but the GPIO registers may be big or little endian. So the code needs to get the endian property from DTB, then make additional functions to fit all the PowerPC/Layerscape GPIO register read/write operations. gpio-generic.c provides an universal infrastructure for both big and little endian register operations. So switch the gpio-mpc8xxx to use gpio-generic can simplify the driver and reduce a lot of code. The IRQ and some workaround parts in gpio-mpc8xxx.c will be updated with the new API interfaces but following the original functionalities. Signed-off-by: Liu Gang <Gang.Liu@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Liu Gang
Linus Walleij
parent
daec0beda6
commit
42178e2a1e
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@ -1,7 +1,8 @@
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/*
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* GPIOs on MPC512x/8349/8572/8610 and compatible
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* GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
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*
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* Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
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* Copyright (C) 2016 Freescale Semiconductor Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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@ -14,11 +15,12 @@
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/gpio.h>
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#include <linux/slab.h>
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#include <linux/irq.h>
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#include <linux/gpio/driver.h>
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#define MPC8XXX_GPIO_PINS 32
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@ -31,32 +33,20 @@
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#define GPIO_ICR2 0x18
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struct mpc8xxx_gpio_chip {
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struct of_mm_gpio_chip mm_gc;
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struct gpio_chip gc;
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void __iomem *regs;
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raw_spinlock_t lock;
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/*
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* shadowed data register to be able to clear/set output pins in
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* open drain mode safely
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*/
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u32 data;
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unsigned long (*read_reg)(void __iomem *reg);
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void (*write_reg)(void __iomem *reg, unsigned long data);
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int (*direction_output)(struct gpio_chip *chip,
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unsigned offset, int value);
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struct irq_domain *irq;
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unsigned int irqn;
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const void *of_dev_id_data;
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};
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static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
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{
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return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
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}
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static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc =
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container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
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mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
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}
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/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
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* defined as output cannot be determined by reading GPDAT register,
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* so we use shadow data register instead. The status of input pins
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@ -65,117 +55,36 @@ static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
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static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
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{
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u32 val;
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struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
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u32 out_mask, out_shadow;
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out_mask = in_be32(mm->regs + GPIO_DIR);
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out_mask = mpc8xxx_gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
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val = mpc8xxx_gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
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out_shadow = gc->bgpio_data & out_mask;
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val = in_be32(mm->regs + GPIO_DAT) & ~out_mask;
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out_shadow = mpc8xxx_gc->data & out_mask;
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return !!((val | out_shadow) & mpc8xxx_gpio2mask(gpio));
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return !!((val | out_shadow) & gc->pin2mask(gc, gpio));
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}
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static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
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static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
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unsigned int gpio, int val)
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{
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struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
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return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
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}
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static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
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unsigned long flags;
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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if (val)
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mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
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else
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mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
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out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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}
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static void mpc8xxx_gpio_set_multiple(struct gpio_chip *gc,
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unsigned long *mask, unsigned long *bits)
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{
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struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
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unsigned long flags;
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int i;
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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for (i = 0; i < gc->ngpio; i++) {
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if (*mask == 0)
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break;
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if (__test_and_clear_bit(i, mask)) {
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if (test_bit(i, bits))
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mpc8xxx_gc->data |= mpc8xxx_gpio2mask(i);
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else
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mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(i);
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}
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}
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out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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}
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static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
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{
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struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
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unsigned long flags;
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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return 0;
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}
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static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
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unsigned long flags;
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mpc8xxx_gpio_set(gc, gpio, val);
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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return 0;
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}
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static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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/* GPIO 28..31 are input only on MPC5121 */
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if (gpio >= 28)
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return -EINVAL;
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return mpc8xxx_gpio_dir_out(gc, gpio, val);
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return mpc8xxx_gc->direction_output(gc, gpio, val);
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}
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static int mpc5125_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
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unsigned int gpio, int val)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
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/* GPIO 0..3 are input only on MPC5125 */
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if (gpio <= 3)
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return -EINVAL;
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return mpc8xxx_gpio_dir_out(gc, gpio, val);
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return mpc8xxx_gc->direction_output(gc, gpio, val);
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}
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static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
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@ -192,10 +101,10 @@ static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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unsigned int mask;
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mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
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mask = mpc8xxx_gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
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& mpc8xxx_gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
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if (mask)
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generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
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32 - ffs(mask)));
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@ -206,12 +115,14 @@ static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc)
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static void mpc8xxx_irq_unmask(struct irq_data *d)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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struct gpio_chip *gc = &mpc8xxx_gc->gc;
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unsigned long flags;
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
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mpc8xxx_gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
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mpc8xxx_gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
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| gc->pin2mask(gc, irqd_to_hwirq(d)));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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}
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@ -219,12 +130,14 @@ static void mpc8xxx_irq_unmask(struct irq_data *d)
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static void mpc8xxx_irq_mask(struct irq_data *d)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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struct gpio_chip *gc = &mpc8xxx_gc->gc;
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unsigned long flags;
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
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mpc8xxx_gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
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mpc8xxx_gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
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& ~(gc->pin2mask(gc, irqd_to_hwirq(d))));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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}
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@ -232,29 +145,32 @@ static void mpc8xxx_irq_mask(struct irq_data *d)
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static void mpc8xxx_irq_ack(struct irq_data *d)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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struct gpio_chip *gc = &mpc8xxx_gc->gc;
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out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
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mpc8xxx_gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
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gc->pin2mask(gc, irqd_to_hwirq(d)));
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}
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static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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struct gpio_chip *gc = &mpc8xxx_gc->gc;
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unsigned long flags;
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switch (flow_type) {
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case IRQ_TYPE_EDGE_FALLING:
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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setbits32(mm->regs + GPIO_ICR,
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mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
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mpc8xxx_gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
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mpc8xxx_gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
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| gc->pin2mask(gc, irqd_to_hwirq(d)));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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case IRQ_TYPE_EDGE_BOTH:
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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clrbits32(mm->regs + GPIO_ICR,
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mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
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mpc8xxx_gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
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mpc8xxx_gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
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& ~(gc->pin2mask(gc, irqd_to_hwirq(d))));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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@ -268,17 +184,16 @@ static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
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static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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unsigned long gpio = irqd_to_hwirq(d);
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void __iomem *reg;
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unsigned int shift;
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unsigned long flags;
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if (gpio < 16) {
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reg = mm->regs + GPIO_ICR;
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reg = mpc8xxx_gc->regs + GPIO_ICR;
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shift = (15 - gpio) * 2;
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} else {
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reg = mm->regs + GPIO_ICR2;
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reg = mpc8xxx_gc->regs + GPIO_ICR2;
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shift = (15 - (gpio % 16)) * 2;
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}
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@ -286,20 +201,25 @@ static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
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case IRQ_TYPE_EDGE_FALLING:
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case IRQ_TYPE_LEVEL_LOW:
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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clrsetbits_be32(reg, 3 << shift, 2 << shift);
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mpc8xxx_gc->write_reg(reg,
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(mpc8xxx_gc->read_reg(reg) & ~(3 << shift))
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| (2 << shift));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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case IRQ_TYPE_EDGE_RISING:
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case IRQ_TYPE_LEVEL_HIGH:
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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clrsetbits_be32(reg, 3 << shift, 1 << shift);
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mpc8xxx_gc->write_reg(reg,
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(mpc8xxx_gc->read_reg(reg) & ~(3 << shift))
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| (1 << shift));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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case IRQ_TYPE_EDGE_BOTH:
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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clrbits32(reg, 3 << shift);
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mpc8xxx_gc->write_reg(reg,
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(mpc8xxx_gc->read_reg(reg) & ~(3 << shift)));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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@ -354,8 +274,6 @@ static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
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};
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static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
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.gpio_dir_out = mpc8xxx_gpio_dir_out,
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.gpio_get = mpc8xxx_gpio_get,
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.irq_set_type = mpc8xxx_irq_set_type,
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};
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@ -374,9 +292,7 @@ static int mpc8xxx_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct mpc8xxx_gpio_chip *mpc8xxx_gc;
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struct of_mm_gpio_chip *mm_gc;
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struct gpio_chip *gc;
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const struct of_device_id *id;
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struct gpio_chip *gc;
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const struct mpc8xxx_gpio_devtype *devtype =
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of_device_get_match_data(&pdev->dev);
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int ret;
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@ -389,12 +305,35 @@ static int mpc8xxx_probe(struct platform_device *pdev)
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raw_spin_lock_init(&mpc8xxx_gc->lock);
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mm_gc = &mpc8xxx_gc->mm_gc;
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gc = &mm_gc->gc;
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mpc8xxx_gc->regs = of_iomap(np, 0);
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if (!mpc8xxx_gc->regs)
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return -ENOMEM;
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mm_gc->save_regs = mpc8xxx_gpio_save_regs;
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gc->ngpio = MPC8XXX_GPIO_PINS;
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gc->direction_input = mpc8xxx_gpio_dir_in;
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gc = &mpc8xxx_gc->gc;
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if (of_property_read_bool(np, "little-endian")) {
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ret = bgpio_init(gc, &pdev->dev, 4,
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mpc8xxx_gc->regs + GPIO_DAT,
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NULL, NULL,
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mpc8xxx_gc->regs + GPIO_DIR, NULL,
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BGPIOF_BIG_ENDIAN);
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if (ret)
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goto err;
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dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
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} else {
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ret = bgpio_init(gc, &pdev->dev, 4,
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mpc8xxx_gc->regs + GPIO_DAT,
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||||
NULL, NULL,
|
||||
mpc8xxx_gc->regs + GPIO_DIR, NULL,
|
||||
BGPIOF_BIG_ENDIAN
|
||||
| BGPIOF_BIG_ENDIAN_BYTE_ORDER);
|
||||
if (ret)
|
||||
goto err;
|
||||
dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
|
||||
}
|
||||
|
||||
mpc8xxx_gc->read_reg = gc->read_reg;
|
||||
mpc8xxx_gc->write_reg = gc->write_reg;
|
||||
|
||||
if (!devtype)
|
||||
devtype = &mpc8xxx_gpio_devtype_default;
|
||||
|
|
@ -405,18 +344,21 @@ static int mpc8xxx_probe(struct platform_device *pdev)
|
|||
*/
|
||||
mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
|
||||
|
||||
gc->direction_output = devtype->gpio_dir_out ?: mpc8xxx_gpio_dir_out;
|
||||
gc->get = devtype->gpio_get ?: mpc8xxx_gpio_get;
|
||||
gc->set = mpc8xxx_gpio_set;
|
||||
gc->set_multiple = mpc8xxx_gpio_set_multiple;
|
||||
gc->direction_output = devtype->gpio_dir_out ?: gc->direction_output;
|
||||
gc->get = devtype->gpio_get ?: gc->get;
|
||||
gc->to_irq = mpc8xxx_gpio_to_irq;
|
||||
|
||||
ret = of_mm_gpiochip_add_data(np, mm_gc, mpc8xxx_gc);
|
||||
if (ret)
|
||||
return ret;
|
||||
mpc8xxx_gc->direction_output = gc->direction_output;
|
||||
|
||||
ret = gpiochip_add_data(gc, mpc8xxx_gc);
|
||||
if (ret) {
|
||||
pr_err("%s: GPIO chip registration failed with status %d\n",
|
||||
np->full_name, ret);
|
||||
goto err;
|
||||
}
|
||||
|
||||
mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
|
||||
if (mpc8xxx_gc->irqn == NO_IRQ)
|
||||
if (!mpc8xxx_gc->irqn)
|
||||
return 0;
|
||||
|
||||
mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
|
||||
|
|
@ -424,18 +366,16 @@ static int mpc8xxx_probe(struct platform_device *pdev)
|
|||
if (!mpc8xxx_gc->irq)
|
||||
return 0;
|
||||
|
||||
id = of_match_node(mpc8xxx_gpio_ids, np);
|
||||
if (id)
|
||||
mpc8xxx_gc->of_dev_id_data = id->data;
|
||||
|
||||
/* ack and mask all irqs */
|
||||
out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
|
||||
out_be32(mm_gc->regs + GPIO_IMR, 0);
|
||||
mpc8xxx_gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
|
||||
mpc8xxx_gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
|
||||
|
||||
irq_set_chained_handler_and_data(mpc8xxx_gc->irqn,
|
||||
mpc8xxx_gpio_irq_cascade, mpc8xxx_gc);
|
||||
|
||||
return 0;
|
||||
err:
|
||||
iounmap(mpc8xxx_gc->regs);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mpc8xxx_remove(struct platform_device *pdev)
|
||||
|
|
@ -447,7 +387,8 @@ static int mpc8xxx_remove(struct platform_device *pdev)
|
|||
irq_domain_remove(mpc8xxx_gc->irq);
|
||||
}
|
||||
|
||||
of_mm_gpiochip_remove(&mpc8xxx_gc->mm_gc);
|
||||
gpiochip_remove(&mpc8xxx_gc->gc);
|
||||
iounmap(mpc8xxx_gc->regs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue