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drm/i915: Re-enable per-engine reset for Broxton 

The corruption in CSB mmio reads we were seeing has been tracked down to
incorrectly touching forcewake of all domains, following an engine reset.
It is still a mistery why we only catched this in Broxton, since it
could happen in any platform.

With that fix already merged, commit 4055dc75d6 ("drm/i915: Stop
touching forcewake following a gen6+ engine reset"), lets try to enable
per-engine resets in Broxton one more time.

This reverts commit f188258bde0f ("drm/i915: Disable per-engine reset for
Broxton").

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170818172342.7282-1-michel.thierry@intel.com
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Michel Thierry 2017-08-18 10:23:42 -07:00 committed by Chris Wilson
parent 1853a9daa1
commit 41e61020e8
1 changed files with 0 additions and 1 deletions
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drivers/gpu/drm/i915/i915_pci.c
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@ -398,7 +398,6 @@ static const struct intel_device_info intel_broxton_info = {
GEN9_LP_FEATURES,
.platform = INTEL_BROXTON,
.ddb_size = 512,
.has_reset_engine = false,
};
static const struct intel_device_info intel_geminilake_info = {