Merge tag 'hisi-arm64-dt-for-4.15' of git://github.com/hisilicon/linux-hisi into next/soc
ARM64: DT: Hisilicon SoC DT updates for 4.15 - Add CoreSight related nodes for hi6220 - Add GPIO line names for hikey960 - Rectify the GPIO line names of the Poplar board to keep consistency - Add thermal sensor binding doc and dt nodes for hi3660 * tag 'hisi-arm64-dt-for-4.15' of git://github.com/hisilicon/linux-hisi: arm64: dts: Register Hi3660's thermal sensor dt-bindings: Document the hi3660 thermal sensor binding arm64: dts: hisilicon: Standardize Poplar GPIO line names arm64: dts: hikey960: Update HiKey960 with GPIO line names arm64: dts: hi6220: add coresight dt nodes
This commit is contained in:
Arnd Bergmann
commit
4167ca1e85
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|
@ -13,6 +13,7 @@
|
|||
|
||||
Example :
|
||||
|
||||
for Hi6220:
|
||||
tsensor: tsensor@0,f7030700 {
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||||
compatible = "hisilicon,tsensor";
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||||
reg = <0x0 0xf7030700 0x0 0x1000>;
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||||
|
|
@ -21,3 +22,11 @@ Example :
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|||
clock-names = "thermal_clk";
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||||
#thermal-sensor-cells = <1>;
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||||
}
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||||
|
||||
for Hi3660:
|
||||
tsensor: tsensor@fff30000 {
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||||
compatible = "hisilicon,hi3660-tsensor";
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||||
reg = <0x0 0xfff30000 0x0 0x1000>;
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||||
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
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||||
#thermal-sensor-cells = <1>;
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||||
};
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||||
|
|
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|||
|
|
@ -196,6 +196,325 @@
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|||
};
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||||
};
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||||
|
||||
/*
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* Legend: proper name = the GPIO line is used as GPIO
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||||
* NC = not connected (pin out but not routed from the chip to
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* anything the board)
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||||
* "[PER]" = pin is muxed for [peripheral] (not GPIO)
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* "" = no idea, schematic doesn't say, could be
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* unrouted (not connected to any external pin)
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* LSEC = Low Speed External Connector
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* HSEC = High Speed External Connector
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*
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* Line names are taken from "HiKey 960 Board ver A" schematics
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* from Huawei. The 40 pin low speed expansion connector is named
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* J2002 63453-140LF.
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*
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* For the lines routed to the external connectors the
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* lines are named after the 96Boards CE Specification 1.0,
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* Appendix "Expansion Connector Signal Description".
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*
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* When the 96Board naming of a line and the schematic name of
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* the same line are in conflict, the 96Board specification
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* takes precedence, which means that the external UART on the
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* LSEC is named UART0 while the schematic and SoC names this
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* UART3. This is only for the informational lines i.e. "[FOO]",
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* the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
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* ones actually used for GPIO.
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*/
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&gpio0 {
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/* GPIO_000-GPIO_007 */
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gpio-line-names =
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"",
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"TP901", /* TEST_MODE connected to TP901 */
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"[PMU0_SSI]",
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"[PMU1_SSI]",
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"[PMU2_SSI]",
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"[PMU0_CLKOUT]",
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"[JTAG_TCK]",
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"[JTAG_TMS]";
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};
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&gpio1 {
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/* GPIO_008-GPIO_015 */
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gpio-line-names =
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"[JTAG_TRST_N]",
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"[JTAG_TDI]",
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"[JTAG_TDO]",
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"NC", "NC",
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"[I2C3_SCL]",
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"[I2C3_SDA]",
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"NC";
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};
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&gpio2 {
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/* GPIO_016-GPIO_023 */
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gpio-line-names =
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"NC", "NC", "NC",
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"GPIO-J", /* LSEC pin 32: GPIO_019 */
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"GPIO_020_HDMI_SEL",
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"GPIO-L", /* LSEC pin 34: GPIO_021 */
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"GPIO_022_UFSBUCK_INT_N",
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"GPIO-G"; /* LSEC pin 29: LCD_TE0 */
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};
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&gpio3 {
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/* GPIO_024-GPIO_031 */
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/* The rail from pin BK36 is named LCD_TE0, we assume to be muxed as GPIO for GPIO-G */
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gpio-line-names =
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"[CSI0_MCLK]", /* HSEC pin 15: ISP_CCLK0_MCAM */
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"[CSI1_MCLK]", /* HSEC pin 17: ISP_CCLK1_SCAM */
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"NC",
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"[I2C2_SCL]", /* HSEC pin 32: ISP_SCL0 */
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"[I2C2_SDA]", /* HSEC pin 34: ISP_SDA0 */
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"[I2C3_SCL]", /* HSEC pin 36: ISP_SCL1 */
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"[I2C3_SDA]", /* HSEC pin 38: ISP_SDA1 */
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"NC";
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};
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&gpio4 {
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/* GPIO_032-GPIO_039 */
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gpio-line-names =
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"NC", "NC",
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"PWR_BTN_N", /* LSEC pin 4: GPIO_034_PWRON_DET */
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"GPIO_035_PMU2_EN",
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"GPIO_036_USB_HUB_RESET",
|
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"NC", "NC", "NC";
|
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};
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|
||||
&gpio5 {
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/* GPIO_040-GPIO_047 */
|
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gpio-line-names =
|
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"GPIO-H", /* LSEC pin 30: GPIO_040_LCD_RST_N */
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"GPIO_041_HDMI_PD",
|
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"TP904", /* Test point */
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"TP905", /* Test point */
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"NC", "NC",
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"GPIO_046_HUB_VDD33_EN",
|
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"GPIO_047_PMU1_EN";
|
||||
};
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||||
|
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&gpio6 {
|
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/* GPIO_048-GPIO_055 */
|
||||
gpio-line-names =
|
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"NC", "NC", "NC",
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"GPIO_051_WIFI_EN",
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"GPIO-I", /* LSEC pin 31: GPIO_052_CAM0_RST_N */
|
||||
/*
|
||||
* These two pins should be used for SD(IO) data according to the
|
||||
* 96boards specification but seems to be repurposed for a IRDA UART.
|
||||
* They are however named according to the spec.
|
||||
*/
|
||||
"[SD_DAT1]", /* HSEC pin 3: UART0_IRDA_RXD */
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||||
"[SD_DAT2]", /* HSEC pin 5: UART0_IRDA_TXD */
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||||
"[UART1_RXD]"; /* LSEC pin 13: DEBUG_UART6_RXD */
|
||||
};
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|
||||
&gpio7 {
|
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/* GPIO_056-GPIO_063 */
|
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gpio-line-names =
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||||
"[UART1_TXD]", /* LSEC pin 11: DEBUG_UART6_TXD */
|
||||
"[UART0_CTS]", /* LSEC pin 3: UART3_CTS_N */
|
||||
"[UART0_RTS]", /* LSEC pin 9: UART3_RTS_N */
|
||||
"[UART0_RXD]", /* LSEC pin 7: UART3_RXD */
|
||||
"[UART0_TXD]", /* LSEC pin 5: UART3_TXD */
|
||||
"[SOC_BT_UART4_CTS_N]",
|
||||
"[SOC_BT_UART4_RTS_N]",
|
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"[SOC_BT_UART4_RXD]";
|
||||
};
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|
||||
&gpio8 {
|
||||
/* GPIO_064-GPIO_071 */
|
||||
gpio-line-names =
|
||||
"[SOC_BT_UART4_TXD]",
|
||||
"NC",
|
||||
"[PMU_HKADC_SSI]",
|
||||
"NC",
|
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"GPIO_068_SEL",
|
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"NC", "NC", "NC";
|
||||
|
||||
};
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||||
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||||
&gpio9 {
|
||||
/* GPIO_072-GPIO_079 */
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||||
gpio-line-names =
|
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"NC", "NC", "NC",
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"GPIO-K", /* LSEC pin 33: GPIO_075_CAM1_RST_N */
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||||
"NC", "NC", "NC", "NC";
|
||||
};
|
||||
|
||||
&gpio10 {
|
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/* GPIO_080-GPIO_087 */
|
||||
gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
|
||||
};
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||||
|
||||
&gpio11 {
|
||||
/* GPIO_088-GPIO_095 */
|
||||
gpio-line-names =
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"NC",
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"[PCIE_PERST_N]",
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"NC", "NC", "NC", "NC", "NC", "NC";
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};
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&gpio12 {
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/* GPIO_096-GPIO_103 */
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gpio-line-names = "NC", "NC", "NC", "", "", "", "", "NC";
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};
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&gpio13 {
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/* GPIO_104-GPIO_111 */
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gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
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};
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&gpio14 {
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/* GPIO_112-GPIO_119 */
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gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
|
||||
};
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||||
|
||||
&gpio15 {
|
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/* GPIO_120-GPIO_127 */
|
||||
gpio-line-names =
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"NC", "NC", "NC", "NC", "NC", "NC",
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||||
"GPIO_126_BT_EN",
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"TP902"; /* GPIO_127_JTAG_SEL0 */
|
||||
};
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|
||||
&gpio16 {
|
||||
/* GPIO_128-GPIO_135 */
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||||
gpio-line-names = "", "", "", "", "", "", "", "";
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};
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&gpio17 {
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/* GPIO_136-GPIO_143 */
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gpio-line-names = "", "", "", "", "", "", "", "";
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};
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||||
&gpio18 {
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/* GPIO_144-GPIO_151 */
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gpio-line-names =
|
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"[UFS_REF_CLK]",
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"[UFS_RST_N]",
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"[SPI1_SCLK]", /* HSEC pin 9: GPIO_146_SPI3_CLK */
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||||
"[SPI1_DIN]", /* HSEC pin 11: GPIO_147_SPI3_DI */
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||||
"[SPI1_DOUT]", /* HSEC pin 1: GPIO_148_SPI3_DO */
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||||
"[SPI1_CS]", /* HSEC pin 7: GPIO_149_SPI3_CS0_N */
|
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"GPIO_150_USER_LED1",
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"GPIO_151_USER_LED2";
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};
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&gpio19 {
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/* GPIO_152-GPIO_159 */
|
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gpio-line-names = "NC", "NC", "NC", "NC", "", "", "", "";
|
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};
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&gpio20 {
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/* GPIO_160-GPIO_167 */
|
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gpio-line-names =
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"[SD_CLK]",
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||||
"[SD_CMD]",
|
||||
"[SD_DATA0]",
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"[SD_DATA1]",
|
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"[SD_DATA2]",
|
||||
"[SD_DATA3]",
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"", "";
|
||||
};
|
||||
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||||
&gpio21 {
|
||||
/* GPIO_168-GPIO_175 */
|
||||
gpio-line-names =
|
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"[WL_SDIO_CLK]",
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"[WL_SDIO_CMD]",
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"[WL_SDIO_DATA0]",
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"[WL_SDIO_DATA1]",
|
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"[WL_SDIO_DATA2]",
|
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"[WL_SDIO_DATA3]",
|
||||
"", "";
|
||||
};
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||||
|
||||
&gpio22 {
|
||||
/* GPIO_176-GPIO_183 */
|
||||
gpio-line-names =
|
||||
"[GPIO_176_PMU_PWR_HOLD]",
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"NA",
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"[SYSCLK_EN]",
|
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"GPIO_179_WL_WAKEUP_AP",
|
||||
"GPIO_180_HDMI_INT",
|
||||
"NA",
|
||||
"GPIO-F", /* LSEC pin 28: LCD_BL_PWM */
|
||||
"[I2C0_SCL]"; /* LSEC pin 15 */
|
||||
};
|
||||
|
||||
&gpio23 {
|
||||
/* GPIO_184-GPIO_191 */
|
||||
gpio-line-names =
|
||||
"[I2C0_SDA]", /* LSEC pin 17 */
|
||||
"[I2C1_SCL]", /* Actual SoC I2C1 */
|
||||
"[I2C1_SDA]", /* Actual SoC I2C1 */
|
||||
"[I2C1_SCL]", /* LSEC pin 19: I2C7_SCL */
|
||||
"[I2C1_SDA]", /* LSEC pin 21: I2C7_SDA */
|
||||
"GPIO_189_USER_LED3",
|
||||
"GPIO_190_USER_LED4",
|
||||
"";
|
||||
};
|
||||
|
||||
&gpio24 {
|
||||
/* GPIO_192-GPIO_199 */
|
||||
gpio-line-names =
|
||||
"[PCM_DI]", /* LSEC pin 22: GPIO_192_I2S0_DI */
|
||||
"[PCM_DO]", /* LSEC pin 20: GPIO_193_I2S0_DO */
|
||||
"[PCM_CLK]", /* LSEC pin 18: GPIO_194_I2S0_XCLK */
|
||||
"[PCM_FS]", /* LSEC pin 16: GPIO_195_I2S0_XFS */
|
||||
"[GPIO_196_I2S2_DI]",
|
||||
"[GPIO_197_I2S2_DO]",
|
||||
"[GPIO_198_I2S2_XCLK]",
|
||||
"[GPIO_199_I2S2_XFS]";
|
||||
};
|
||||
|
||||
&gpio25 {
|
||||
/* GPIO_200-GPIO_207 */
|
||||
gpio-line-names =
|
||||
"NC",
|
||||
"NC",
|
||||
"GPIO_202_VBUS_TYPEC",
|
||||
"GPIO_203_SD_DET",
|
||||
"GPIO_204_PMU12_IRQ_N",
|
||||
"GPIO_205_WIFI_ACTIVE",
|
||||
"GPIO_206_USBSW_SEL",
|
||||
"GPIO_207_BT_ACTIVE";
|
||||
};
|
||||
|
||||
&gpio26 {
|
||||
/* GPIO_208-GPIO_215 */
|
||||
gpio-line-names =
|
||||
"GPIO-A", /* LSEC pin 23: GPIO_208 */
|
||||
"GPIO-B", /* LSEC pin 24: GPIO_209 */
|
||||
"GPIO-C", /* LSEC pin 25: GPIO_210 */
|
||||
"GPIO-D", /* LSEC pin 26: GPIO_211 */
|
||||
"GPIO-E", /* LSEC pin 27: GPIO_212 */
|
||||
"[PCIE_CLKREQ_N]",
|
||||
"[PCIE_WAKE_N]",
|
||||
"[SPI0_CLK]"; /* LSEC pin 8: SPI2_CLK */
|
||||
};
|
||||
|
||||
&gpio27 {
|
||||
/* GPIO_216-GPIO_223 */
|
||||
gpio-line-names =
|
||||
"[SPI0_DIN]", /* LSEC pin 10: SPI2_DI */
|
||||
"[SPI0_DOUT]", /* LSEC pin 14: SPI2_DO */
|
||||
"[SPI0_CS]", /* LSEC pin 12: SPI2_CS0_N */
|
||||
"GPIO_219_CC_INT",
|
||||
"NC",
|
||||
"NC",
|
||||
"[PMU_INT]",
|
||||
"";
|
||||
};
|
||||
|
||||
&gpio28 {
|
||||
/* GPIO_224-GPIO_231 */
|
||||
gpio-line-names =
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
/* On Low speed expansion */
|
||||
label = "LS-I2C0";
|
||||
|
|
|
|||
|
|
@ -978,5 +978,12 @@
|
|||
clocks = <&crg_ctrl HI3660_OSC32K>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
tsensor: tsensor@fff30000 {
|
||||
compatible = "hisilicon,hi3660-tsensor";
|
||||
reg = <0x0 0xfff30000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -78,17 +78,17 @@
|
|||
|
||||
&gpio1 {
|
||||
status = "okay";
|
||||
gpio-line-names = "LS-GPIO-E", "",
|
||||
gpio-line-names = "GPIO-E", "",
|
||||
"", "",
|
||||
"", "LS-GPIO-F",
|
||||
"", "LS-GPIO-J";
|
||||
"", "GPIO-F",
|
||||
"", "GPIO-J";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
status = "okay";
|
||||
gpio-line-names = "LS-GPIO-H", "LS-GPIO-I",
|
||||
"LS-GPIO-L", "LS-GPIO-G",
|
||||
"LS-GPIO-K", "",
|
||||
gpio-line-names = "GPIO-H", "GPIO-I",
|
||||
"GPIO-L", "GPIO-G",
|
||||
"GPIO-K", "",
|
||||
"", "";
|
||||
};
|
||||
|
||||
|
|
@ -96,15 +96,15 @@
|
|||
status = "okay";
|
||||
gpio-line-names = "", "",
|
||||
"", "",
|
||||
"LS-GPIO-C", "",
|
||||
"", "LS-GPIO-B";
|
||||
"GPIO-C", "",
|
||||
"", "GPIO-B";
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
status = "okay";
|
||||
gpio-line-names = "", "",
|
||||
"", "",
|
||||
"", "LS-GPIO-D",
|
||||
"", "GPIO-D",
|
||||
"", "";
|
||||
};
|
||||
|
||||
|
|
@ -112,7 +112,7 @@
|
|||
status = "okay";
|
||||
gpio-line-names = "", "USER-LED-1",
|
||||
"USER-LED-2", "",
|
||||
"", "LS-GPIO-A",
|
||||
"", "GPIO-A",
|
||||
"", "";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,381 @@
|
|||
/*
|
||||
* dtsi file for Hisilicon Hi6220 coresight
|
||||
*
|
||||
* Copyright (C) 2017 Hisilicon Ltd.
|
||||
*
|
||||
* Author: Pengcheng Li <lipengcheng8@huawei.com>
|
||||
* Leo Yan <leo.yan@linaro.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* publishhed by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
/ {
|
||||
soc {
|
||||
funnel@f6401000 {
|
||||
compatible = "arm,coresight-funnel", "arm,primecell";
|
||||
reg = <0 0xf6401000 0 0x1000>;
|
||||
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
soc_funnel_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&etf_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <0>;
|
||||
soc_funnel_in: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint =
|
||||
<&acpu_funnel_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etf@f6402000 {
|
||||
compatible = "arm,coresight-tmc", "arm,primecell";
|
||||
reg = <0 0xf6402000 0 0x1000>;
|
||||
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
etf_in: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint =
|
||||
<&soc_funnel_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <0>;
|
||||
etf_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&replicator_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
replicator {
|
||||
compatible = "arm,coresight-replicator";
|
||||
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
replicator_in: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint =
|
||||
<&etf_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <0>;
|
||||
replicator_out0: endpoint {
|
||||
remote-endpoint =
|
||||
<&etr_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <1>;
|
||||
replicator_out1: endpoint {
|
||||
remote-endpoint =
|
||||
<&tpiu_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etr@f6404000 {
|
||||
compatible = "arm,coresight-tmc", "arm,primecell";
|
||||
reg = <0 0xf6404000 0 0x1000>;
|
||||
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
etr_in: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint =
|
||||
<&replicator_out0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tpiu@f6405000 {
|
||||
compatible = "arm,coresight-tpiu", "arm,primecell";
|
||||
reg = <0 0xf6405000 0 0x1000>;
|
||||
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
tpiu_in: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint =
|
||||
<&replicator_out1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
funnel@f6501000 {
|
||||
compatible = "arm,coresight-funnel", "arm,primecell";
|
||||
reg = <0 0xf6501000 0 0x1000>;
|
||||
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
acpu_funnel_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&soc_funnel_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <0>;
|
||||
acpu_funnel_in0: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint =
|
||||
<&etm0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <1>;
|
||||
acpu_funnel_in1: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint =
|
||||
<&etm1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <2>;
|
||||
acpu_funnel_in2: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint =
|
||||
<&etm2_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <3>;
|
||||
acpu_funnel_in3: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint =
|
||||
<&etm3_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <4>;
|
||||
acpu_funnel_in4: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint =
|
||||
<&etm4_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@6 {
|
||||
reg = <5>;
|
||||
acpu_funnel_in5: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint =
|
||||
<&etm5_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@7 {
|
||||
reg = <6>;
|
||||
acpu_funnel_in6: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint =
|
||||
<&etm6_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@8 {
|
||||
reg = <7>;
|
||||
acpu_funnel_in7: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint =
|
||||
<&etm7_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@f659c000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0xf659c000 0 0x1000>;
|
||||
|
||||
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
cpu = <&cpu0>;
|
||||
|
||||
port {
|
||||
etm0_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&acpu_funnel_in0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@f659d000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0xf659d000 0 0x1000>;
|
||||
|
||||
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
cpu = <&cpu1>;
|
||||
|
||||
port {
|
||||
etm1_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&acpu_funnel_in1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@f659e000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0xf659e000 0 0x1000>;
|
||||
|
||||
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
cpu = <&cpu2>;
|
||||
|
||||
port {
|
||||
etm2_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&acpu_funnel_in2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@f659f000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0xf659f000 0 0x1000>;
|
||||
|
||||
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
cpu = <&cpu3>;
|
||||
|
||||
port {
|
||||
etm3_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&acpu_funnel_in3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@f65dc000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0xf65dc000 0 0x1000>;
|
||||
|
||||
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
cpu = <&cpu4>;
|
||||
|
||||
port {
|
||||
etm4_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&acpu_funnel_in4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@f65dd000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0xf65dd000 0 0x1000>;
|
||||
|
||||
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
cpu = <&cpu5>;
|
||||
|
||||
port {
|
||||
etm5_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&acpu_funnel_in5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@f65de000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0xf65de000 0 0x1000>;
|
||||
|
||||
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
cpu = <&cpu6>;
|
||||
|
||||
port {
|
||||
etm6_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&acpu_funnel_in6>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@f65df000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0xf65df000 0 0x1000>;
|
||||
|
||||
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
cpu = <&cpu7>;
|
||||
|
||||
port {
|
||||
etm7_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&acpu_funnel_in7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -986,3 +986,5 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "hi6220-coresight.dtsi"
|
||||
|
|
|
|||
Loading…
Reference in New Issue