drm/radeon/kms: set crtc and cursor offsets correctly on legacy chips.
The crtc and cursor offsets on the legacy chips are offset from DISPLAY_BASE_ADDR. The code worked if display base addr was at 0, but otherwise falls to pieces. Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -113,7 +113,7 @@ static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj,
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WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr);
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else
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/* offset is from DISP(2)_BASE_ADDRESS */
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WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, gpu_addr);
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WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (gpu_addr-radeon_crtc->legacy_display_base_addr));
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}
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int radeon_crtc_cursor_set(struct drm_crtc *crtc,
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@ -244,7 +244,12 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
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if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) {
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return -EINVAL;
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}
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crtc_offset = (u32)base;
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/* if scanout was in GTT this really wouldn't work */
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/* crtc offset is from display base addr not FB location */
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radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location;
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base -= radeon_crtc->legacy_display_base_addr;
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crtc_offset_cntl = 0;
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pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
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@ -303,11 +308,9 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
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base &= ~7;
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/* update sarea TODO */
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crtc_offset = (u32)base;
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WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, rdev->mc.vram_location);
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WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
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if (ASIC_IS_R300(rdev)) {
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if (radeon_crtc->crtc_id)
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@ -185,6 +185,7 @@ struct radeon_crtc {
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uint64_t cursor_addr;
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int cursor_width;
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int cursor_height;
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uint32_t legacy_display_base_addr;
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};
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#define RADEON_USE_RMX 1
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