Merge branch 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pullx86 core platform updates from Peter Anvin: "This is the x86/platform branch with the objectionable IOSF patches removed. What is left is proper memory handling for Intel GPUs, and a change to the Calgary IOMMU code which will be required to make kexec work sanely on those platforms after some upcoming kexec changes" * 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86, calgary: Use 8M TCE table size by default x86/gpu: Print the Intel graphics stolen memory range x86/gpu: Add Intel graphics stolen memory quirk for gen2 platforms x86/gpu: Add vfunc for Intel graphics stolen memory base address
This commit is contained in:
Linus Torvalds
commit
40e9963e62
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@ -225,7 +225,7 @@ static void __init intel_remapping_check(int num, int slot, int func)
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*
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* And yes, so far on current devices the base addr is always under 4G.
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*/
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static u32 __init intel_stolen_base(int num, int slot, int func)
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static u32 __init intel_stolen_base(int num, int slot, int func, size_t stolen_size)
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{
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u32 base;
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@ -244,6 +244,114 @@ static u32 __init intel_stolen_base(int num, int slot, int func)
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#define MB(x) (KB (KB (x)))
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#define GB(x) (MB (KB (x)))
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static size_t __init i830_tseg_size(void)
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{
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u8 tmp = read_pci_config_byte(0, 0, 0, I830_ESMRAMC);
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if (!(tmp & TSEG_ENABLE))
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return 0;
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if (tmp & I830_TSEG_SIZE_1M)
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return MB(1);
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else
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return KB(512);
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}
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static size_t __init i845_tseg_size(void)
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{
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u8 tmp = read_pci_config_byte(0, 0, 0, I845_ESMRAMC);
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if (!(tmp & TSEG_ENABLE))
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return 0;
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switch (tmp & I845_TSEG_SIZE_MASK) {
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case I845_TSEG_SIZE_512K:
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return KB(512);
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case I845_TSEG_SIZE_1M:
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return MB(1);
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default:
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WARN_ON(1);
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return 0;
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}
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}
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static size_t __init i85x_tseg_size(void)
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{
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u8 tmp = read_pci_config_byte(0, 0, 0, I85X_ESMRAMC);
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if (!(tmp & TSEG_ENABLE))
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return 0;
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return MB(1);
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}
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static size_t __init i830_mem_size(void)
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{
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return read_pci_config_byte(0, 0, 0, I830_DRB3) * MB(32);
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}
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static size_t __init i85x_mem_size(void)
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{
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return read_pci_config_byte(0, 0, 1, I85X_DRB3) * MB(32);
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}
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/*
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* On 830/845/85x the stolen memory base isn't available in any
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* register. We need to calculate it as TOM-TSEG_SIZE-stolen_size.
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*/
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static u32 __init i830_stolen_base(int num, int slot, int func, size_t stolen_size)
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{
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return i830_mem_size() - i830_tseg_size() - stolen_size;
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}
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static u32 __init i845_stolen_base(int num, int slot, int func, size_t stolen_size)
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{
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return i830_mem_size() - i845_tseg_size() - stolen_size;
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}
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static u32 __init i85x_stolen_base(int num, int slot, int func, size_t stolen_size)
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{
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return i85x_mem_size() - i85x_tseg_size() - stolen_size;
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}
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static u32 __init i865_stolen_base(int num, int slot, int func, size_t stolen_size)
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{
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/*
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* FIXME is the graphics stolen memory region
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* always at TOUD? Ie. is it always the last
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* one to be allocated by the BIOS?
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*/
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return read_pci_config_16(0, 0, 0, I865_TOUD) << 16;
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}
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static size_t __init i830_stolen_size(int num, int slot, int func)
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{
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size_t stolen_size;
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u16 gmch_ctrl;
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gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
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switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
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case I830_GMCH_GMS_STOLEN_512:
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stolen_size = KB(512);
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break;
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case I830_GMCH_GMS_STOLEN_1024:
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stolen_size = MB(1);
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break;
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case I830_GMCH_GMS_STOLEN_8192:
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stolen_size = MB(8);
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break;
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case I830_GMCH_GMS_LOCAL:
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/* local memory isn't part of the normal address space */
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stolen_size = 0;
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break;
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default:
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return 0;
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}
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return stolen_size;
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}
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static size_t __init gen3_stolen_size(int num, int slot, int func)
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{
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size_t stolen_size;
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@ -310,7 +418,7 @@ static size_t __init gen6_stolen_size(int num, int slot, int func)
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return gmch_ctrl << 25; /* 32 MB units */
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}
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static inline size_t gen8_stolen_size(int num, int slot, int func)
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static size_t gen8_stolen_size(int num, int slot, int func)
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{
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u16 gmch_ctrl;
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@ -320,31 +428,74 @@ static inline size_t gen8_stolen_size(int num, int slot, int func)
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return gmch_ctrl << 25; /* 32 MB units */
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}
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typedef size_t (*stolen_size_fn)(int num, int slot, int func);
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struct intel_stolen_funcs {
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size_t (*size)(int num, int slot, int func);
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u32 (*base)(int num, int slot, int func, size_t size);
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};
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static const struct intel_stolen_funcs i830_stolen_funcs = {
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.base = i830_stolen_base,
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.size = i830_stolen_size,
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};
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static const struct intel_stolen_funcs i845_stolen_funcs = {
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.base = i845_stolen_base,
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.size = i830_stolen_size,
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};
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static const struct intel_stolen_funcs i85x_stolen_funcs = {
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.base = i85x_stolen_base,
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.size = gen3_stolen_size,
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};
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static const struct intel_stolen_funcs i865_stolen_funcs = {
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.base = i865_stolen_base,
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.size = gen3_stolen_size,
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};
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static const struct intel_stolen_funcs gen3_stolen_funcs = {
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.base = intel_stolen_base,
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.size = gen3_stolen_size,
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};
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static const struct intel_stolen_funcs gen6_stolen_funcs = {
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.base = intel_stolen_base,
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.size = gen6_stolen_size,
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};
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static const struct intel_stolen_funcs gen8_stolen_funcs = {
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.base = intel_stolen_base,
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.size = gen8_stolen_size,
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};
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static struct pci_device_id intel_stolen_ids[] __initdata = {
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INTEL_I915G_IDS(gen3_stolen_size),
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INTEL_I915GM_IDS(gen3_stolen_size),
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INTEL_I945G_IDS(gen3_stolen_size),
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INTEL_I945GM_IDS(gen3_stolen_size),
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INTEL_VLV_M_IDS(gen6_stolen_size),
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INTEL_VLV_D_IDS(gen6_stolen_size),
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INTEL_PINEVIEW_IDS(gen3_stolen_size),
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INTEL_I965G_IDS(gen3_stolen_size),
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INTEL_G33_IDS(gen3_stolen_size),
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INTEL_I965GM_IDS(gen3_stolen_size),
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INTEL_GM45_IDS(gen3_stolen_size),
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INTEL_G45_IDS(gen3_stolen_size),
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INTEL_IRONLAKE_D_IDS(gen3_stolen_size),
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INTEL_IRONLAKE_M_IDS(gen3_stolen_size),
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INTEL_SNB_D_IDS(gen6_stolen_size),
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INTEL_SNB_M_IDS(gen6_stolen_size),
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INTEL_IVB_M_IDS(gen6_stolen_size),
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INTEL_IVB_D_IDS(gen6_stolen_size),
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INTEL_HSW_D_IDS(gen6_stolen_size),
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INTEL_HSW_M_IDS(gen6_stolen_size),
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INTEL_BDW_M_IDS(gen8_stolen_size),
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INTEL_BDW_D_IDS(gen8_stolen_size)
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INTEL_I830_IDS(&i830_stolen_funcs),
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INTEL_I845G_IDS(&i845_stolen_funcs),
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INTEL_I85X_IDS(&i85x_stolen_funcs),
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INTEL_I865G_IDS(&i865_stolen_funcs),
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INTEL_I915G_IDS(&gen3_stolen_funcs),
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INTEL_I915GM_IDS(&gen3_stolen_funcs),
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INTEL_I945G_IDS(&gen3_stolen_funcs),
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INTEL_I945GM_IDS(&gen3_stolen_funcs),
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INTEL_VLV_M_IDS(&gen6_stolen_funcs),
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INTEL_VLV_D_IDS(&gen6_stolen_funcs),
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INTEL_PINEVIEW_IDS(&gen3_stolen_funcs),
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INTEL_I965G_IDS(&gen3_stolen_funcs),
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INTEL_G33_IDS(&gen3_stolen_funcs),
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INTEL_I965GM_IDS(&gen3_stolen_funcs),
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INTEL_GM45_IDS(&gen3_stolen_funcs),
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INTEL_G45_IDS(&gen3_stolen_funcs),
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INTEL_IRONLAKE_D_IDS(&gen3_stolen_funcs),
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INTEL_IRONLAKE_M_IDS(&gen3_stolen_funcs),
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INTEL_SNB_D_IDS(&gen6_stolen_funcs),
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INTEL_SNB_M_IDS(&gen6_stolen_funcs),
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INTEL_IVB_M_IDS(&gen6_stolen_funcs),
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INTEL_IVB_D_IDS(&gen6_stolen_funcs),
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INTEL_HSW_D_IDS(&gen6_stolen_funcs),
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INTEL_HSW_M_IDS(&gen6_stolen_funcs),
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INTEL_BDW_M_IDS(&gen8_stolen_funcs),
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INTEL_BDW_D_IDS(&gen8_stolen_funcs)
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};
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static void __init intel_graphics_stolen(int num, int slot, int func)
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@ -361,11 +512,13 @@ static void __init intel_graphics_stolen(int num, int slot, int func)
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for (i = 0; i < ARRAY_SIZE(intel_stolen_ids); i++) {
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if (intel_stolen_ids[i].device == device) {
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stolen_size_fn stolen_size =
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(stolen_size_fn)intel_stolen_ids[i].driver_data;
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size = stolen_size(num, slot, func);
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start = intel_stolen_base(num, slot, func);
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const struct intel_stolen_funcs *stolen_funcs =
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(const struct intel_stolen_funcs *)intel_stolen_ids[i].driver_data;
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size = stolen_funcs->size(num, slot, func);
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start = stolen_funcs->base(num, slot, func, size);
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if (size && start) {
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printk(KERN_INFO "Reserving Intel graphics stolen memory at 0x%x-0x%x\n",
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start, start + (u32)size - 1);
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/* Mark this space as reserved */
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e820_add_region(start, size, E820_RESERVED);
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sanitize_e820_map(e820.map,
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@ -1207,23 +1207,31 @@ error:
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return ret;
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}
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static inline int __init determine_tce_table_size(u64 ram)
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static inline int __init determine_tce_table_size(void)
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{
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int ret;
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if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
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return specified_table_size;
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/*
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* Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
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* TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
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* larger table size has twice as many entries, so shift the
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* max ram address by 13 to divide by 8K and then look at the
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* order of the result to choose between 0-7.
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*/
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ret = get_order(ram >> 13);
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if (ret > TCE_TABLE_SIZE_8M)
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if (is_kdump_kernel() && saved_max_pfn) {
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/*
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* Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
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* TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
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* larger table size has twice as many entries, so shift the
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* max ram address by 13 to divide by 8K and then look at the
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* order of the result to choose between 0-7.
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*/
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ret = get_order((saved_max_pfn * PAGE_SIZE) >> 13);
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if (ret > TCE_TABLE_SIZE_8M)
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ret = TCE_TABLE_SIZE_8M;
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} else {
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/*
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* Use 8M by default (suggested by Muli) if it's not
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* kdump kernel and saved_max_pfn isn't set.
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*/
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ret = TCE_TABLE_SIZE_8M;
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}
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return ret;
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}
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@ -1418,8 +1426,7 @@ int __init detect_calgary(void)
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return -ENOMEM;
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}
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specified_table_size = determine_tce_table_size((is_kdump_kernel() ?
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saved_max_pfn : max_pfn) * PAGE_SIZE);
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specified_table_size = determine_tce_table_size();
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for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
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struct calgary_bus_info *info = &bus_info[bus];
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@ -56,6 +56,12 @@ extern bool i915_gpu_turbo_disable(void);
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#define I830_GMCH_CTRL 0x52
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#define I830_GMCH_GMS_MASK 0x70
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#define I830_GMCH_GMS_LOCAL 0x10
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#define I830_GMCH_GMS_STOLEN_512 0x20
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#define I830_GMCH_GMS_STOLEN_1024 0x30
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#define I830_GMCH_GMS_STOLEN_8192 0x40
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#define I855_GMCH_GMS_MASK 0xF0
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#define I855_GMCH_GMS_STOLEN_0M 0x0
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#define I855_GMCH_GMS_STOLEN_1M (0x1 << 4)
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@ -72,4 +78,18 @@ extern bool i915_gpu_turbo_disable(void);
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#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
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#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
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#define I830_DRB3 0x63
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#define I85X_DRB3 0x43
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#define I865_TOUD 0xc4
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#define I830_ESMRAMC 0x91
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#define I845_ESMRAMC 0x9e
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#define I85X_ESMRAMC 0x61
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#define TSEG_ENABLE (1 << 0)
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#define I830_TSEG_SIZE_512K (0 << 1)
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#define I830_TSEG_SIZE_1M (1 << 1)
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#define I845_TSEG_SIZE_MASK (3 << 1)
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#define I845_TSEG_SIZE_512K (2 << 1)
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#define I845_TSEG_SIZE_1M (3 << 1)
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#endif /* _I915_DRM_H_ */
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Loading…
Reference in New Issue