x86: automatical unification of i8259.c
Make conversion of i8259 very mechanical -- i8259 was generated by
This commit is contained in:
Pavel Machek
Thomas Gleixner
parent
75d3bce2fc
commit
40bd217400
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@ -18,7 +18,7 @@ CFLAGS_tsc_64.o := $(nostackp)
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obj-y := process_$(BITS).o signal_$(BITS).o entry_$(BITS).o
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obj-y := process_$(BITS).o signal_$(BITS).o entry_$(BITS).o
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obj-y += traps_$(BITS).o irq_$(BITS).o
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obj-y += traps_$(BITS).o irq_$(BITS).o
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obj-y += time_$(BITS).o ioport.o ldt.o
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obj-y += time_$(BITS).o ioport.o ldt.o
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obj-y += setup_$(BITS).o i8259_$(BITS).o setup.o
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obj-y += setup_$(BITS).o i8259.o i8259_$(BITS).o setup.o
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obj-$(CONFIG_X86_32) += sys_i386_32.o i386_ksyms_32.o
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obj-$(CONFIG_X86_32) += sys_i386_32.o i386_ksyms_32.o
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obj-$(CONFIG_X86_64) += sys_x86_64.o x8664_ksyms_64.o
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obj-$(CONFIG_X86_64) += sys_x86_64.o x8664_ksyms_64.o
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obj-$(CONFIG_X86_64) += syscall_64.o vsyscall_64.o setup64.o
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obj-$(CONFIG_X86_64) += syscall_64.o vsyscall_64.o setup64.o
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@ -0,0 +1,368 @@
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#ifdef CONFIG_X86_64
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#include <linux/linkage.h>
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#endif /* CONFIG_X86_64 */
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#include <linux/errno.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#ifdef CONFIG_X86_64
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#include <linux/timex.h>
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#endif /* CONFIG_X86_64 */
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#include <linux/slab.h>
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#include <linux/random.h>
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#include <linux/init.h>
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#include <linux/kernel_stat.h>
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#include <linux/sysdev.h>
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#include <linux/bitops.h>
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#ifdef CONFIG_X86_64
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#include <asm/acpi.h>
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#endif /* CONFIG_X86_64 */
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#include <asm/atomic.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#ifndef CONFIG_X86_64
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#include <asm/timer.h>
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#else /* CONFIG_X86_64 */
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#include <asm/hw_irq.h>
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#endif /* CONFIG_X86_64 */
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#include <asm/pgtable.h>
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#include <asm/delay.h>
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#include <asm/desc.h>
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#include <asm/apic.h>
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#ifndef CONFIG_X86_64
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#include <asm/arch_hooks.h>
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#endif /* ! CONFIG_X86_64 */
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#include <asm/i8259.h>
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/*
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* This is the 'legacy' 8259A Programmable Interrupt Controller,
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* present in the majority of PC/AT boxes.
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* plus some generic x86 specific things if generic specifics makes
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* any sense at all.
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*/
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static int i8259A_auto_eoi;
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DEFINE_SPINLOCK(i8259A_lock);
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static void mask_and_ack_8259A(unsigned int);
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struct irq_chip i8259A_chip = {
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.name = "XT-PIC",
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.mask = disable_8259A_irq,
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.disable = disable_8259A_irq,
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.unmask = enable_8259A_irq,
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.mask_ack = mask_and_ack_8259A,
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};
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/*
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* 8259A PIC functions to handle ISA devices:
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*/
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/*
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* This contains the irq mask for both 8259A irq controllers,
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*/
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unsigned int cached_irq_mask = 0xffff;
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/*
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* Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
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* boards the timer interrupt is not really connected to any IO-APIC pin,
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* it's fed to the master 8259A's IR0 line only.
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*
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* Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
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* this 'mixed mode' IRQ handling costs nothing because it's only used
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* at IRQ setup time.
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*/
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unsigned long io_apic_irqs;
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void disable_8259A_irq(unsigned int irq)
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{
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unsigned int mask = 1 << irq;
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unsigned long flags;
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spin_lock_irqsave(&i8259A_lock, flags);
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cached_irq_mask |= mask;
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if (irq & 8)
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outb(cached_slave_mask, PIC_SLAVE_IMR);
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else
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outb(cached_master_mask, PIC_MASTER_IMR);
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spin_unlock_irqrestore(&i8259A_lock, flags);
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}
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void enable_8259A_irq(unsigned int irq)
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{
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unsigned int mask = ~(1 << irq);
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unsigned long flags;
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spin_lock_irqsave(&i8259A_lock, flags);
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cached_irq_mask &= mask;
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if (irq & 8)
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outb(cached_slave_mask, PIC_SLAVE_IMR);
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else
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outb(cached_master_mask, PIC_MASTER_IMR);
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spin_unlock_irqrestore(&i8259A_lock, flags);
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}
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int i8259A_irq_pending(unsigned int irq)
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{
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unsigned int mask = 1<<irq;
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&i8259A_lock, flags);
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if (irq < 8)
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ret = inb(PIC_MASTER_CMD) & mask;
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else
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ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
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spin_unlock_irqrestore(&i8259A_lock, flags);
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return ret;
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}
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void make_8259A_irq(unsigned int irq)
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{
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disable_irq_nosync(irq);
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io_apic_irqs &= ~(1<<irq);
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set_irq_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq,
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"XT");
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enable_irq(irq);
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}
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/*
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* This function assumes to be called rarely. Switching between
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* 8259A registers is slow.
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* This has to be protected by the irq controller spinlock
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* before being called.
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*/
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static inline int i8259A_irq_real(unsigned int irq)
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{
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int value;
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int irqmask = 1<<irq;
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if (irq < 8) {
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outb(0x0B,PIC_MASTER_CMD); /* ISR register */
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value = inb(PIC_MASTER_CMD) & irqmask;
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outb(0x0A,PIC_MASTER_CMD); /* back to the IRR register */
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return value;
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}
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outb(0x0B,PIC_SLAVE_CMD); /* ISR register */
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value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
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outb(0x0A,PIC_SLAVE_CMD); /* back to the IRR register */
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return value;
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}
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/*
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* Careful! The 8259A is a fragile beast, it pretty
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* much _has_ to be done exactly like this (mask it
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* first, _then_ send the EOI, and the order of EOI
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* to the two 8259s is important!
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*/
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static void mask_and_ack_8259A(unsigned int irq)
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{
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unsigned int irqmask = 1 << irq;
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unsigned long flags;
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spin_lock_irqsave(&i8259A_lock, flags);
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/*
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* Lightweight spurious IRQ detection. We do not want
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* to overdo spurious IRQ handling - it's usually a sign
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* of hardware problems, so we only do the checks we can
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* do without slowing down good hardware unnecessarily.
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*
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* Note that IRQ7 and IRQ15 (the two spurious IRQs
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* usually resulting from the 8259A-1|2 PICs) occur
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* even if the IRQ is masked in the 8259A. Thus we
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* can check spurious 8259A IRQs without doing the
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* quite slow i8259A_irq_real() call for every IRQ.
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* This does not cover 100% of spurious interrupts,
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* but should be enough to warn the user that there
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* is something bad going on ...
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*/
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if (cached_irq_mask & irqmask)
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goto spurious_8259A_irq;
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cached_irq_mask |= irqmask;
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handle_real_irq:
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if (irq & 8) {
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inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
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outb(cached_slave_mask, PIC_SLAVE_IMR);
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#ifndef CONFIG_X86_64
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outb(0x60+(irq&7),PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
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outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
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#else /* CONFIG_X86_64 */
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/* 'Specific EOI' to slave */
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outb(0x60+(irq&7),PIC_SLAVE_CMD);
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/* 'Specific EOI' to master-IRQ2 */
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outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD);
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#endif /* CONFIG_X86_64 */
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} else {
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inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
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outb(cached_master_mask, PIC_MASTER_IMR);
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#ifndef CONFIG_X86_64
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outb(0x60+irq,PIC_MASTER_CMD); /* 'Specific EOI to master */
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#else /* CONFIG_X86_64 */
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/* 'Specific EOI' to master */
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outb(0x60+irq,PIC_MASTER_CMD);
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#endif /* CONFIG_X86_64 */
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}
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spin_unlock_irqrestore(&i8259A_lock, flags);
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return;
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spurious_8259A_irq:
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/*
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* this is the slow path - should happen rarely.
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*/
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if (i8259A_irq_real(irq))
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/*
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* oops, the IRQ _is_ in service according to the
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* 8259A - not spurious, go handle it.
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*/
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goto handle_real_irq;
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{
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static int spurious_irq_mask;
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/*
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* At this point we can be sure the IRQ is spurious,
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* lets ACK and report it. [once per IRQ]
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*/
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if (!(spurious_irq_mask & irqmask)) {
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#ifndef CONFIG_X86_64
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printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
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#else /* CONFIG_X86_64 */
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printk(KERN_DEBUG
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"spurious 8259A interrupt: IRQ%d.\n", irq);
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#endif /* CONFIG_X86_64 */
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spurious_irq_mask |= irqmask;
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}
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atomic_inc(&irq_err_count);
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/*
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* Theoretically we do not have to handle this IRQ,
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* but in Linux this does not cause problems and is
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* simpler for us.
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*/
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goto handle_real_irq;
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}
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}
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static char irq_trigger[2];
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/**
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* ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
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*/
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static void restore_ELCR(char *trigger)
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{
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outb(trigger[0], 0x4d0);
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outb(trigger[1], 0x4d1);
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}
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static void save_ELCR(char *trigger)
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{
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/* IRQ 0,1,2,8,13 are marked as reserved */
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trigger[0] = inb(0x4d0) & 0xF8;
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trigger[1] = inb(0x4d1) & 0xDE;
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}
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static int i8259A_resume(struct sys_device *dev)
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{
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init_8259A(i8259A_auto_eoi);
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restore_ELCR(irq_trigger);
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return 0;
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}
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static int i8259A_suspend(struct sys_device *dev, pm_message_t state)
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{
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save_ELCR(irq_trigger);
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return 0;
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}
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static int i8259A_shutdown(struct sys_device *dev)
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{
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/* Put the i8259A into a quiescent state that
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* the kernel initialization code can get it
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* out of.
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*/
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outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
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outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-1 */
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return 0;
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}
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static struct sysdev_class i8259_sysdev_class = {
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.name = "i8259",
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.suspend = i8259A_suspend,
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.resume = i8259A_resume,
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.shutdown = i8259A_shutdown,
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};
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static struct sys_device device_i8259A = {
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.id = 0,
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.cls = &i8259_sysdev_class,
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};
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static int __init i8259A_init_sysfs(void)
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{
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int error = sysdev_class_register(&i8259_sysdev_class);
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if (!error)
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error = sysdev_register(&device_i8259A);
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return error;
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}
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device_initcall(i8259A_init_sysfs);
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void init_8259A(int auto_eoi)
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{
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unsigned long flags;
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i8259A_auto_eoi = auto_eoi;
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spin_lock_irqsave(&i8259A_lock, flags);
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outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
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outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
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/*
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* outb_pic - this has to work on a wide range of PC hardware.
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*/
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outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
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#ifndef CONFIG_X86_64
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outb_pic(0x20 + 0, PIC_MASTER_IMR); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
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outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */
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#else /* CONFIG_X86_64 */
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/* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 */
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outb_pic(IRQ0_VECTOR, PIC_MASTER_IMR);
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/* 8259A-1 (the master) has a slave on IR2 */
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outb_pic(0x04, PIC_MASTER_IMR);
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#endif /* CONFIG_X86_64 */
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if (auto_eoi) /* master does Auto EOI */
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outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
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else /* master expects normal EOI */
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outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
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outb_pic(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
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#ifndef CONFIG_X86_64
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outb_pic(0x20 + 8, PIC_SLAVE_IMR); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
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||||||
|
outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR); /* 8259A-2 is a slave on master's IR2 */
|
||||||
|
outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
|
||||||
|
#else /* CONFIG_X86_64 */
|
||||||
|
/* ICW2: 8259A-2 IR0-7 mapped to 0x38-0x3f */
|
||||||
|
outb_pic(IRQ8_VECTOR, PIC_SLAVE_IMR);
|
||||||
|
/* 8259A-2 is a slave on master's IR2 */
|
||||||
|
outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);
|
||||||
|
/* (slave's support for AEOI in flat mode is to be investigated) */
|
||||||
|
outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);
|
||||||
|
|
||||||
|
#endif /* CONFIG_X86_64 */
|
||||||
|
if (auto_eoi)
|
||||||
|
/*
|
||||||
|
* In AEOI mode we just have to mask the interrupt
|
||||||
|
* when acking.
|
||||||
|
*/
|
||||||
|
i8259A_chip.mask_ack = disable_8259A_irq;
|
||||||
|
else
|
||||||
|
i8259A_chip.mask_ack = mask_and_ack_8259A;
|
||||||
|
|
||||||
|
udelay(100); /* wait for 8259A to initialize */
|
||||||
|
|
||||||
|
outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
|
||||||
|
outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
|
||||||
|
|
||||||
|
spin_unlock_irqrestore(&i8259A_lock, flags);
|
||||||
|
}
|
||||||
|
|
@ -21,302 +21,7 @@
|
||||||
#include <asm/arch_hooks.h>
|
#include <asm/arch_hooks.h>
|
||||||
#include <asm/i8259.h>
|
#include <asm/i8259.h>
|
||||||
|
|
||||||
/*
|
|
||||||
* This is the 'legacy' 8259A Programmable Interrupt Controller,
|
|
||||||
* present in the majority of PC/AT boxes.
|
|
||||||
* plus some generic x86 specific things if generic specifics makes
|
|
||||||
* any sense at all.
|
|
||||||
*/
|
|
||||||
|
|
||||||
static int i8259A_auto_eoi;
|
|
||||||
DEFINE_SPINLOCK(i8259A_lock);
|
|
||||||
static void mask_and_ack_8259A(unsigned int);
|
|
||||||
|
|
||||||
static struct irq_chip i8259A_chip = {
|
|
||||||
.name = "XT-PIC",
|
|
||||||
.mask = disable_8259A_irq,
|
|
||||||
.disable = disable_8259A_irq,
|
|
||||||
.unmask = enable_8259A_irq,
|
|
||||||
.mask_ack = mask_and_ack_8259A,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* 8259A PIC functions to handle ISA devices:
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* This contains the irq mask for both 8259A irq controllers,
|
|
||||||
*/
|
|
||||||
unsigned int cached_irq_mask = 0xffff;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
|
|
||||||
* boards the timer interrupt is not really connected to any IO-APIC pin,
|
|
||||||
* it's fed to the master 8259A's IR0 line only.
|
|
||||||
*
|
|
||||||
* Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
|
|
||||||
* this 'mixed mode' IRQ handling costs nothing because it's only used
|
|
||||||
* at IRQ setup time.
|
|
||||||
*/
|
|
||||||
unsigned long io_apic_irqs;
|
|
||||||
|
|
||||||
void disable_8259A_irq(unsigned int irq)
|
|
||||||
{
|
|
||||||
unsigned int mask = 1 << irq;
|
|
||||||
unsigned long flags;
|
|
||||||
|
|
||||||
spin_lock_irqsave(&i8259A_lock, flags);
|
|
||||||
cached_irq_mask |= mask;
|
|
||||||
if (irq & 8)
|
|
||||||
outb(cached_slave_mask, PIC_SLAVE_IMR);
|
|
||||||
else
|
|
||||||
outb(cached_master_mask, PIC_MASTER_IMR);
|
|
||||||
spin_unlock_irqrestore(&i8259A_lock, flags);
|
|
||||||
}
|
|
||||||
|
|
||||||
void enable_8259A_irq(unsigned int irq)
|
|
||||||
{
|
|
||||||
unsigned int mask = ~(1 << irq);
|
|
||||||
unsigned long flags;
|
|
||||||
|
|
||||||
spin_lock_irqsave(&i8259A_lock, flags);
|
|
||||||
cached_irq_mask &= mask;
|
|
||||||
if (irq & 8)
|
|
||||||
outb(cached_slave_mask, PIC_SLAVE_IMR);
|
|
||||||
else
|
|
||||||
outb(cached_master_mask, PIC_MASTER_IMR);
|
|
||||||
spin_unlock_irqrestore(&i8259A_lock, flags);
|
|
||||||
}
|
|
||||||
|
|
||||||
int i8259A_irq_pending(unsigned int irq)
|
|
||||||
{
|
|
||||||
unsigned int mask = 1<<irq;
|
|
||||||
unsigned long flags;
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
spin_lock_irqsave(&i8259A_lock, flags);
|
|
||||||
if (irq < 8)
|
|
||||||
ret = inb(PIC_MASTER_CMD) & mask;
|
|
||||||
else
|
|
||||||
ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
|
|
||||||
spin_unlock_irqrestore(&i8259A_lock, flags);
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
void make_8259A_irq(unsigned int irq)
|
|
||||||
{
|
|
||||||
disable_irq_nosync(irq);
|
|
||||||
io_apic_irqs &= ~(1<<irq);
|
|
||||||
set_irq_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq,
|
|
||||||
"XT");
|
|
||||||
enable_irq(irq);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* This function assumes to be called rarely. Switching between
|
|
||||||
* 8259A registers is slow.
|
|
||||||
* This has to be protected by the irq controller spinlock
|
|
||||||
* before being called.
|
|
||||||
*/
|
|
||||||
static inline int i8259A_irq_real(unsigned int irq)
|
|
||||||
{
|
|
||||||
int value;
|
|
||||||
int irqmask = 1<<irq;
|
|
||||||
|
|
||||||
if (irq < 8) {
|
|
||||||
outb(0x0B,PIC_MASTER_CMD); /* ISR register */
|
|
||||||
value = inb(PIC_MASTER_CMD) & irqmask;
|
|
||||||
outb(0x0A,PIC_MASTER_CMD); /* back to the IRR register */
|
|
||||||
return value;
|
|
||||||
}
|
|
||||||
outb(0x0B,PIC_SLAVE_CMD); /* ISR register */
|
|
||||||
value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
|
|
||||||
outb(0x0A,PIC_SLAVE_CMD); /* back to the IRR register */
|
|
||||||
return value;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Careful! The 8259A is a fragile beast, it pretty
|
|
||||||
* much _has_ to be done exactly like this (mask it
|
|
||||||
* first, _then_ send the EOI, and the order of EOI
|
|
||||||
* to the two 8259s is important!
|
|
||||||
*/
|
|
||||||
static void mask_and_ack_8259A(unsigned int irq)
|
|
||||||
{
|
|
||||||
unsigned int irqmask = 1 << irq;
|
|
||||||
unsigned long flags;
|
|
||||||
|
|
||||||
spin_lock_irqsave(&i8259A_lock, flags);
|
|
||||||
/*
|
|
||||||
* Lightweight spurious IRQ detection. We do not want
|
|
||||||
* to overdo spurious IRQ handling - it's usually a sign
|
|
||||||
* of hardware problems, so we only do the checks we can
|
|
||||||
* do without slowing down good hardware unnecessarily.
|
|
||||||
*
|
|
||||||
* Note that IRQ7 and IRQ15 (the two spurious IRQs
|
|
||||||
* usually resulting from the 8259A-1|2 PICs) occur
|
|
||||||
* even if the IRQ is masked in the 8259A. Thus we
|
|
||||||
* can check spurious 8259A IRQs without doing the
|
|
||||||
* quite slow i8259A_irq_real() call for every IRQ.
|
|
||||||
* This does not cover 100% of spurious interrupts,
|
|
||||||
* but should be enough to warn the user that there
|
|
||||||
* is something bad going on ...
|
|
||||||
*/
|
|
||||||
if (cached_irq_mask & irqmask)
|
|
||||||
goto spurious_8259A_irq;
|
|
||||||
cached_irq_mask |= irqmask;
|
|
||||||
|
|
||||||
handle_real_irq:
|
|
||||||
if (irq & 8) {
|
|
||||||
inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
|
|
||||||
outb(cached_slave_mask, PIC_SLAVE_IMR);
|
|
||||||
outb(0x60+(irq&7),PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
|
|
||||||
outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
|
|
||||||
} else {
|
|
||||||
inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
|
|
||||||
outb(cached_master_mask, PIC_MASTER_IMR);
|
|
||||||
outb(0x60+irq,PIC_MASTER_CMD); /* 'Specific EOI to master */
|
|
||||||
}
|
|
||||||
spin_unlock_irqrestore(&i8259A_lock, flags);
|
|
||||||
return;
|
|
||||||
|
|
||||||
spurious_8259A_irq:
|
|
||||||
/*
|
|
||||||
* this is the slow path - should happen rarely.
|
|
||||||
*/
|
|
||||||
if (i8259A_irq_real(irq))
|
|
||||||
/*
|
|
||||||
* oops, the IRQ _is_ in service according to the
|
|
||||||
* 8259A - not spurious, go handle it.
|
|
||||||
*/
|
|
||||||
goto handle_real_irq;
|
|
||||||
|
|
||||||
{
|
|
||||||
static int spurious_irq_mask;
|
|
||||||
/*
|
|
||||||
* At this point we can be sure the IRQ is spurious,
|
|
||||||
* lets ACK and report it. [once per IRQ]
|
|
||||||
*/
|
|
||||||
if (!(spurious_irq_mask & irqmask)) {
|
|
||||||
printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
|
|
||||||
spurious_irq_mask |= irqmask;
|
|
||||||
}
|
|
||||||
atomic_inc(&irq_err_count);
|
|
||||||
/*
|
|
||||||
* Theoretically we do not have to handle this IRQ,
|
|
||||||
* but in Linux this does not cause problems and is
|
|
||||||
* simpler for us.
|
|
||||||
*/
|
|
||||||
goto handle_real_irq;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static char irq_trigger[2];
|
|
||||||
/**
|
|
||||||
* ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
|
|
||||||
*/
|
|
||||||
static void restore_ELCR(char *trigger)
|
|
||||||
{
|
|
||||||
outb(trigger[0], 0x4d0);
|
|
||||||
outb(trigger[1], 0x4d1);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void save_ELCR(char *trigger)
|
|
||||||
{
|
|
||||||
/* IRQ 0,1,2,8,13 are marked as reserved */
|
|
||||||
trigger[0] = inb(0x4d0) & 0xF8;
|
|
||||||
trigger[1] = inb(0x4d1) & 0xDE;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int i8259A_resume(struct sys_device *dev)
|
|
||||||
{
|
|
||||||
init_8259A(i8259A_auto_eoi);
|
|
||||||
restore_ELCR(irq_trigger);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int i8259A_suspend(struct sys_device *dev, pm_message_t state)
|
|
||||||
{
|
|
||||||
save_ELCR(irq_trigger);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int i8259A_shutdown(struct sys_device *dev)
|
|
||||||
{
|
|
||||||
/* Put the i8259A into a quiescent state that
|
|
||||||
* the kernel initialization code can get it
|
|
||||||
* out of.
|
|
||||||
*/
|
|
||||||
outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
|
|
||||||
outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-1 */
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct sysdev_class i8259_sysdev_class = {
|
|
||||||
.name = "i8259",
|
|
||||||
.suspend = i8259A_suspend,
|
|
||||||
.resume = i8259A_resume,
|
|
||||||
.shutdown = i8259A_shutdown,
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct sys_device device_i8259A = {
|
|
||||||
.id = 0,
|
|
||||||
.cls = &i8259_sysdev_class,
|
|
||||||
};
|
|
||||||
|
|
||||||
static int __init i8259A_init_sysfs(void)
|
|
||||||
{
|
|
||||||
int error = sysdev_class_register(&i8259_sysdev_class);
|
|
||||||
if (!error)
|
|
||||||
error = sysdev_register(&device_i8259A);
|
|
||||||
return error;
|
|
||||||
}
|
|
||||||
|
|
||||||
device_initcall(i8259A_init_sysfs);
|
|
||||||
|
|
||||||
void init_8259A(int auto_eoi)
|
|
||||||
{
|
|
||||||
unsigned long flags;
|
|
||||||
|
|
||||||
i8259A_auto_eoi = auto_eoi;
|
|
||||||
|
|
||||||
spin_lock_irqsave(&i8259A_lock, flags);
|
|
||||||
|
|
||||||
outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
|
|
||||||
outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* outb_pic - this has to work on a wide range of PC hardware.
|
|
||||||
*/
|
|
||||||
outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
|
|
||||||
outb_pic(0x20 + 0, PIC_MASTER_IMR); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
|
|
||||||
outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */
|
|
||||||
if (auto_eoi) /* master does Auto EOI */
|
|
||||||
outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
|
|
||||||
else /* master expects normal EOI */
|
|
||||||
outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
|
|
||||||
|
|
||||||
outb_pic(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
|
|
||||||
outb_pic(0x20 + 8, PIC_SLAVE_IMR); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
|
|
||||||
outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR); /* 8259A-2 is a slave on master's IR2 */
|
|
||||||
outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
|
|
||||||
if (auto_eoi)
|
|
||||||
/*
|
|
||||||
* In AEOI mode we just have to mask the interrupt
|
|
||||||
* when acking.
|
|
||||||
*/
|
|
||||||
i8259A_chip.mask_ack = disable_8259A_irq;
|
|
||||||
else
|
|
||||||
i8259A_chip.mask_ack = mask_and_ack_8259A;
|
|
||||||
|
|
||||||
udelay(100); /* wait for 8259A to initialize */
|
|
||||||
|
|
||||||
outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
|
|
||||||
outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
|
|
||||||
|
|
||||||
spin_unlock_irqrestore(&i8259A_lock, flags);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Note that on a 486, we don't want to do a SIGFPE on an irq13
|
* Note that on a 486, we don't want to do a SIGFPE on an irq13
|
||||||
|
|
|
||||||
|
|
@ -87,315 +87,6 @@ static void (*__initdata interrupt[NR_VECTORS - FIRST_EXTERNAL_VECTOR])(void) =
|
||||||
#undef IRQ
|
#undef IRQ
|
||||||
#undef IRQLIST_16
|
#undef IRQLIST_16
|
||||||
|
|
||||||
/*
|
|
||||||
* This is the 'legacy' 8259A Programmable Interrupt Controller,
|
|
||||||
* present in the majority of PC/AT boxes.
|
|
||||||
* plus some generic x86 specific things if generic specifics makes
|
|
||||||
* any sense at all.
|
|
||||||
* this file should become arch/i386/kernel/irq.c when the old irq.c
|
|
||||||
* moves to arch independent land
|
|
||||||
*/
|
|
||||||
|
|
||||||
static int i8259A_auto_eoi;
|
|
||||||
DEFINE_SPINLOCK(i8259A_lock);
|
|
||||||
static void mask_and_ack_8259A(unsigned int);
|
|
||||||
|
|
||||||
static struct irq_chip i8259A_chip = {
|
|
||||||
.name = "XT-PIC",
|
|
||||||
.mask = disable_8259A_irq,
|
|
||||||
.disable = disable_8259A_irq,
|
|
||||||
.unmask = enable_8259A_irq,
|
|
||||||
.mask_ack = mask_and_ack_8259A,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* 8259A PIC functions to handle ISA devices:
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* This contains the irq mask for both 8259A irq controllers,
|
|
||||||
*/
|
|
||||||
unsigned int cached_irq_mask = 0xffff;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
|
|
||||||
* boards the timer interrupt is not really connected to any IO-APIC pin,
|
|
||||||
* it's fed to the master 8259A's IR0 line only.
|
|
||||||
*
|
|
||||||
* Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
|
|
||||||
* this 'mixed mode' IRQ handling costs nothing because it's only used
|
|
||||||
* at IRQ setup time.
|
|
||||||
*/
|
|
||||||
unsigned long io_apic_irqs;
|
|
||||||
|
|
||||||
void disable_8259A_irq(unsigned int irq)
|
|
||||||
{
|
|
||||||
unsigned int mask = 1 << irq;
|
|
||||||
unsigned long flags;
|
|
||||||
|
|
||||||
spin_lock_irqsave(&i8259A_lock, flags);
|
|
||||||
cached_irq_mask |= mask;
|
|
||||||
if (irq & 8)
|
|
||||||
outb(cached_slave_mask, PIC_SLAVE_IMR);
|
|
||||||
else
|
|
||||||
outb(cached_master_mask, PIC_MASTER_IMR);
|
|
||||||
spin_unlock_irqrestore(&i8259A_lock, flags);
|
|
||||||
}
|
|
||||||
|
|
||||||
void enable_8259A_irq(unsigned int irq)
|
|
||||||
{
|
|
||||||
unsigned int mask = ~(1 << irq);
|
|
||||||
unsigned long flags;
|
|
||||||
|
|
||||||
spin_lock_irqsave(&i8259A_lock, flags);
|
|
||||||
cached_irq_mask &= mask;
|
|
||||||
if (irq & 8)
|
|
||||||
outb(cached_slave_mask, PIC_SLAVE_IMR);
|
|
||||||
else
|
|
||||||
outb(cached_master_mask, PIC_MASTER_IMR);
|
|
||||||
spin_unlock_irqrestore(&i8259A_lock, flags);
|
|
||||||
}
|
|
||||||
|
|
||||||
int i8259A_irq_pending(unsigned int irq)
|
|
||||||
{
|
|
||||||
unsigned int mask = 1<<irq;
|
|
||||||
unsigned long flags;
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
spin_lock_irqsave(&i8259A_lock, flags);
|
|
||||||
if (irq < 8)
|
|
||||||
ret = inb(PIC_MASTER_CMD) & mask;
|
|
||||||
else
|
|
||||||
ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
|
|
||||||
spin_unlock_irqrestore(&i8259A_lock, flags);
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
void make_8259A_irq(unsigned int irq)
|
|
||||||
{
|
|
||||||
disable_irq_nosync(irq);
|
|
||||||
io_apic_irqs &= ~(1<<irq);
|
|
||||||
set_irq_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq,
|
|
||||||
"XT");
|
|
||||||
enable_irq(irq);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* This function assumes to be called rarely. Switching between
|
|
||||||
* 8259A registers is slow.
|
|
||||||
* This has to be protected by the irq controller spinlock
|
|
||||||
* before being called.
|
|
||||||
*/
|
|
||||||
static inline int i8259A_irq_real(unsigned int irq)
|
|
||||||
{
|
|
||||||
int value;
|
|
||||||
int irqmask = 1<<irq;
|
|
||||||
|
|
||||||
if (irq < 8) {
|
|
||||||
outb(0x0B,PIC_MASTER_CMD); /* ISR register */
|
|
||||||
value = inb(PIC_MASTER_CMD) & irqmask;
|
|
||||||
outb(0x0A,PIC_MASTER_CMD); /* back to the IRR register */
|
|
||||||
return value;
|
|
||||||
}
|
|
||||||
outb(0x0B,PIC_SLAVE_CMD); /* ISR register */
|
|
||||||
value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
|
|
||||||
outb(0x0A,PIC_SLAVE_CMD); /* back to the IRR register */
|
|
||||||
return value;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Careful! The 8259A is a fragile beast, it pretty
|
|
||||||
* much _has_ to be done exactly like this (mask it
|
|
||||||
* first, _then_ send the EOI, and the order of EOI
|
|
||||||
* to the two 8259s is important!
|
|
||||||
*/
|
|
||||||
static void mask_and_ack_8259A(unsigned int irq)
|
|
||||||
{
|
|
||||||
unsigned int irqmask = 1 << irq;
|
|
||||||
unsigned long flags;
|
|
||||||
|
|
||||||
spin_lock_irqsave(&i8259A_lock, flags);
|
|
||||||
/*
|
|
||||||
* Lightweight spurious IRQ detection. We do not want
|
|
||||||
* to overdo spurious IRQ handling - it's usually a sign
|
|
||||||
* of hardware problems, so we only do the checks we can
|
|
||||||
* do without slowing down good hardware unnecessarily.
|
|
||||||
*
|
|
||||||
* Note that IRQ7 and IRQ15 (the two spurious IRQs
|
|
||||||
* usually resulting from the 8259A-1|2 PICs) occur
|
|
||||||
* even if the IRQ is masked in the 8259A. Thus we
|
|
||||||
* can check spurious 8259A IRQs without doing the
|
|
||||||
* quite slow i8259A_irq_real() call for every IRQ.
|
|
||||||
* This does not cover 100% of spurious interrupts,
|
|
||||||
* but should be enough to warn the user that there
|
|
||||||
* is something bad going on ...
|
|
||||||
*/
|
|
||||||
if (cached_irq_mask & irqmask)
|
|
||||||
goto spurious_8259A_irq;
|
|
||||||
cached_irq_mask |= irqmask;
|
|
||||||
|
|
||||||
handle_real_irq:
|
|
||||||
if (irq & 8) {
|
|
||||||
inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
|
|
||||||
outb(cached_slave_mask, PIC_SLAVE_IMR);
|
|
||||||
/* 'Specific EOI' to slave */
|
|
||||||
outb(0x60+(irq&7),PIC_SLAVE_CMD);
|
|
||||||
/* 'Specific EOI' to master-IRQ2 */
|
|
||||||
outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD);
|
|
||||||
} else {
|
|
||||||
inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
|
|
||||||
outb(cached_master_mask, PIC_MASTER_IMR);
|
|
||||||
/* 'Specific EOI' to master */
|
|
||||||
outb(0x60+irq,PIC_MASTER_CMD);
|
|
||||||
}
|
|
||||||
spin_unlock_irqrestore(&i8259A_lock, flags);
|
|
||||||
return;
|
|
||||||
|
|
||||||
spurious_8259A_irq:
|
|
||||||
/*
|
|
||||||
* this is the slow path - should happen rarely.
|
|
||||||
*/
|
|
||||||
if (i8259A_irq_real(irq))
|
|
||||||
/*
|
|
||||||
* oops, the IRQ _is_ in service according to the
|
|
||||||
* 8259A - not spurious, go handle it.
|
|
||||||
*/
|
|
||||||
goto handle_real_irq;
|
|
||||||
|
|
||||||
{
|
|
||||||
static int spurious_irq_mask;
|
|
||||||
/*
|
|
||||||
* At this point we can be sure the IRQ is spurious,
|
|
||||||
* lets ACK and report it. [once per IRQ]
|
|
||||||
*/
|
|
||||||
if (!(spurious_irq_mask & irqmask)) {
|
|
||||||
printk(KERN_DEBUG
|
|
||||||
"spurious 8259A interrupt: IRQ%d.\n", irq);
|
|
||||||
spurious_irq_mask |= irqmask;
|
|
||||||
}
|
|
||||||
atomic_inc(&irq_err_count);
|
|
||||||
/*
|
|
||||||
* Theoretically we do not have to handle this IRQ,
|
|
||||||
* but in Linux this does not cause problems and is
|
|
||||||
* simpler for us.
|
|
||||||
*/
|
|
||||||
goto handle_real_irq;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static char irq_trigger[2];
|
|
||||||
/**
|
|
||||||
* ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
|
|
||||||
*/
|
|
||||||
static void restore_ELCR(char *trigger)
|
|
||||||
{
|
|
||||||
outb(trigger[0], 0x4d0);
|
|
||||||
outb(trigger[1], 0x4d1);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void save_ELCR(char *trigger)
|
|
||||||
{
|
|
||||||
/* IRQ 0,1,2,8,13 are marked as reserved */
|
|
||||||
trigger[0] = inb(0x4d0) & 0xF8;
|
|
||||||
trigger[1] = inb(0x4d1) & 0xDE;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int i8259A_resume(struct sys_device *dev)
|
|
||||||
{
|
|
||||||
init_8259A(i8259A_auto_eoi);
|
|
||||||
restore_ELCR(irq_trigger);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int i8259A_suspend(struct sys_device *dev, pm_message_t state)
|
|
||||||
{
|
|
||||||
save_ELCR(irq_trigger);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int i8259A_shutdown(struct sys_device *dev)
|
|
||||||
{
|
|
||||||
/* Put the i8259A into a quiescent state that
|
|
||||||
* the kernel initialization code can get it
|
|
||||||
* out of.
|
|
||||||
*/
|
|
||||||
outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
|
|
||||||
outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-1 */
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct sysdev_class i8259_sysdev_class = {
|
|
||||||
.name = "i8259",
|
|
||||||
.suspend = i8259A_suspend,
|
|
||||||
.resume = i8259A_resume,
|
|
||||||
.shutdown = i8259A_shutdown,
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct sys_device device_i8259A = {
|
|
||||||
.id = 0,
|
|
||||||
.cls = &i8259_sysdev_class,
|
|
||||||
};
|
|
||||||
|
|
||||||
static int __init i8259A_init_sysfs(void)
|
|
||||||
{
|
|
||||||
int error = sysdev_class_register(&i8259_sysdev_class);
|
|
||||||
if (!error)
|
|
||||||
error = sysdev_register(&device_i8259A);
|
|
||||||
return error;
|
|
||||||
}
|
|
||||||
|
|
||||||
device_initcall(i8259A_init_sysfs);
|
|
||||||
|
|
||||||
void init_8259A(int auto_eoi)
|
|
||||||
{
|
|
||||||
unsigned long flags;
|
|
||||||
|
|
||||||
i8259A_auto_eoi = auto_eoi;
|
|
||||||
|
|
||||||
spin_lock_irqsave(&i8259A_lock, flags);
|
|
||||||
|
|
||||||
outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
|
|
||||||
outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* outb_pic - this has to work on a wide range of PC hardware.
|
|
||||||
*/
|
|
||||||
outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
|
|
||||||
/* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 */
|
|
||||||
outb_pic(IRQ0_VECTOR, PIC_MASTER_IMR);
|
|
||||||
/* 8259A-1 (the master) has a slave on IR2 */
|
|
||||||
outb_pic(0x04, PIC_MASTER_IMR);
|
|
||||||
if (auto_eoi) /* master does Auto EOI */
|
|
||||||
outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
|
|
||||||
else /* master expects normal EOI */
|
|
||||||
outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
|
|
||||||
|
|
||||||
outb_pic(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
|
|
||||||
/* ICW2: 8259A-2 IR0-7 mapped to 0x38-0x3f */
|
|
||||||
outb_pic(IRQ8_VECTOR, PIC_SLAVE_IMR);
|
|
||||||
/* 8259A-2 is a slave on master's IR2 */
|
|
||||||
outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);
|
|
||||||
/* (slave's support for AEOI in flat mode is to be investigated) */
|
|
||||||
outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);
|
|
||||||
|
|
||||||
if (auto_eoi)
|
|
||||||
/*
|
|
||||||
* In AEOI mode we just have to mask the interrupt
|
|
||||||
* when acking.
|
|
||||||
*/
|
|
||||||
i8259A_chip.mask_ack = disable_8259A_irq;
|
|
||||||
else
|
|
||||||
i8259A_chip.mask_ack = mask_and_ack_8259A;
|
|
||||||
|
|
||||||
udelay(100); /* wait for 8259A to initialize */
|
|
||||||
|
|
||||||
outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
|
|
||||||
outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
|
|
||||||
|
|
||||||
spin_unlock_irqrestore(&i8259A_lock, flags);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -55,4 +55,6 @@ static inline void outb_pic(unsigned char value, unsigned int port)
|
||||||
udelay(2);
|
udelay(2);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
extern struct irq_chip i8259A_chip;
|
||||||
|
|
||||||
#endif /* __ASM_I8259_H__ */
|
#endif /* __ASM_I8259_H__ */
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue