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linux-sg2042
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Merge branch 'depends/rmk/restart' into next/cleanup 

Conflicts:
	arch/arm/mach-at91/at91cap9.c
	arch/arm/mach-at91/at91sam9260.c
	arch/arm/mach-at91/at91sam9261.c
	arch/arm/mach-at91/at91sam9263.c
	arch/arm/mach-at91/at91sam9g45.c
	arch/arm/mach-at91/at91sam9rl.c
	arch/arm/mach-exynos/cpu.c
	arch/arm/mach-shmobile/board-kota2.c

This resolves a bunch of conflicts between the arm-soc tree
and changes from the arm tree that have gone upstream.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2012-01-07 11:51:28 +00:00
parent 70d84a6431 0575fb754d
commit 40ba95fdf1
931 changed files with 8051 additions and 7922 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
Documentation/ABI/testing/sysfs-bus-rbd
View File

@ -57,13 +57,6 @@ create_snap
$ echo <snap-name> > /sys/bus/rbd/devices/<dev-id>/snap_create $ echo <snap-name> > /sys/bus/rbd/devices/<dev-id>/snap_create
rollback_snap
Rolls back data to the specified snapshot. This goes over the entire
list of rados blocks and sends a rollback command to each.
$ echo <snap-name> > /sys/bus/rbd/devices/<dev-id>/snap_rollback
snap_* snap_*
A directory per each snapshot A directory per each snapshot

22
MAINTAINERS
View File

@ -1124,13 +1124,6 @@ S: Supported
F: arch/arm/mach-shmobile/ F: arch/arm/mach-shmobile/
F: drivers/sh/ F: drivers/sh/
ARM/TELECHIPS ARM ARCHITECTURE
M: "Hans J. Koch" <hjk@hansjkoch.de>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/plat-tcc/
F: arch/arm/mach-tcc8k/
ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org> M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@ -3101,6 +3094,7 @@ F: include/linux/hid*
HIGH-RESOLUTION TIMERS, CLOCKEVENTS, DYNTICKS HIGH-RESOLUTION TIMERS, CLOCKEVENTS, DYNTICKS
M: Thomas Gleixner <tglx@linutronix.de> M: Thomas Gleixner <tglx@linutronix.de>
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git timers/core
S: Maintained S: Maintained
F: Documentation/timers/ F: Documentation/timers/
F: kernel/hrtimer.c F: kernel/hrtimer.c
@ -3610,7 +3604,7 @@ F: net/irda/
IRQ SUBSYSTEM IRQ SUBSYSTEM
M: Thomas Gleixner <tglx@linutronix.de> M: Thomas Gleixner <tglx@linutronix.de>
S: Maintained S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip.git irq/core T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core
F: kernel/irq/ F: kernel/irq/
ISAPNP ISAPNP
@ -4098,7 +4092,7 @@ F: drivers/hwmon/lm90.c
LOCKDEP AND LOCKSTAT LOCKDEP AND LOCKSTAT
M: Peter Zijlstra <peterz@infradead.org> M: Peter Zijlstra <peterz@infradead.org>
M: Ingo Molnar <mingo@redhat.com> M: Ingo Molnar <mingo@redhat.com>
T: git git://git.kernel.org/pub/scm/linux/kernel/git/peterz/linux-2.6-lockdep.git T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git core/locking
S: Maintained S: Maintained
F: Documentation/lockdep*.txt F: Documentation/lockdep*.txt
F: Documentation/lockstat.txt F: Documentation/lockstat.txt
@ -4280,7 +4274,9 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-2.6.git
S: Maintained S: Maintained
F: Documentation/dvb/ F: Documentation/dvb/
F: Documentation/video4linux/ F: Documentation/video4linux/
F: Documentation/DocBook/media/
F: drivers/media/ F: drivers/media/
F: drivers/staging/media/
F: include/media/ F: include/media/
F: include/linux/dvb/ F: include/linux/dvb/
F: include/linux/videodev*.h F: include/linux/videodev*.h
@ -5086,6 +5082,7 @@ M: Peter Zijlstra <a.p.zijlstra@chello.nl>
M: Paul Mackerras <paulus@samba.org> M: Paul Mackerras <paulus@samba.org>
M: Ingo Molnar <mingo@elte.hu> M: Ingo Molnar <mingo@elte.hu>
M: Arnaldo Carvalho de Melo <acme@ghostprotocols.net> M: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git perf/core
S: Supported S: Supported
F: kernel/events/* F: kernel/events/*
F: include/linux/perf_event.h F: include/linux/perf_event.h
@ -5174,6 +5171,7 @@ F: drivers/scsi/pm8001/
POSIX CLOCKS and TIMERS POSIX CLOCKS and TIMERS
M: Thomas Gleixner <tglx@linutronix.de> M: Thomas Gleixner <tglx@linutronix.de>
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git timers/core
S: Supported S: Supported
F: fs/timerfd.c F: fs/timerfd.c
F: include/linux/timer* F: include/linux/timer*
@ -5689,6 +5687,7 @@ F: drivers/dma/dw_dmac.c
TIMEKEEPING, NTP TIMEKEEPING, NTP
M: John Stultz <johnstul@us.ibm.com> M: John Stultz <johnstul@us.ibm.com>
M: Thomas Gleixner <tglx@linutronix.de> M: Thomas Gleixner <tglx@linutronix.de>
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git timers/core
S: Supported S: Supported
F: include/linux/clocksource.h F: include/linux/clocksource.h
F: include/linux/time.h F: include/linux/time.h
@ -5713,6 +5712,7 @@ F: drivers/watchdog/sc1200wdt.c
SCHEDULER SCHEDULER
M: Ingo Molnar <mingo@elte.hu> M: Ingo Molnar <mingo@elte.hu>
M: Peter Zijlstra <peterz@infradead.org> M: Peter Zijlstra <peterz@infradead.org>
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git sched/core
S: Maintained S: Maintained
F: kernel/sched* F: kernel/sched*
F: include/linux/sched.h F: include/linux/sched.h
@ -6640,7 +6640,7 @@ TRACING
M: Steven Rostedt <rostedt@goodmis.org> M: Steven Rostedt <rostedt@goodmis.org>
M: Frederic Weisbecker <fweisbec@gmail.com> M: Frederic Weisbecker <fweisbec@gmail.com>
M: Ingo Molnar <mingo@redhat.com> M: Ingo Molnar <mingo@redhat.com>
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip.git perf/core T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git perf/core
S: Maintained S: Maintained
F: Documentation/trace/ftrace.txt F: Documentation/trace/ftrace.txt
F: arch/*/*/*/ftrace.h F: arch/*/*/*/ftrace.h
@ -7390,7 +7390,7 @@ M: Thomas Gleixner <tglx@linutronix.de>
M: Ingo Molnar <mingo@redhat.com> M: Ingo Molnar <mingo@redhat.com>
M: "H. Peter Anvin" <hpa@zytor.com> M: "H. Peter Anvin" <hpa@zytor.com>
M: x86@kernel.org M: x86@kernel.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/x86/linux-2.6-x86.git T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/core
S: Maintained S: Maintained
F: Documentation/x86/ F: Documentation/x86/
F: arch/x86/ F: arch/x86/

2
Makefile
View File

@ -1,7 +1,7 @@
VERSION = 3 VERSION = 3
PATCHLEVEL = 2 PATCHLEVEL = 2
SUBLEVEL = 0 SUBLEVEL = 0
EXTRAVERSION = -rc5 EXTRAVERSION = -rc7
NAME = Saber-toothed Squirrel NAME = Saber-toothed Squirrel
# *DOCUMENTATION* # *DOCUMENTATION*

15
arch/arm/Kconfig
View File

@ -220,8 +220,9 @@ config NEED_MACH_MEMORY_H
be avoided when possible. be avoided when possible.
config PHYS_OFFSET config PHYS_OFFSET
hex "Physical address of main memory" hex "Physical address of main memory" if MMU
depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
default DRAM_BASE if !MMU
help help
Please provide the physical address corresponding to the Please provide the physical address corresponding to the
location of main memory in your system. location of main memory in your system.
@ -868,16 +869,6 @@ config ARCH_SHARK
Support for the StrongARM based Digital DNARD machine, also known Support for the StrongARM based Digital DNARD machine, also known
as "Shark" (<http://www.shark-linux.de/shark.html>). as "Shark" (<http://www.shark-linux.de/shark.html>).
config ARCH_TCC_926
bool "Telechips TCC ARM926-based systems"
select CLKSRC_MMIO
select CPU_ARM926T
select HAVE_CLK
select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
help
Support for Telechips TCC ARM926-based systems.
config ARCH_U300 config ARCH_U300
bool "ST-Ericsson U300 Series" bool "ST-Ericsson U300 Series"
depends on MMU depends on MMU
@ -1059,8 +1050,6 @@ source "arch/arm/plat-s5p/Kconfig"
source "arch/arm/plat-spear/Kconfig" source "arch/arm/plat-spear/Kconfig"
source "arch/arm/plat-tcc/Kconfig"
if ARCH_S3C2410 if ARCH_S3C2410
source "arch/arm/mach-s3c2410/Kconfig" source "arch/arm/mach-s3c2410/Kconfig"
source "arch/arm/mach-s3c2412/Kconfig" source "arch/arm/mach-s3c2412/Kconfig"

2
arch/arm/Makefile
View File

@ -184,7 +184,6 @@ machine-$(CONFIG_ARCH_EXYNOS4) := exynos
machine-$(CONFIG_ARCH_SA1100) := sa1100 machine-$(CONFIG_ARCH_SA1100) := sa1100
machine-$(CONFIG_ARCH_SHARK) := shark machine-$(CONFIG_ARCH_SHARK) := shark
machine-$(CONFIG_ARCH_SHMOBILE) := shmobile machine-$(CONFIG_ARCH_SHMOBILE) := shmobile
machine-$(CONFIG_ARCH_TCC8K) := tcc8k
machine-$(CONFIG_ARCH_TEGRA) := tegra machine-$(CONFIG_ARCH_TEGRA) := tegra
machine-$(CONFIG_ARCH_U300) := u300 machine-$(CONFIG_ARCH_U300) := u300
machine-$(CONFIG_ARCH_U8500) := ux500 machine-$(CONFIG_ARCH_U8500) := ux500
@ -204,7 +203,6 @@ machine-$(CONFIG_ARCH_ZYNQ) := zynq
plat-$(CONFIG_ARCH_MXC) := mxc plat-$(CONFIG_ARCH_MXC) := mxc
plat-$(CONFIG_ARCH_OMAP) := omap plat-$(CONFIG_ARCH_OMAP) := omap
plat-$(CONFIG_ARCH_S3C64XX) := samsung plat-$(CONFIG_ARCH_S3C64XX) := samsung
plat-$(CONFIG_ARCH_TCC_926) := tcc
plat-$(CONFIG_ARCH_ZYNQ) := versatile plat-$(CONFIG_ARCH_ZYNQ) := versatile
plat-$(CONFIG_PLAT_IOP) := iop plat-$(CONFIG_PLAT_IOP) := iop
plat-$(CONFIG_PLAT_NOMADIK) := nomadik plat-$(CONFIG_PLAT_NOMADIK) := nomadik

1
arch/arm/include/asm/hardware/iop3xx.h
View File

@ -234,6 +234,7 @@ extern int iop3xx_get_init_atu(void);
void iop3xx_map_io(void); void iop3xx_map_io(void);
void iop_init_cp6_handler(void); void iop_init_cp6_handler(void);
void iop_init_time(unsigned long tickrate); void iop_init_time(unsigned long tickrate);
void iop3xx_restart(char, const char *);
static inline u32 read_tmr0(void) static inline u32 read_tmr0(void)
{ {

1
arch/arm/include/asm/system.h
View File

@ -108,7 +108,6 @@ extern void __show_regs(struct pt_regs *);
extern int __pure cpu_architecture(void); extern int __pure cpu_architecture(void);
extern void cpu_init(void); extern void cpu_init(void);
void arm_machine_restart(char mode, const char *cmd);
void soft_restart(unsigned long); void soft_restart(unsigned long);
extern void (*arm_pm_restart)(char str, const char *cmd); extern void (*arm_pm_restart)(char str, const char *cmd);

16
arch/arm/include/asm/unwind.h
View File

@ -30,14 +30,15 @@ enum unwind_reason_code {
}; };
struct unwind_idx { struct unwind_idx {
unsigned long addr; unsigned long addr_offset;
unsigned long insn; unsigned long insn;
}; };
struct unwind_table { struct unwind_table {
struct list_head list; struct list_head list;
struct unwind_idx *start; const struct unwind_idx *start;
struct unwind_idx *stop; const struct unwind_idx *origin;
const struct unwind_idx *stop;
unsigned long begin_addr; unsigned long begin_addr;
unsigned long end_addr; unsigned long end_addr;
}; };
@ -49,15 +50,6 @@ extern struct unwind_table *unwind_table_add(unsigned long start,
extern void unwind_table_del(struct unwind_table *tab); extern void unwind_table_del(struct unwind_table *tab);
extern void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk); extern void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk);
#ifdef CONFIG_ARM_UNWIND
extern int __init unwind_init(void);
#else
static inline int __init unwind_init(void)
{
return 0;
}
#endif
#endif /* !__ASSEMBLY__ */ #endif /* !__ASSEMBLY__ */
#ifdef CONFIG_ARM_UNWIND #ifdef CONFIG_ARM_UNWIND

3
arch/arm/kernel/perf_event.c
View File

@ -639,6 +639,9 @@ static struct platform_device_id armpmu_plat_device_ids[] = {
static int __devinit armpmu_device_probe(struct platform_device *pdev) static int __devinit armpmu_device_probe(struct platform_device *pdev)
{ {
if (!cpu_pmu)
return -ENODEV;
cpu_pmu->plat_device = pdev; cpu_pmu->plat_device = pdev;
return 0; return 0;
} }

10
arch/arm/kernel/process.c
View File

@ -147,14 +147,8 @@ void soft_restart(unsigned long addr)
BUG(); BUG();
} }
void arm_machine_restart(char mode, const char *cmd) static void null_restart(char mode, const char *cmd)
{ {
/* Disable interrupts first */
local_irq_disable();
local_fiq_disable();
/* Call the architecture specific reboot code. */
arch_reset(mode, cmd);
} }
/* /*
@ -163,7 +157,7 @@ void arm_machine_restart(char mode, const char *cmd)
void (*pm_power_off)(void); void (*pm_power_off)(void);
EXPORT_SYMBOL(pm_power_off); EXPORT_SYMBOL(pm_power_off);
void (*arm_pm_restart)(char str, const char *cmd) = arm_machine_restart; void (*arm_pm_restart)(char str, const char *cmd) = null_restart;
EXPORT_SYMBOL_GPL(arm_pm_restart); EXPORT_SYMBOL_GPL(arm_pm_restart);
static void do_nothing(void *unused) static void do_nothing(void *unused)

14
arch/arm/kernel/setup.c
View File

@ -902,8 +902,6 @@ void __init setup_arch(char **cmdline_p)
{ {
struct machine_desc *mdesc; struct machine_desc *mdesc;
unwind_init();
setup_processor(); setup_processor();
mdesc = setup_machine_fdt(__atags_pointer); mdesc = setup_machine_fdt(__atags_pointer);
if (!mdesc) if (!mdesc)
@ -911,6 +909,12 @@ void __init setup_arch(char **cmdline_p)
machine_desc = mdesc; machine_desc = mdesc;
machine_name = mdesc->name; machine_name = mdesc->name;
#ifdef CONFIG_ZONE_DMA
if (mdesc->dma_zone_size) {
extern unsigned long arm_dma_zone_size;
arm_dma_zone_size = mdesc->dma_zone_size;
}
#endif
if (mdesc->restart_mode) if (mdesc->restart_mode)
reboot_setup(&mdesc->restart_mode); reboot_setup(&mdesc->restart_mode);
@ -945,12 +949,6 @@ void __init setup_arch(char **cmdline_p)
tcm_init(); tcm_init();
#ifdef CONFIG_ZONE_DMA
if (mdesc->dma_zone_size) {
extern unsigned long arm_dma_zone_size;
arm_dma_zone_size = mdesc->dma_zone_size;
}
#endif
#ifdef CONFIG_MULTI_IRQ_HANDLER #ifdef CONFIG_MULTI_IRQ_HANDLER
handle_arch_irq = mdesc->handle_irq; handle_arch_irq = mdesc->handle_irq;
#endif #endif

133
arch/arm/kernel/unwind.c
View File

@ -67,7 +67,7 @@ EXPORT_SYMBOL(__aeabi_unwind_cpp_pr2);
struct unwind_ctrl_block { struct unwind_ctrl_block {
unsigned long vrs[16]; /* virtual register set */ unsigned long vrs[16]; /* virtual register set */
unsigned long *insn; /* pointer to the current instructions word */ const unsigned long *insn; /* pointer to the current instructions word */
int entries; /* number of entries left to interpret */ int entries; /* number of entries left to interpret */
int byte; /* current byte number in the instructions word */ int byte; /* current byte number in the instructions word */
}; };
@ -83,8 +83,9 @@ enum regs {
PC = 15 PC = 15
}; };
extern struct unwind_idx __start_unwind_idx[]; extern const struct unwind_idx __start_unwind_idx[];
extern struct unwind_idx __stop_unwind_idx[]; static const struct unwind_idx *__origin_unwind_idx;
extern const struct unwind_idx __stop_unwind_idx[];
static DEFINE_SPINLOCK(unwind_lock); static DEFINE_SPINLOCK(unwind_lock);
static LIST_HEAD(unwind_tables); static LIST_HEAD(unwind_tables);
@ -98,45 +99,99 @@ static LIST_HEAD(unwind_tables);
}) })
/* /*
* Binary search in the unwind index. The entries entries are * Binary search in the unwind index. The entries are
* guaranteed to be sorted in ascending order by the linker. * guaranteed to be sorted in ascending order by the linker.
*
* start = first entry
* origin = first entry with positive offset (or stop if there is no such entry)
* stop - 1 = last entry
*/ */
static struct unwind_idx *search_index(unsigned long addr, static const struct unwind_idx *search_index(unsigned long addr,
struct unwind_idx *first, const struct unwind_idx *start,
struct unwind_idx *last) const struct unwind_idx *origin,
const struct unwind_idx *stop)
{ {
pr_debug("%s(%08lx, %p, %p)\n", __func__, addr, first, last); unsigned long addr_prel31;
if (addr < first->addr) { pr_debug("%s(%08lx, %p, %p, %p)\n",
pr_warning("unwind: Unknown symbol address %08lx\n", addr); __func__, addr, start, origin, stop);
return NULL;
} else if (addr >= last->addr)
return last;
while (first < last - 1) { /*
struct unwind_idx *mid = first + ((last - first + 1) >> 1); * only search in the section with the matching sign. This way the
* prel31 numbers can be compared as unsigned longs.
*/
if (addr < (unsigned long)start)
/* negative offsets: [start; origin) */
stop = origin;
else
/* positive offsets: [origin; stop) */
start = origin;
if (addr < mid->addr) /* prel31 for address relavive to start */
last = mid; addr_prel31 = (addr - (unsigned long)start) & 0x7fffffff;
else
first = mid; while (start < stop - 1) {
const struct unwind_idx *mid = start + ((stop - start) >> 1);
/*
* As addr_prel31 is relative to start an offset is needed to
* make it relative to mid.
*/
if (addr_prel31 - ((unsigned long)mid - (unsigned long)start) <
mid->addr_offset)
stop = mid;
else {
/* keep addr_prel31 relative to start */
addr_prel31 -= ((unsigned long)mid -
(unsigned long)start);
start = mid;
}
} }
return first; if (likely(start->addr_offset <= addr_prel31))
return start;
else {
pr_warning("unwind: Unknown symbol address %08lx\n", addr);
return NULL;
}
} }
static struct unwind_idx *unwind_find_idx(unsigned long addr) static const struct unwind_idx *unwind_find_origin(
const struct unwind_idx *start, const struct unwind_idx *stop)
{ {
struct unwind_idx *idx = NULL; pr_debug("%s(%p, %p)\n", __func__, start, stop);
while (start < stop) {
const struct unwind_idx *mid = start + ((stop - start) >> 1);
if (mid->addr_offset >= 0x40000000)
/* negative offset */
start = mid + 1;
else
/* positive offset */
stop = mid;
}
pr_debug("%s -> %p\n", __func__, stop);
return stop;
}
static const struct unwind_idx *unwind_find_idx(unsigned long addr)
{
const struct unwind_idx *idx = NULL;
unsigned long flags; unsigned long flags;
pr_debug("%s(%08lx)\n", __func__, addr); pr_debug("%s(%08lx)\n", __func__, addr);
if (core_kernel_text(addr)) if (core_kernel_text(addr)) {
if (unlikely(!__origin_unwind_idx))
__origin_unwind_idx =
unwind_find_origin(__start_unwind_idx,
__stop_unwind_idx);
/* main unwind table */ /* main unwind table */
idx = search_index(addr, __start_unwind_idx, idx = search_index(addr, __start_unwind_idx,
__stop_unwind_idx - 1); __origin_unwind_idx,
else { __stop_unwind_idx);
} else {
/* module unwind tables */ /* module unwind tables */
struct unwind_table *table; struct unwind_table *table;
@ -145,7 +200,8 @@ static struct unwind_idx *unwind_find_idx(unsigned long addr)
if (addr >= table->begin_addr && if (addr >= table->begin_addr &&
addr < table->end_addr) { addr < table->end_addr) {
idx = search_index(addr, table->start, idx = search_index(addr, table->start,
table->stop - 1); table->origin,
table->stop);
/* Move-to-front to exploit common traces */ /* Move-to-front to exploit common traces */
list_move(&table->list, &unwind_tables); list_move(&table->list, &unwind_tables);
break; break;
@ -274,7 +330,7 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
int unwind_frame(struct stackframe *frame) int unwind_frame(struct stackframe *frame)
{ {
unsigned long high, low; unsigned long high, low;
struct unwind_idx *idx; const struct unwind_idx *idx;
struct unwind_ctrl_block ctrl; struct unwind_ctrl_block ctrl;
/* only go to a higher address on the stack */ /* only go to a higher address on the stack */
@ -399,7 +455,6 @@ struct unwind_table *unwind_table_add(unsigned long start, unsigned long size,
unsigned long text_size) unsigned long text_size)
{ {
unsigned long flags; unsigned long flags;
struct unwind_idx *idx;
struct unwind_table *tab = kmalloc(sizeof(*tab), GFP_KERNEL); struct unwind_table *tab = kmalloc(sizeof(*tab), GFP_KERNEL);
pr_debug("%s(%08lx, %08lx, %08lx, %08lx)\n", __func__, start, size, pr_debug("%s(%08lx, %08lx, %08lx, %08lx)\n", __func__, start, size,
@ -408,15 +463,12 @@ struct unwind_table *unwind_table_add(unsigned long start, unsigned long size,
if (!tab) if (!tab)
return tab; return tab;
tab->start = (struct unwind_idx *)start; tab->start = (const struct unwind_idx *)start;
tab->stop = (struct unwind_idx *)(start + size); tab->stop = (const struct unwind_idx *)(start + size);
tab->origin = unwind_find_origin(tab->start, tab->stop);
tab->begin_addr = text_addr; tab->begin_addr = text_addr;
tab->end_addr = text_addr + text_size; tab->end_addr = text_addr + text_size;
/* Convert the symbol addresses to absolute values */
for (idx = tab->start; idx < tab->stop; idx++)
idx->addr = prel31_to_addr(&idx->addr);
spin_lock_irqsave(&unwind_lock, flags); spin_lock_irqsave(&unwind_lock, flags);
list_add_tail(&tab->list, &unwind_tables); list_add_tail(&tab->list, &unwind_tables);
spin_unlock_irqrestore(&unwind_lock, flags); spin_unlock_irqrestore(&unwind_lock, flags);
@ -437,16 +489,3 @@ void unwind_table_del(struct unwind_table *tab)
kfree(tab); kfree(tab);
} }
int __init unwind_init(void)
{
struct unwind_idx *idx;
/* Convert the symbol addresses to absolute values */
for (idx = __start_unwind_idx; idx < __stop_unwind_idx; idx++)
idx->addr = prel31_to_addr(&idx->addr);
pr_debug("unwind: ARM stack unwinding initialised\n");
return 0;
}

4
arch/arm/mach-at91/at91cap9.c
View File

@ -314,7 +314,7 @@ static struct at91_gpio_bank at91cap9_gpio[] __initdata = {
} }
}; };
static void at91cap9_reset(void) static void at91cap9_restart(char mode, const char *cmd)
{ {
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
} }
@ -337,7 +337,7 @@ static void __init at91cap9_ioremap_registers(void)
static void __init at91cap9_initialize(void) static void __init at91cap9_initialize(void)
{ {
at91_arch_reset = at91cap9_reset; arm_pm_restart = at91cap9_restart;
at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1); at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
/* Register GPIO subsystem */ /* Register GPIO subsystem */

4
arch/arm/mach-at91/at91rm9200.c
View File

@ -289,7 +289,7 @@ static struct at91_gpio_bank at91rm9200_gpio[] __initdata = {
} }
}; };
static void at91rm9200_reset(void) static void at91rm9200_restart(char mode, const char *cmd)
{ {
/* /*
* Perform a hardware reset with the use of the Watchdog timer. * Perform a hardware reset with the use of the Watchdog timer.
@ -314,7 +314,7 @@ static void __init at91rm9200_ioremap_registers(void)
static void __init at91rm9200_initialize(void) static void __init at91rm9200_initialize(void)
{ {
at91_arch_reset = at91rm9200_reset; arm_pm_restart = at91rm9200_restart;
at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1) at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
| (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3) | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
| (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5) | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)

2
arch/arm/mach-at91/at91sam9260.c
View File

@ -329,7 +329,7 @@ static void __init at91sam9260_ioremap_registers(void)
static void __init at91sam9260_initialize(void) static void __init at91sam9260_initialize(void)
{ {
at91_arch_reset = at91sam9_alt_reset; arm_pm_restart = at91sam9_alt_restart;
at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1) at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
| (1 << AT91SAM9260_ID_IRQ2); | (1 << AT91SAM9260_ID_IRQ2);

2
arch/arm/mach-at91/at91sam9261.c
View File

@ -287,7 +287,7 @@ static void __init at91sam9261_ioremap_registers(void)
static void __init at91sam9261_initialize(void) static void __init at91sam9261_initialize(void)
{ {
at91_arch_reset = at91sam9_alt_reset; arm_pm_restart = at91sam9_alt_restart;
at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1) at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
| (1 << AT91SAM9261_ID_IRQ2); | (1 << AT91SAM9261_ID_IRQ2);

2
arch/arm/mach-at91/at91sam9263.c
View File

@ -308,7 +308,7 @@ static void __init at91sam9263_ioremap_registers(void)
static void __init at91sam9263_initialize(void) static void __init at91sam9263_initialize(void)
{ {
at91_arch_reset = at91sam9_alt_reset; arm_pm_restart = at91sam9_alt_restart;
at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1); at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
/* Register GPIO subsystem */ /* Register GPIO subsystem */

9
arch/arm/mach-at91/at91sam9_alt_reset.S
View File

@ -14,20 +14,15 @@
*/ */
#include <linux/linkage.h> #include <linux/linkage.h>
#include <asm/system.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/at91sam9_sdramc.h> #include <mach/at91sam9_sdramc.h>
#include <mach/at91_rstc.h> #include <mach/at91_rstc.h>
.arm .arm
.globl at91sam9_alt_reset .globl at91sam9_alt_restart
at91sam9_alt_reset: mrc p15, 0, r0, c1, c0, 0 at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants
orr r0, r0, #CR_I
mcr p15, 0, r0, c1, c0, 0 @ enable I-cache
ldr r0, .at91_va_base_sdramc @ preload constants
ldr r1, .at91_va_base_rstc_cr ldr r1, .at91_va_base_rstc_cr
mov r2, #1 mov r2, #1

4
arch/arm/mach-at91/at91sam9g45.c
View File

@ -318,7 +318,7 @@ static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
} }
}; };
static void at91sam9g45_reset(void) static void at91sam9g45_restart(char mode, const char *cmd)
{ {
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
} }
@ -342,7 +342,7 @@ static void __init at91sam9g45_ioremap_registers(void)
static void __init at91sam9g45_initialize(void) static void __init at91sam9g45_initialize(void)
{ {
at91_arch_reset = at91sam9g45_reset; arm_pm_restart = at91sam9g45_restart;
at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0); at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
/* Register GPIO subsystem */ /* Register GPIO subsystem */

2
arch/arm/mach-at91/at91sam9rl.c
View File

@ -292,7 +292,7 @@ static void __init at91sam9rl_ioremap_registers(void)
static void __init at91sam9rl_initialize(void) static void __init at91sam9rl_initialize(void)
{ {
at91_arch_reset = at91sam9_alt_reset; arm_pm_restart = at91sam9_alt_restart;
at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0); at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
/* Register GPIO subsystem */ /* Register GPIO subsystem */

3
arch/arm/mach-at91/generic.h
View File

@ -58,7 +58,7 @@ extern void at91_irq_suspend(void);
extern void at91_irq_resume(void); extern void at91_irq_resume(void);
/* reset */ /* reset */
extern void at91sam9_alt_reset(void); extern void at91sam9_alt_restart(char, const char *);
/* shutdown */ /* shutdown */
extern void at91_ioremap_shdwc(u32 base_addr); extern void at91_ioremap_shdwc(u32 base_addr);
@ -74,5 +74,4 @@ struct at91_gpio_bank {
extern void __init at91_gpio_init(struct at91_gpio_bank *, int nr_banks); extern void __init at91_gpio_init(struct at91_gpio_bank *, int nr_banks);
extern void __init at91_gpio_irq_setup(void); extern void __init at91_gpio_irq_setup(void);
extern void (*at91_arch_reset)(void);
extern int at91_extern_irq; extern int at91_extern_irq;

9
arch/arm/mach-at91/include/mach/system.h
View File

@ -47,13 +47,4 @@ static inline void arch_idle(void)
#endif #endif
} }
void (*at91_arch_reset)(void);
static inline void arch_reset(char mode, const char *cmd)
{
/* call the CPU-specific reset function */
if (at91_arch_reset)
(at91_arch_reset)();
}
#endif #endif

25
arch/arm/mach-bcmring/arch.c
View File

@ -49,7 +49,29 @@ HW_DECLARE_SPINLOCK(gpio)
#endif #endif
/* sysctl */ /* sysctl */
int bcmring_arch_warm_reboot; /* do a warm reboot on hard reset */ static int bcmring_arch_warm_reboot; /* do a warm reboot on hard reset */
static void bcmring_restart(char mode, const char *cmd)
{
printk("arch_reset:%c %x\n", mode, bcmring_arch_warm_reboot);
if (mode == 'h') {
/* Reboot configured in proc entry */
if (bcmring_arch_warm_reboot) {
printk("warm reset\n");
/* Issue Warm reset (do not reset ethernet switch, keep alive) */
chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_WARM);
} else {
/* Force reset of everything */
printk("force reset\n");
chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
}
} else {
/* Force reset of everything */
printk("force reset\n");
chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
}
}
static struct ctl_table_header *bcmring_sysctl_header; static struct ctl_table_header *bcmring_sysctl_header;
@ -173,4 +195,5 @@ MACHINE_START(BCMRING, "BCMRING")
.init_irq = bcmring_init_irq, .init_irq = bcmring_init_irq,
.timer = &bcmring_timer, .timer = &bcmring_timer,
.init_machine = bcmring_init_machine .init_machine = bcmring_init_machine
.restart = bcmring_restart,
MACHINE_END MACHINE_END

26
arch/arm/mach-bcmring/include/mach/system.h
View File

@ -20,35 +20,9 @@
#ifndef __ASM_ARCH_SYSTEM_H #ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H #define __ASM_ARCH_SYSTEM_H
#include <mach/csp/chipcHw_inline.h>
extern int bcmring_arch_warm_reboot;
static inline void arch_idle(void) static inline void arch_idle(void)
{ {
cpu_do_idle(); cpu_do_idle();
} }
static inline void arch_reset(char mode, const char *cmd)
{
printk("arch_reset:%c %x\n", mode, bcmring_arch_warm_reboot);
if (mode == 'h') {
/* Reboot configured in proc entry */
if (bcmring_arch_warm_reboot) {
printk("warm reset\n");
/* Issue Warm reset (do not reset ethernet switch, keep alive) */
chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_WARM);
} else {
/* Force reset of everything */
printk("force reset\n");
chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
}
} else {
/* Force reset of everything */
printk("force reset\n");
chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
}
}
#endif #endif

1
arch/arm/mach-clps711x/autcpu12.c
View File

@ -68,5 +68,6 @@ MACHINE_START(AUTCPU12, "autronix autcpu12")
.map_io = autcpu12_map_io, .map_io = autcpu12_map_io,
.init_irq = clps711x_init_irq, .init_irq = clps711x_init_irq,
.timer = &clps711x_timer, .timer = &clps711x_timer,
.restart = clps711x_restart,
MACHINE_END MACHINE_END

1
arch/arm/mach-clps711x/cdb89712.c
View File

@ -59,4 +59,5 @@ MACHINE_START(CDB89712, "Cirrus-CDB89712")
.map_io = cdb89712_map_io, .map_io = cdb89712_map_io,
.init_irq = clps711x_init_irq, .init_irq = clps711x_init_irq,
.timer = &clps711x_timer, .timer = &clps711x_timer,
.restart = clps711x_restart,
MACHINE_END MACHINE_END

1
arch/arm/mach-clps711x/ceiva.c
View File

@ -60,4 +60,5 @@ MACHINE_START(CEIVA, "CEIVA/Polaroid Photo MAX Digital Picture Frame")
.map_io = ceiva_map_io, .map_io = ceiva_map_io,
.init_irq = clps711x_init_irq, .init_irq = clps711x_init_irq,
.timer = &clps711x_timer, .timer = &clps711x_timer,
.restart = clps711x_restart,
MACHINE_END MACHINE_END

1
arch/arm/mach-clps711x/clep7312.c
View File

@ -41,5 +41,6 @@ MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312")
.map_io = clps711x_map_io, .map_io = clps711x_map_io,
.init_irq = clps711x_init_irq, .init_irq = clps711x_init_irq,
.timer = &clps711x_timer, .timer = &clps711x_timer,
.restart = clps711x_restart,
MACHINE_END MACHINE_END

5
arch/arm/mach-clps711x/common.c
View File

@ -220,3 +220,8 @@ struct sys_timer clps711x_timer = {
.init = clps711x_timer_init, .init = clps711x_timer_init,
.offset = clps711x_gettimeoffset, .offset = clps711x_gettimeoffset,
}; };
void clps711x_restart(char mode, const char *cmd)
{
soft_restart(0);
}

1
arch/arm/mach-clps711x/common.h
View File

@ -9,3 +9,4 @@ struct sys_timer;
extern void clps711x_map_io(void); extern void clps711x_map_io(void);
extern void clps711x_init_irq(void); extern void clps711x_init_irq(void);
extern struct sys_timer clps711x_timer; extern struct sys_timer clps711x_timer;
extern void clps711x_restart(char mode, const char *cmd);

1
arch/arm/mach-clps711x/edb7211-arch.c
View File

@ -62,4 +62,5 @@ MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
.reserve = edb7211_reserve, .reserve = edb7211_reserve,
.init_irq = clps711x_init_irq, .init_irq = clps711x_init_irq,
.timer = &clps711x_timer, .timer = &clps711x_timer,
.restart = clps711x_restart,
MACHINE_END MACHINE_END

1
arch/arm/mach-clps711x/fortunet.c
View File

@ -78,4 +78,5 @@ MACHINE_START(FORTUNET, "ARM-FortuNet")
.map_io = clps711x_map_io, .map_io = clps711x_map_io,
.init_irq = clps711x_init_irq, .init_irq = clps711x_init_irq,
.timer = &clps711x_timer, .timer = &clps711x_timer,
.restart = clps711x_restart,
MACHINE_END MACHINE_END

5
arch/arm/mach-clps711x/include/mach/system.h
View File

@ -32,9 +32,4 @@ static inline void arch_idle(void)
mov r0, r0"); mov r0, r0");
} }
static inline void arch_reset(char mode, const char *cmd)
{
soft_restart(0);
}
#endif #endif

1
arch/arm/mach-clps711x/p720t.c
View File

@ -93,6 +93,7 @@ MACHINE_START(P720T, "ARM-Prospector720T")
.map_io = p720t_map_io, .map_io = p720t_map_io,
.init_irq = clps711x_init_irq, .init_irq = clps711x_init_irq,
.timer = &clps711x_timer, .timer = &clps711x_timer,
.restart = clps711x_restart,
MACHINE_END MACHINE_END
static int p720t_hw_init(void) static int p720t_hw_init(void)

1
arch/arm/mach-cns3xxx/cns3420vb.c
View File

@ -204,4 +204,5 @@ MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
.timer = &cns3xxx_timer, .timer = &cns3xxx_timer,
.handle_irq = gic_handle_irq, .handle_irq = gic_handle_irq,
.init_machine = cns3420_init, .init_machine = cns3420_init,
.restart = cns3xxx_restart,
MACHINE_END MACHINE_END

1
arch/arm/mach-cns3xxx/core.h
View File

@ -22,5 +22,6 @@ static inline void cns3xxx_l2x0_init(void) {}
void __init cns3xxx_map_io(void); void __init cns3xxx_map_io(void);
void __init cns3xxx_init_irq(void); void __init cns3xxx_init_irq(void);
void cns3xxx_power_off(void); void cns3xxx_power_off(void);
void cns3xxx_restart(char, const char *);
#endif /* __CNS3XXX_CORE_H */ #endif /* __CNS3XXX_CORE_H */

3
arch/arm/mach-cns3xxx/include/mach/system.h
View File

@ -11,7 +11,6 @@
#ifndef __MACH_SYSTEM_H #ifndef __MACH_SYSTEM_H
#define __MACH_SYSTEM_H #define __MACH_SYSTEM_H
#include <linux/io.h>
#include <asm/proc-fns.h> #include <asm/proc-fns.h>
static inline void arch_idle(void) static inline void arch_idle(void)
@ -23,6 +22,4 @@ static inline void arch_idle(void)
cpu_do_idle(); cpu_do_idle();
} }
void arch_reset(char mode, const char *cmd);
#endif #endif

4
arch/arm/mach-cns3xxx/pm.c
View File

@ -11,9 +11,9 @@
#include <linux/io.h> #include <linux/io.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/atomic.h> #include <linux/atomic.h>
#include <mach/system.h>
#include <mach/cns3xxx.h> #include <mach/cns3xxx.h>
#include <mach/pm.h> #include <mach/pm.h>
#include "core.h"
void cns3xxx_pwr_clk_en(unsigned int block) void cns3xxx_pwr_clk_en(unsigned int block)
{ {
@ -89,7 +89,7 @@ void cns3xxx_pwr_soft_rst(unsigned int block)
} }
EXPORT_SYMBOL(cns3xxx_pwr_soft_rst); EXPORT_SYMBOL(cns3xxx_pwr_soft_rst);
void arch_reset(char mode, const char *cmd) void cns3xxx_restart(char mode, const char *cmd)
{ {
/* /*
* To reset, we hit the on-board reset register * To reset, we hit the on-board reset register

1
arch/arm/mach-davinci/board-da830-evm.c
View File

@ -682,4 +682,5 @@ MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM")
.timer = &davinci_timer, .timer = &davinci_timer,
.init_machine = da830_evm_init, .init_machine = da830_evm_init,
.dma_zone_size = SZ_128M, .dma_zone_size = SZ_128M,
.restart = da8xx_restart,
MACHINE_END MACHINE_END

1
arch/arm/mach-davinci/board-da850-evm.c
View File

@ -1411,4 +1411,5 @@ MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM")
.timer = &davinci_timer, .timer = &davinci_timer,
.init_machine = da850_evm_init, .init_machine = da850_evm_init,
.dma_zone_size = SZ_128M, .dma_zone_size = SZ_128M,
.restart = da8xx_restart,
MACHINE_END MACHINE_END

1
arch/arm/mach-davinci/board-dm355-evm.c
View File

@ -357,4 +357,5 @@ MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
.timer = &davinci_timer, .timer = &davinci_timer,
.init_machine = dm355_evm_init, .init_machine = dm355_evm_init,
.dma_zone_size = SZ_128M, .dma_zone_size = SZ_128M,
.restart = davinci_restart,
MACHINE_END MACHINE_END

1
arch/arm/mach-davinci/board-dm355-leopard.c
View File

@ -276,4 +276,5 @@ MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard")
.timer = &davinci_timer, .timer = &davinci_timer,
.init_machine = dm355_leopard_init, .init_machine = dm355_leopard_init,
.dma_zone_size = SZ_128M, .dma_zone_size = SZ_128M,
.restart = davinci_restart,
MACHINE_END MACHINE_END

1
arch/arm/mach-davinci/board-dm365-evm.c
View File

@ -618,5 +618,6 @@ MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
.timer = &davinci_timer, .timer = &davinci_timer,
.init_machine = dm365_evm_init, .init_machine = dm365_evm_init,
.dma_zone_size = SZ_128M, .dma_zone_size = SZ_128M,
.restart = davinci_restart,
MACHINE_END MACHINE_END

1
arch/arm/mach-davinci/board-dm644x-evm.c
View File

@ -719,4 +719,5 @@ MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
.timer = &davinci_timer, .timer = &davinci_timer,
.init_machine = davinci_evm_init, .init_machine = davinci_evm_init,
.dma_zone_size = SZ_128M, .dma_zone_size = SZ_128M,
.restart = davinci_restart,
MACHINE_END MACHINE_END

2
arch/arm/mach-davinci/board-dm646x-evm.c
View File

@ -799,6 +799,7 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
.timer = &davinci_timer, .timer = &davinci_timer,
.init_machine = evm_init, .init_machine = evm_init,
.dma_zone_size = SZ_128M, .dma_zone_size = SZ_128M,
.restart = davinci_restart,
MACHINE_END MACHINE_END
MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM") MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
@ -808,5 +809,6 @@ MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
.timer = &davinci_timer, .timer = &davinci_timer,
.init_machine = evm_init, .init_machine = evm_init,
.dma_zone_size = SZ_128M, .dma_zone_size = SZ_128M,
.restart = davinci_restart,
MACHINE_END MACHINE_END

1
arch/arm/mach-davinci/board-mityomapl138.c
View File

@ -573,4 +573,5 @@ MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
.timer = &davinci_timer, .timer = &davinci_timer,
.init_machine = mityomapl138_init, .init_machine = mityomapl138_init,
.dma_zone_size = SZ_128M, .dma_zone_size = SZ_128M,
.restart = da8xx_restart,
MACHINE_END MACHINE_END

1
arch/arm/mach-davinci/board-neuros-osd2.c
View File

@ -278,4 +278,5 @@ MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
.timer = &davinci_timer, .timer = &davinci_timer,
.init_machine = davinci_ntosd2_init, .init_machine = davinci_ntosd2_init,
.dma_zone_size = SZ_128M, .dma_zone_size = SZ_128M,
.restart = davinci_restart,
MACHINE_END MACHINE_END

1
arch/arm/mach-davinci/board-omapl138-hawk.c
View File

@ -344,4 +344,5 @@ MACHINE_START(OMAPL138_HAWKBOARD, "AM18x/OMAP-L138 Hawkboard")
.timer = &davinci_timer, .timer = &davinci_timer,
.init_machine = omapl138_hawk_init, .init_machine = omapl138_hawk_init,
.dma_zone_size = SZ_128M, .dma_zone_size = SZ_128M,
.restart = da8xx_restart,
MACHINE_END MACHINE_END

1
arch/arm/mach-davinci/board-sffsdr.c
View File

@ -157,4 +157,5 @@ MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
.timer = &davinci_timer, .timer = &davinci_timer,
.init_machine = davinci_sffsdr_init, .init_machine = davinci_sffsdr_init,
.dma_zone_size = SZ_128M, .dma_zone_size = SZ_128M,
.restart = davinci_restart,
MACHINE_END MACHINE_END

1
arch/arm/mach-davinci/board-tnetv107x-evm.c
View File

@ -283,4 +283,5 @@ MACHINE_START(TNETV107X, "TNETV107X EVM")
.timer = &davinci_timer, .timer = &davinci_timer,
.init_machine = tnetv107x_evm_board_init, .init_machine = tnetv107x_evm_board_init,
.dma_zone_size = SZ_128M, .dma_zone_size = SZ_128M,
.restart = tnetv107x_restart,
MACHINE_END MACHINE_END

3
arch/arm/mach-davinci/common.c
View File

@ -97,9 +97,6 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info)
local_flush_tlb_all(); local_flush_tlb_all();
flush_cache_all(); flush_cache_all();
if (!davinci_soc_info.reset)
davinci_soc_info.reset = davinci_watchdog_reset;
/* /*
* We want to check CPU revision early for cpu_is_xxxx() macros. * We want to check CPU revision early for cpu_is_xxxx() macros.
* IO space mapping must be initialized before we can do that. * IO space mapping must be initialized before we can do that.

1
arch/arm/mach-davinci/da830.c
View File

@ -1201,7 +1201,6 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
.gpio_irq = IRQ_DA8XX_GPIO0, .gpio_irq = IRQ_DA8XX_GPIO0,
.serial_dev = &da8xx_serial_device, .serial_dev = &da8xx_serial_device,
.emac_pdata = &da8xx_emac_pdata, .emac_pdata = &da8xx_emac_pdata,
.reset_device = &da8xx_wdt_device,
}; };
void __init da830_init(void) void __init da830_init(void)

1
arch/arm/mach-davinci/da850.c
View File

@ -1121,7 +1121,6 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
.emac_pdata = &da8xx_emac_pdata, .emac_pdata = &da8xx_emac_pdata,
.sram_dma = DA8XX_ARM_RAM_BASE, .sram_dma = DA8XX_ARM_RAM_BASE,
.sram_len = SZ_8K, .sram_len = SZ_8K,
.reset_device = &da8xx_wdt_device,
}; };
void __init da850_init(void) void __init da850_init(void)

5
arch/arm/mach-davinci/devices-da8xx.c
View File

@ -363,6 +363,11 @@ struct platform_device da8xx_wdt_device = {
.resource = da8xx_watchdog_resources, .resource = da8xx_watchdog_resources,
}; };
void da8xx_restart(char mode, const char *cmd)
{
davinci_watchdog_reset(&da8xx_wdt_device);
}
int __init da8xx_register_watchdog(void) int __init da8xx_register_watchdog(void)
{ {
return platform_device_register(&da8xx_wdt_device); return platform_device_register(&da8xx_wdt_device);

5
arch/arm/mach-davinci/devices.c
View File

@ -291,6 +291,11 @@ struct platform_device davinci_wdt_device = {
.resource = wdt_resources, .resource = wdt_resources,
}; };
void davinci_restart(char mode, const char *cmd)
{
davinci_watchdog_reset(&davinci_wdt_device);
}
static void davinci_init_wdt(void) static void davinci_init_wdt(void)
{ {
platform_device_register(&davinci_wdt_device); platform_device_register(&davinci_wdt_device);

1
arch/arm/mach-davinci/dm355.c
View File

@ -853,7 +853,6 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
.serial_dev = &dm355_serial_device, .serial_dev = &dm355_serial_device,
.sram_dma = 0x00010000, .sram_dma = 0x00010000,
.sram_len = SZ_32K, .sram_len = SZ_32K,
.reset_device = &davinci_wdt_device,
}; };
void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata) void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata)

1
arch/arm/mach-davinci/dm365.c
View File

@ -1083,7 +1083,6 @@ static struct davinci_soc_info davinci_soc_info_dm365 = {
.emac_pdata = &dm365_emac_pdata, .emac_pdata = &dm365_emac_pdata,
.sram_dma = 0x00010000, .sram_dma = 0x00010000,
.sram_len = SZ_32K, .sram_len = SZ_32K,
.reset_device = &davinci_wdt_device,
}; };
void __init dm365_init_asp(struct snd_platform_data *pdata) void __init dm365_init_asp(struct snd_platform_data *pdata)

1
arch/arm/mach-davinci/dm644x.c
View File

@ -767,7 +767,6 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
.emac_pdata = &dm644x_emac_pdata, .emac_pdata = &dm644x_emac_pdata,
.sram_dma = 0x00008000, .sram_dma = 0x00008000,
.sram_len = SZ_16K, .sram_len = SZ_16K,
.reset_device = &davinci_wdt_device,
}; };
void __init dm644x_init_asp(struct snd_platform_data *pdata) void __init dm644x_init_asp(struct snd_platform_data *pdata)

1
arch/arm/mach-davinci/dm646x.c
View File

@ -854,7 +854,6 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
.emac_pdata = &dm646x_emac_pdata, .emac_pdata = &dm646x_emac_pdata,
.sram_dma = 0x10010000, .sram_dma = 0x10010000,
.sram_len = SZ_32K, .sram_len = SZ_32K,
.reset_device = &davinci_wdt_device,
}; };
void __init dm646x_init_mcasp0(struct snd_platform_data *pdata) void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)

3
arch/arm/mach-davinci/include/mach/common.h
View File

@ -77,14 +77,13 @@ struct davinci_soc_info {
struct emac_platform_data *emac_pdata; struct emac_platform_data *emac_pdata;
dma_addr_t sram_dma; dma_addr_t sram_dma;
unsigned sram_len; unsigned sram_len;
struct platform_device *reset_device;
void (*reset)(struct platform_device *);
}; };
extern struct davinci_soc_info davinci_soc_info; extern struct davinci_soc_info davinci_soc_info;
extern void davinci_common_init(struct davinci_soc_info *soc_info); extern void davinci_common_init(struct davinci_soc_info *soc_info);
extern void davinci_init_ide(void); extern void davinci_init_ide(void);
void davinci_restart(char mode, const char *cmd);
/* standard place to map on-chip SRAMs; they *may* support DMA */ /* standard place to map on-chip SRAMs; they *may* support DMA */
#define SRAM_VIRT 0xfffe0000 #define SRAM_VIRT 0xfffe0000

1
arch/arm/mach-davinci/include/mach/da8xx.h
View File

@ -91,6 +91,7 @@ int da8xx_register_cpuidle(void);
void __iomem * __init da8xx_get_mem_ctlr(void); void __iomem * __init da8xx_get_mem_ctlr(void);
int da850_register_pm(struct platform_device *pdev); int da850_register_pm(struct platform_device *pdev);
int __init da850_register_sata(unsigned long refclkpn); int __init da850_register_sata(unsigned long refclkpn);
void da8xx_restart(char mode, const char *cmd);
extern struct platform_device da8xx_serial_device; extern struct platform_device da8xx_serial_device;
extern struct emac_platform_data da8xx_emac_pdata; extern struct emac_platform_data da8xx_emac_pdata;

6
arch/arm/mach-davinci/include/mach/system.h
View File

@ -18,10 +18,4 @@ static inline void arch_idle(void)
cpu_do_idle(); cpu_do_idle();
} }
static inline void arch_reset(char mode, const char *cmd)
{
if (davinci_soc_info.reset)
davinci_soc_info.reset(davinci_soc_info.reset_device);
}
#endif /* __ASM_ARCH_SYSTEM_H */ #endif /* __ASM_ARCH_SYSTEM_H */

1
arch/arm/mach-davinci/include/mach/tnetv107x.h
View File

@ -54,6 +54,7 @@ extern struct platform_device tnetv107x_serial_device;
extern void __init tnetv107x_init(void); extern void __init tnetv107x_init(void);
extern void __init tnetv107x_devices_init(struct tnetv107x_device_info *); extern void __init tnetv107x_devices_init(struct tnetv107x_device_info *);
extern void __init tnetv107x_irq_init(void); extern void __init tnetv107x_irq_init(void);
void tnetv107x_restart(char mode, const char *cmd);
#endif #endif

7
arch/arm/mach-davinci/tnetv107x.c
View File

@ -730,6 +730,11 @@ static void tnetv107x_watchdog_reset(struct platform_device *pdev)
__raw_writel(1, &regs->kick); __raw_writel(1, &regs->kick);
} }
void tnetv107x_restart(char mode, const char *cmd)
{
tnetv107x_watchdog_reset(&tnetv107x_wdt_device);
}
static struct davinci_soc_info tnetv107x_soc_info = { static struct davinci_soc_info tnetv107x_soc_info = {
.io_desc = io_desc, .io_desc = io_desc,
.io_desc_num = ARRAY_SIZE(io_desc), .io_desc_num = ARRAY_SIZE(io_desc),
@ -752,8 +757,6 @@ static struct davinci_soc_info tnetv107x_soc_info = {
.gpio_num = TNETV107X_N_GPIO, .gpio_num = TNETV107X_N_GPIO,
.timer_info = &timer_info, .timer_info = &timer_info,
.serial_dev = &tnetv107x_serial_device, .serial_dev = &tnetv107x_serial_device,
.reset = tnetv107x_watchdog_reset,
.reset_device = &tnetv107x_wdt_device,
}; };
void __init tnetv107x_init(void) void __init tnetv107x_init(void)

1
arch/arm/mach-dove/cm-a510.c
View File

@ -93,4 +93,5 @@ MACHINE_START(CM_A510, "Compulab CM-A510 Board")
.init_early = dove_init_early, .init_early = dove_init_early,
.init_irq = dove_init_irq, .init_irq = dove_init_irq,
.timer = &dove_timer, .timer = &dove_timer,
.restart = dove_restart,
MACHINE_END MACHINE_END

16
arch/arm/mach-dove/common.c
View File

@ -292,3 +292,19 @@ void __init dove_init(void)
dove_xor0_init(); dove_xor0_init();
dove_xor1_init(); dove_xor1_init();
} }
void dove_restart(char mode, const char *cmd)
{
/*
* Enable soft reset to assert RSTOUTn.
*/
writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
/*
* Assert soft reset.
*/
writel(SOFT_RESET, SYSTEM_SOFT_RESET);
while (1)
;
}

1
arch/arm/mach-dove/common.h
View File

@ -39,5 +39,6 @@ void dove_spi1_init(void);
void dove_i2c_init(void); void dove_i2c_init(void);
void dove_sdio0_init(void); void dove_sdio0_init(void);
void dove_sdio1_init(void); void dove_sdio1_init(void);
void dove_restart(char, const char *);
#endif #endif

1
arch/arm/mach-dove/dove-db-setup.c
View File

@ -100,4 +100,5 @@ MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board")
.init_early = dove_init_early, .init_early = dove_init_early,
.init_irq = dove_init_irq, .init_irq = dove_init_irq,
.timer = &dove_timer, .timer = &dove_timer,
.restart = dove_restart,
MACHINE_END MACHINE_END

19
arch/arm/mach-dove/include/mach/system.h
View File

@ -9,28 +9,9 @@
#ifndef __ASM_ARCH_SYSTEM_H #ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H #define __ASM_ARCH_SYSTEM_H
#include <mach/bridge-regs.h>
static inline void arch_idle(void) static inline void arch_idle(void)
{ {
cpu_do_idle(); cpu_do_idle();
} }
static inline void arch_reset(char mode, const char *cmd)
{
/*
* Enable soft reset to assert RSTOUTn.
*/
writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
/*
* Assert soft reset.
*/
writel(SOFT_RESET, SYSTEM_SOFT_RESET);
while (1)
;
}
#endif #endif

6
arch/arm/mach-ebsa110/core.c
View File

@ -278,6 +278,11 @@ static int __init ebsa110_init(void)
arch_initcall(ebsa110_init); arch_initcall(ebsa110_init);
static void ebsa110_restart(char mode, const char *cmd)
{
soft_restart(0x80000000);
}
MACHINE_START(EBSA110, "EBSA110") MACHINE_START(EBSA110, "EBSA110")
/* Maintainer: Russell King */ /* Maintainer: Russell King */
.atag_offset = 0x400, .atag_offset = 0x400,
@ -287,4 +292,5 @@ MACHINE_START(EBSA110, "EBSA110")
.map_io = ebsa110_map_io, .map_io = ebsa110_map_io,
.init_irq = ebsa110_init_irq, .init_irq = ebsa110_init_irq,
.timer = &ebsa110_timer, .timer = &ebsa110_timer,
.restart = ebsa110_restart,
MACHINE_END MACHINE_END

2
arch/arm/mach-ebsa110/include/mach/system.h
View File

@ -34,6 +34,4 @@ static inline void arch_idle(void)
asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc"); asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc");
} }
#define arch_reset(mode, cmd) soft_restart(0x80000000)
#endif #endif

1
arch/arm/mach-ep93xx/adssphere.c
View File

@ -40,4 +40,5 @@ MACHINE_START(ADSSPHERE, "ADS Sphere board")
.handle_irq = vic_handle_irq, .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer, .timer = &ep93xx_timer,
.init_machine = adssphere_init_machine, .init_machine = adssphere_init_machine,
.restart = ep93xx_restart,
MACHINE_END MACHINE_END

12
arch/arm/mach-ep93xx/core.c
View File

@ -906,3 +906,15 @@ void __init ep93xx_init_devices(void)
platform_device_register(&ep93xx_ohci_device); platform_device_register(&ep93xx_ohci_device);
platform_device_register(&ep93xx_leds); platform_device_register(&ep93xx_leds);
} }
void ep93xx_restart(char mode, const char *cmd)
{
/*
* Set then clear the SWRST bit to initiate a software reset
*/
ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_SWRST);
ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_SWRST);
while (1)
;
}

8
arch/arm/mach-ep93xx/edb93xx.c
View File

@ -254,6 +254,7 @@ MACHINE_START(EDB9301, "Cirrus Logic EDB9301 Evaluation Board")
.handle_irq = vic_handle_irq, .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer, .timer = &ep93xx_timer,
.init_machine = edb93xx_init_machine, .init_machine = edb93xx_init_machine,
.restart = ep93xx_restart,
MACHINE_END MACHINE_END
#endif #endif
@ -266,6 +267,7 @@ MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board")
.handle_irq = vic_handle_irq, .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer, .timer = &ep93xx_timer,
.init_machine = edb93xx_init_machine, .init_machine = edb93xx_init_machine,
.restart = ep93xx_restart,
MACHINE_END MACHINE_END
#endif #endif
@ -278,6 +280,7 @@ MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board")
.handle_irq = vic_handle_irq, .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer, .timer = &ep93xx_timer,
.init_machine = edb93xx_init_machine, .init_machine = edb93xx_init_machine,
.restart = ep93xx_restart,
MACHINE_END MACHINE_END
#endif #endif
@ -290,6 +293,7 @@ MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board")
.handle_irq = vic_handle_irq, .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer, .timer = &ep93xx_timer,
.init_machine = edb93xx_init_machine, .init_machine = edb93xx_init_machine,
.restart = ep93xx_restart,
MACHINE_END MACHINE_END
#endif #endif
@ -302,6 +306,7 @@ MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board")
.handle_irq = vic_handle_irq, .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer, .timer = &ep93xx_timer,
.init_machine = edb93xx_init_machine, .init_machine = edb93xx_init_machine,
.restart = ep93xx_restart,
MACHINE_END MACHINE_END
#endif #endif
@ -314,6 +319,7 @@ MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board")
.handle_irq = vic_handle_irq, .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer, .timer = &ep93xx_timer,
.init_machine = edb93xx_init_machine, .init_machine = edb93xx_init_machine,
.restart = ep93xx_restart,
MACHINE_END MACHINE_END
#endif #endif
@ -326,6 +332,7 @@ MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board")
.handle_irq = vic_handle_irq, .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer, .timer = &ep93xx_timer,
.init_machine = edb93xx_init_machine, .init_machine = edb93xx_init_machine,
.restart = ep93xx_restart,
MACHINE_END MACHINE_END
#endif #endif
@ -338,5 +345,6 @@ MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board")
.handle_irq = vic_handle_irq, .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer, .timer = &ep93xx_timer,
.init_machine = edb93xx_init_machine, .init_machine = edb93xx_init_machine,
.restart = ep93xx_restart,
MACHINE_END MACHINE_END
#endif #endif

1
arch/arm/mach-ep93xx/gesbc9312.c
View File

@ -40,4 +40,5 @@ MACHINE_START(GESBC9312, "Glomation GESBC-9312-sx")
.handle_irq = vic_handle_irq, .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer, .timer = &ep93xx_timer,
.init_machine = gesbc9312_init_machine, .init_machine = gesbc9312_init_machine,
.restart = ep93xx_restart,
MACHINE_END MACHINE_END

2
arch/arm/mach-ep93xx/include/mach/platform.h
View File

@ -66,4 +66,6 @@ void ep93xx_register_ac97(void);
void ep93xx_init_devices(void); void ep93xx_init_devices(void);
extern struct sys_timer ep93xx_timer; extern struct sys_timer ep93xx_timer;
void ep93xx_restart(char, const char *);
#endif #endif

15
arch/arm/mach-ep93xx/include/mach/system.h
View File

@ -1,22 +1,7 @@
/* /*
* arch/arm/mach-ep93xx/include/mach/system.h * arch/arm/mach-ep93xx/include/mach/system.h
*/ */
#include <mach/hardware.h>
static inline void arch_idle(void) static inline void arch_idle(void)
{ {
cpu_do_idle(); cpu_do_idle();
} }
static inline void arch_reset(char mode, const char *cmd)
{
/*
* Set then clear the SWRST bit to initiate a software reset
*/
ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_SWRST);
ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_SWRST);
while (1)
;
}

4
arch/arm/mach-ep93xx/micro9.c
View File

@ -84,6 +84,7 @@ MACHINE_START(MICRO9, "Contec Micro9-High")
.handle_irq = vic_handle_irq, .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer, .timer = &ep93xx_timer,
.init_machine = micro9_init_machine, .init_machine = micro9_init_machine,
.restart = ep93xx_restart,
MACHINE_END MACHINE_END
#endif #endif
@ -96,6 +97,7 @@ MACHINE_START(MICRO9M, "Contec Micro9-Mid")
.handle_irq = vic_handle_irq, .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer, .timer = &ep93xx_timer,
.init_machine = micro9_init_machine, .init_machine = micro9_init_machine,
.restart = ep93xx_restart,
MACHINE_END MACHINE_END
#endif #endif
@ -108,6 +110,7 @@ MACHINE_START(MICRO9L, "Contec Micro9-Lite")
.handle_irq = vic_handle_irq, .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer, .timer = &ep93xx_timer,
.init_machine = micro9_init_machine, .init_machine = micro9_init_machine,
.restart = ep93xx_restart,
MACHINE_END MACHINE_END
#endif #endif
@ -120,5 +123,6 @@ MACHINE_START(MICRO9S, "Contec Micro9-Slim")
.handle_irq = vic_handle_irq, .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer, .timer = &ep93xx_timer,
.init_machine = micro9_init_machine, .init_machine = micro9_init_machine,
.restart = ep93xx_restart,
MACHINE_END MACHINE_END
#endif #endif

1
arch/arm/mach-ep93xx/simone.c
View File

@ -84,4 +84,5 @@ MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board")
.handle_irq = vic_handle_irq, .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer, .timer = &ep93xx_timer,
.init_machine = simone_init_machine, .init_machine = simone_init_machine,
.restart = ep93xx_restart,
MACHINE_END MACHINE_END

1
arch/arm/mach-ep93xx/snappercl15.c
View File

@ -181,4 +181,5 @@ MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15")
.handle_irq = vic_handle_irq, .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer, .timer = &ep93xx_timer,
.init_machine = snappercl15_init_machine, .init_machine = snappercl15_init_machine,
.restart = ep93xx_restart,
MACHINE_END MACHINE_END

1
arch/arm/mach-ep93xx/ts72xx.c
View File

@ -251,4 +251,5 @@ MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC")
.handle_irq = vic_handle_irq, .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer, .timer = &ep93xx_timer,
.init_machine = ts72xx_init_machine, .init_machine = ts72xx_init_machine,
.restart = ep93xx_restart,
MACHINE_END MACHINE_END

1
arch/arm/mach-ep93xx/vision_ep9307.c
View File

@ -361,4 +361,5 @@ MACHINE_START(VISION_EP9307, "Vision Engraving Systems EP9307")
.init_irq = ep93xx_init_irq, .init_irq = ep93xx_init_irq,
.timer = &ep93xx_timer, .timer = &ep93xx_timer,
.init_machine = vision_init_machine, .init_machine = vision_init_machine,
.restart = ep93xx_restart,
MACHINE_END MACHINE_END

9
arch/arm/mach-exynos/Makefile
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@ -10,15 +10,17 @@ obj-m :=
obj-n := obj-n :=
obj- := obj- :=
# Core support for EXYNOS4 system # Core
obj-$(CONFIG_ARCH_EXYNOS4) += cpu.o init.o clock.o irq-combiner.o setup-i2c0.o obj-$(CONFIG_ARCH_EXYNOS4) += common.o clock.o
obj-$(CONFIG_ARCH_EXYNOS4) += irq-eint.o dma.o pmu.o
obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_ARCH_EXYNOS4) += dma.o pmu.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_EXYNOS4_MCT) += mct.o obj-$(CONFIG_EXYNOS4_MCT) += mct.o
@ -45,6 +47,7 @@ obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o
obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o
obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o

3
arch/arm/mach-exynos/clock-exynos4210.c
View File

@ -23,7 +23,6 @@
#include <plat/pll.h> #include <plat/pll.h>
#include <plat/s5p-clock.h> #include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h> #include <plat/clock-clksrc.h>
#include <plat/exynos4.h>
#include <plat/pm.h> #include <plat/pm.h>
#include <mach/hardware.h> #include <mach/hardware.h>
@ -31,6 +30,8 @@
#include <mach/regs-clock.h> #include <mach/regs-clock.h>
#include <mach/exynos4-clock.h> #include <mach/exynos4-clock.h>
#include "common.h"
static struct sleep_save exynos4210_clock_save[] = { static struct sleep_save exynos4210_clock_save[] = {
SAVE_ITEM(S5P_CLKSRC_IMAGE), SAVE_ITEM(S5P_CLKSRC_IMAGE),
SAVE_ITEM(S5P_CLKSRC_LCD1), SAVE_ITEM(S5P_CLKSRC_LCD1),

3
arch/arm/mach-exynos/clock-exynos4212.c
View File

@ -23,7 +23,6 @@
#include <plat/pll.h> #include <plat/pll.h>
#include <plat/s5p-clock.h> #include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h> #include <plat/clock-clksrc.h>
#include <plat/exynos4.h>
#include <plat/pm.h> #include <plat/pm.h>
#include <mach/hardware.h> #include <mach/hardware.h>
@ -31,6 +30,8 @@
#include <mach/regs-clock.h> #include <mach/regs-clock.h>
#include <mach/exynos4-clock.h> #include <mach/exynos4-clock.h>
#include "common.h"
static struct sleep_save exynos4212_clock_save[] = { static struct sleep_save exynos4212_clock_save[] = {
SAVE_ITEM(S5P_CLKSRC_IMAGE), SAVE_ITEM(S5P_CLKSRC_IMAGE),
SAVE_ITEM(S5P_CLKDIV_IMAGE), SAVE_ITEM(S5P_CLKDIV_IMAGE),

3
arch/arm/mach-exynos/clock.c
View File

@ -21,7 +21,6 @@
#include <plat/pll.h> #include <plat/pll.h>
#include <plat/s5p-clock.h> #include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h> #include <plat/clock-clksrc.h>
#include <plat/exynos4.h>
#include <plat/pm.h> #include <plat/pm.h>
#include <mach/map.h> #include <mach/map.h>
@ -29,6 +28,8 @@
#include <mach/sysmmu.h> #include <mach/sysmmu.h>
#include <mach/exynos4-clock.h> #include <mach/exynos4-clock.h>
#include "common.h"
static struct sleep_save exynos4_clock_save[] = { static struct sleep_save exynos4_clock_save[] = {
SAVE_ITEM(S5P_CLKDIV_LEFTBUS), SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS), SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),

704
arch/arm/mach-exynos/common.c Normal file
View File

@ -0,0 +1,704 @@
/*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Common Codes for EXYNOS
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/sysdev.h>
#include <linux/gpio.h>
#include <linux/sched.h>
#include <linux/serial_core.h>
#include <asm/proc-fns.h>
#include <asm/exception.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/regs-irq.h>
#include <mach/regs-pmu.h>
#include <mach/regs-gpio.h>
#include <plat/cpu.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/pm.h>
#include <plat/sdhci.h>
#include <plat/gpio-cfg.h>
#include <plat/adc-core.h>
#include <plat/fb-core.h>
#include <plat/fimc-core.h>
#include <plat/iic-core.h>
#include <plat/tv-core.h>
#include <plat/regs-serial.h>
#include "common.h"
static const char name_exynos4210[] = "EXYNOS4210";
static const char name_exynos4212[] = "EXYNOS4212";
static const char name_exynos4412[] = "EXYNOS4412";
static struct cpu_table cpu_ids[] __initdata = {
{
.idcode = EXYNOS4210_CPU_ID,
.idmask = EXYNOS4_CPU_MASK,
.map_io = exynos4_map_io,
.init_clocks = exynos4_init_clocks,
.init_uarts = exynos4_init_uarts,
.init = exynos_init,
.name = name_exynos4210,
}, {
.idcode = EXYNOS4212_CPU_ID,
.idmask = EXYNOS4_CPU_MASK,
.map_io = exynos4_map_io,
.init_clocks = exynos4_init_clocks,
.init_uarts = exynos4_init_uarts,
.init = exynos_init,
.name = name_exynos4212,
}, {
.idcode = EXYNOS4412_CPU_ID,
.idmask = EXYNOS4_CPU_MASK,
.map_io = exynos4_map_io,
.init_clocks = exynos4_init_clocks,
.init_uarts = exynos4_init_uarts,
.init = exynos_init,
.name = name_exynos4412,
},
};
/* Initial IO mappings */
static struct map_desc exynos_iodesc[] __initdata = {
{
.virtual = (unsigned long)S5P_VA_CHIPID,
.pfn = __phys_to_pfn(EXYNOS4_PA_CHIPID),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_SYS,
.pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
.length = SZ_64K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_TIMER,
.pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_WATCHDOG,
.pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_SROMC,
.pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_SYSTIMER,
.pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_PMU,
.pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
.length = SZ_64K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_COMBINER_BASE,
.pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GIC_CPU,
.pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
.length = SZ_64K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GIC_DIST,
.pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
.length = SZ_64K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_UART,
.pfn = __phys_to_pfn(EXYNOS4_PA_UART),
.length = SZ_512K,
.type = MT_DEVICE,
},
};
static struct map_desc exynos4_iodesc[] __initdata = {
{
.virtual = (unsigned long)S5P_VA_CMU,
.pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
.length = SZ_128K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_COREPERI_BASE,
.pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
.length = SZ_8K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_L2CC,
.pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GPIO1,
.pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GPIO2,
.pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GPIO3,
.pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
.length = SZ_256,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_DMC0,
.pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_SROMC,
.pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_USB_HSPHY,
.pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
.length = SZ_4K,
.type = MT_DEVICE,
},
};
static struct map_desc exynos4_iodesc0[] __initdata = {
{
.virtual = (unsigned long)S5P_VA_SYSRAM,
.pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
.length = SZ_4K,
.type = MT_DEVICE,
},
};
static struct map_desc exynos4_iodesc1[] __initdata = {
{
.virtual = (unsigned long)S5P_VA_SYSRAM,
.pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
.length = SZ_4K,
.type = MT_DEVICE,
},
};
static void exynos_idle(void)
{
if (!need_resched())
cpu_do_idle();
local_irq_enable();
}
void exynos4_restart(char mode, const char *cmd)
{
__raw_writel(0x1, S5P_SWRESET);
}
/*
* exynos_map_io
*
* register the standard cpu IO areas
*/
void __init exynos_init_io(struct map_desc *mach_desc, int size)
{
/* initialize the io descriptors we need for initialization */
iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
if (mach_desc)
iotable_init(mach_desc, size);
/* detect cpu id and rev. */
s5p_init_cpu(S5P_VA_CHIPID);
s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
}
void __init exynos4_map_io(void)
{
iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
else
iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
/* initialize device information early */
exynos4_default_sdhci0();
exynos4_default_sdhci1();
exynos4_default_sdhci2();
exynos4_default_sdhci3();
s3c_adc_setname("samsung-adc-v3");
s3c_fimc_setname(0, "exynos4-fimc");
s3c_fimc_setname(1, "exynos4-fimc");
s3c_fimc_setname(2, "exynos4-fimc");
s3c_fimc_setname(3, "exynos4-fimc");
/* The I2C bus controllers are directly compatible with s3c2440 */
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
s3c_i2c2_setname("s3c2440-i2c");
s5p_fb_setname(0, "exynos4-fb");
s5p_hdmi_setname("exynos4-hdmi");
}
void __init exynos4_init_clocks(int xtal)
{
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
s3c24xx_register_baseclocks(xtal);
s5p_register_clocks(xtal);
if (soc_is_exynos4210())
exynos4210_register_clocks();
else if (soc_is_exynos4212() || soc_is_exynos4412())
exynos4212_register_clocks();
exynos4_register_clocks();
exynos4_setup_clocks();
}
#define COMBINER_ENABLE_SET 0x0
#define COMBINER_ENABLE_CLEAR 0x4
#define COMBINER_INT_STATUS 0xC
static DEFINE_SPINLOCK(irq_controller_lock);
struct combiner_chip_data {
unsigned int irq_offset;
unsigned int irq_mask;
void __iomem *base;
};
static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
static inline void __iomem *combiner_base(struct irq_data *data)
{
struct combiner_chip_data *combiner_data =
irq_data_get_irq_chip_data(data);
return combiner_data->base;
}
static void combiner_mask_irq(struct irq_data *data)
{
u32 mask = 1 << (data->irq % 32);
__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
}
static void combiner_unmask_irq(struct irq_data *data)
{
u32 mask = 1 << (data->irq % 32);
__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
}
static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
{
struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
struct irq_chip *chip = irq_get_chip(irq);
unsigned int cascade_irq, combiner_irq;
unsigned long status;
chained_irq_enter(chip, desc);
spin_lock(&irq_controller_lock);
status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
spin_unlock(&irq_controller_lock);
status &= chip_data->irq_mask;
if (status == 0)
goto out;
combiner_irq = __ffs(status);
cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
if (unlikely(cascade_irq >= NR_IRQS))
do_bad_IRQ(cascade_irq, desc);
else
generic_handle_irq(cascade_irq);
out:
chained_irq_exit(chip, desc);
}
static struct irq_chip combiner_chip = {
.name = "COMBINER",
.irq_mask = combiner_mask_irq,
.irq_unmask = combiner_unmask_irq,
};
static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
{
if (combiner_nr >= MAX_COMBINER_NR)
BUG();
if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
BUG();
irq_set_chained_handler(irq, combiner_handle_cascade_irq);
}
static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
unsigned int irq_start)
{
unsigned int i;
if (combiner_nr >= MAX_COMBINER_NR)
BUG();
combiner_data[combiner_nr].base = base;
combiner_data[combiner_nr].irq_offset = irq_start;
combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
/* Disable all interrupts */
__raw_writel(combiner_data[combiner_nr].irq_mask,
base + COMBINER_ENABLE_CLEAR);
/* Setup the Linux IRQ subsystem */
for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
+ MAX_IRQ_IN_COMBINER; i++) {
irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
irq_set_chip_data(i, &combiner_data[combiner_nr]);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
}
void __init exynos4_init_irq(void)
{
int irq;
unsigned int gic_bank_offset;
gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset);
for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
COMBINER_IRQ(irq, 0));
combiner_cascade_irq(irq, IRQ_SPI(irq));
}
/*
* The parameters of s5p_init_irq() are for VIC init.
* Theses parameters should be NULL and 0 because EXYNOS4
* uses GIC instead of VIC.
*/
s5p_init_irq(NULL, 0);
}
struct sysdev_class exynos4_sysclass = {
.name = "exynos4-core",
};
static struct sys_device exynos4_sysdev = {
.cls = &exynos4_sysclass,
};
static int __init exynos4_core_init(void)
{
return sysdev_class_register(&exynos4_sysclass);
}
core_initcall(exynos4_core_init);
#ifdef CONFIG_CACHE_L2X0
static int __init exynos4_l2x0_cache_init(void)
{
/* TAG, Data Latency Control: 2cycle */
__raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
if (soc_is_exynos4210())
__raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
else if (soc_is_exynos4212() || soc_is_exynos4412())
__raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
/* L2X0 Prefetch Control */
__raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
/* L2X0 Power Control */
__raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
S5P_VA_L2CC + L2X0_POWER_CTRL);
l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
return 0;
}
early_initcall(exynos4_l2x0_cache_init);
#endif
int __init exynos_init(void)
{
printk(KERN_INFO "EXYNOS: Initializing architecture\n");
/* set idle function */
pm_idle = exynos_idle;
return sysdev_register(&exynos4_sysdev);
}
static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = {
[0] = {
.name = "uclk1",
.divisor = 1,
.min_baud = 0,
.max_baud = 0,
},
};
/* uart registration process */
void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
struct s3c2410_uartcfg *tcfg = cfg;
u32 ucnt;
for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
if (!tcfg->clocks) {
tcfg->has_fracval = 1;
tcfg->clocks = exynos4_serial_clocks;
tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks);
}
tcfg->flags |= NO_NEED_CHECK_CLKSRC;
}
s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
}
static DEFINE_SPINLOCK(eint_lock);
static unsigned int eint0_15_data[16];
static unsigned int exynos4_get_irq_nr(unsigned int number)
{
u32 ret = 0;
switch (number) {
case 0 ... 3:
ret = (number + IRQ_EINT0);
break;
case 4 ... 7:
ret = (number + (IRQ_EINT4 - 4));
break;
case 8 ... 15:
ret = (number + (IRQ_EINT8 - 8));
break;
default:
printk(KERN_ERR "number available : %d\n", number);
}
return ret;
}
static inline void exynos4_irq_eint_mask(struct irq_data *data)
{
u32 mask;
spin_lock(&eint_lock);
mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
mask |= eint_irq_to_bit(data->irq);
__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
spin_unlock(&eint_lock);
}
static void exynos4_irq_eint_unmask(struct irq_data *data)
{
u32 mask;
spin_lock(&eint_lock);
mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
mask &= ~(eint_irq_to_bit(data->irq));
__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
spin_unlock(&eint_lock);
}
static inline void exynos4_irq_eint_ack(struct irq_data *data)
{
__raw_writel(eint_irq_to_bit(data->irq),
S5P_EINT_PEND(EINT_REG_NR(data->irq)));
}
static void exynos4_irq_eint_maskack(struct irq_data *data)
{
exynos4_irq_eint_mask(data);
exynos4_irq_eint_ack(data);
}
static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
{
int offs = EINT_OFFSET(data->irq);
int shift;
u32 ctrl, mask;
u32 newvalue = 0;
switch (type) {
case IRQ_TYPE_EDGE_RISING:
newvalue = S5P_IRQ_TYPE_EDGE_RISING;
break;
case IRQ_TYPE_EDGE_FALLING:
newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
break;
case IRQ_TYPE_EDGE_BOTH:
newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
break;
case IRQ_TYPE_LEVEL_LOW:
newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
break;
case IRQ_TYPE_LEVEL_HIGH:
newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
break;
default:
printk(KERN_ERR "No such irq type %d", type);
return -EINVAL;
}
shift = (offs & 0x7) * 4;
mask = 0x7 << shift;
spin_lock(&eint_lock);
ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
ctrl &= ~mask;
ctrl |= newvalue << shift;
__raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
spin_unlock(&eint_lock);
switch (offs) {
case 0 ... 7:
s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
break;
case 8 ... 15:
s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
break;
case 16 ... 23:
s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
break;
case 24 ... 31:
s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
break;
default:
printk(KERN_ERR "No such irq number %d", offs);
}
return 0;
}
static struct irq_chip exynos4_irq_eint = {
.name = "exynos4-eint",
.irq_mask = exynos4_irq_eint_mask,
.irq_unmask = exynos4_irq_eint_unmask,
.irq_mask_ack = exynos4_irq_eint_maskack,
.irq_ack = exynos4_irq_eint_ack,
.irq_set_type = exynos4_irq_eint_set_type,
#ifdef CONFIG_PM
.irq_set_wake = s3c_irqext_wake,
#endif
};
/*
* exynos4_irq_demux_eint
*
* This function demuxes the IRQ from from EINTs 16 to 31.
* It is designed to be inlined into the specific handler
* s5p_irq_demux_eintX_Y.
*
* Each EINT pend/mask registers handle eight of them.
*/
static inline void exynos4_irq_demux_eint(unsigned int start)
{
unsigned int irq;
u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
status &= ~mask;
status &= 0xff;
while (status) {
irq = fls(status) - 1;
generic_handle_irq(irq + start);
status &= ~(1 << irq);
}
}
static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
{
struct irq_chip *chip = irq_get_chip(irq);
chained_irq_enter(chip, desc);
exynos4_irq_demux_eint(IRQ_EINT(16));
exynos4_irq_demux_eint(IRQ_EINT(24));
chained_irq_exit(chip, desc);
}
static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
{
u32 *irq_data = irq_get_handler_data(irq);
struct irq_chip *chip = irq_get_chip(irq);
chained_irq_enter(chip, desc);
chip->irq_mask(&desc->irq_data);
if (chip->irq_ack)
chip->irq_ack(&desc->irq_data);
generic_handle_irq(*irq_data);
chip->irq_unmask(&desc->irq_data);
chained_irq_exit(chip, desc);
}
int __init exynos4_init_irq_eint(void)
{
int irq;
for (irq = 0 ; irq <= 31 ; irq++) {
irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
handle_level_irq);
set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
}
irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
for (irq = 0 ; irq <= 15 ; irq++) {
eint0_15_data[irq] = IRQ_EINT(irq);
irq_set_handler_data(exynos4_get_irq_nr(irq),
&eint0_15_data[irq]);
irq_set_chained_handler(exynos4_get_irq_nr(irq),
exynos4_irq_eint0_15);
}
return 0;
}
arch_initcall(exynos4_init_irq_eint);

41
arch/arm/mach-exynos/common.h Normal file
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@ -0,0 +1,41 @@
/*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Common Header for EXYNOS machines
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
void exynos_init_io(struct map_desc *mach_desc, int size);
void exynos4_init_irq(void);
void exynos4_register_clocks(void);
void exynos4_setup_clocks(void);
void exynos4210_register_clocks(void);
void exynos4212_register_clocks(void);
void exynos4_restart(char mode, const char *cmd);
extern struct sys_timer exynos4_timer;
#ifdef CONFIG_ARCH_EXYNOS
extern int exynos_init(void);
extern void exynos4_map_io(void);
extern void exynos4_init_clocks(int xtal);
extern void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
#else
#define exynos4_init_clocks NULL
#define exynos4_init_uarts NULL
#define exynos4_map_io NULL
#define exynos_init NULL
#endif
#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */

284
arch/arm/mach-exynos/cpu.c
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@ -1,284 +0,0 @@
/* linux/arch/arm/mach-exynos/cpu.c
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/sched.h>
#include <linux/sysdev.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/proc-fns.h>
#include <asm/exception.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
#include <plat/cpu.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/exynos4.h>
#include <plat/adc-core.h>
#include <plat/sdhci.h>
#include <plat/fb-core.h>
#include <plat/fimc-core.h>
#include <plat/iic-core.h>
#include <plat/reset.h>
#include <plat/tv-core.h>
#include <mach/regs-irq.h>
#include <mach/regs-pmu.h>
extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
unsigned int irq_start);
extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
/* Initial IO mappings */
static struct map_desc exynos_iodesc[] __initdata = {
{
.virtual = (unsigned long)S5P_VA_SYSTIMER,
.pfn = __phys_to_pfn(EXYNOS_PA_SYSTIMER),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_PMU,
.pfn = __phys_to_pfn(EXYNOS_PA_PMU),
.length = SZ_64K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_COMBINER_BASE,
.pfn = __phys_to_pfn(EXYNOS_PA_COMBINER),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GIC_CPU,
.pfn = __phys_to_pfn(EXYNOS_PA_GIC_CPU),
.length = SZ_64K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GIC_DIST,
.pfn = __phys_to_pfn(EXYNOS_PA_GIC_DIST),
.length = SZ_64K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_UART,
.pfn = __phys_to_pfn(S3C_PA_UART),
.length = SZ_512K,
.type = MT_DEVICE,
},
};
static struct map_desc exynos4_iodesc[] __initdata = {
{
.virtual = (unsigned long)S5P_VA_CMU,
.pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
.length = SZ_128K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_COREPERI_BASE,
.pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
.length = SZ_8K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_L2CC,
.pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GPIO1,
.pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GPIO2,
.pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GPIO3,
.pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
.length = SZ_256,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_DMC0,
.pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_SROMC,
.pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_USB_HSPHY,
.pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
.length = SZ_4K,
.type = MT_DEVICE,
},
};
static struct map_desc exynos4_iodesc0[] __initdata = {
{
.virtual = (unsigned long)S5P_VA_SYSRAM,
.pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
.length = SZ_4K,
.type = MT_DEVICE,
},
};
static struct map_desc exynos4_iodesc1[] __initdata = {
{
.virtual = (unsigned long)S5P_VA_SYSRAM,
.pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
.length = SZ_4K,
.type = MT_DEVICE,
},
};
static void exynos_idle(void)
{
if (!need_resched())
cpu_do_idle();
local_irq_enable();
}
static void exynos4_sw_reset(void)
{
__raw_writel(0x1, S5P_SWRESET);
}
/*
* exynos_map_io
*
* register the standard cpu IO areas
*/
void __init exynos4_map_io(void)
{
iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
else
iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
/* initialize device information early */
exynos4_default_sdhci0();
exynos4_default_sdhci1();
exynos4_default_sdhci2();
exynos4_default_sdhci3();
s3c_adc_setname("samsung-adc-v3");
s3c_fimc_setname(0, "exynos4-fimc");
s3c_fimc_setname(1, "exynos4-fimc");
s3c_fimc_setname(2, "exynos4-fimc");
s3c_fimc_setname(3, "exynos4-fimc");
/* The I2C bus controllers are directly compatible with s3c2440 */
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
s3c_i2c2_setname("s3c2440-i2c");
s5p_fb_setname(0, "exynos4-fb");
s5p_hdmi_setname("exynos4-hdmi");
}
void __init exynos4_init_clocks(int xtal)
{
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
s3c24xx_register_baseclocks(xtal);
s5p_register_clocks(xtal);
if (soc_is_exynos4210())
exynos4210_register_clocks();
else if (soc_is_exynos4212() || soc_is_exynos4412())
exynos4212_register_clocks();
exynos4_register_clocks();
exynos4_setup_clocks();
}
void __init exynos4_init_irq(void)
{
int irq;
unsigned int gic_bank_offset;
gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset);
for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
COMBINER_IRQ(irq, 0));
combiner_cascade_irq(irq, IRQ_SPI(irq));
}
/* The parameters of s5p_init_irq() are for VIC init.
* Theses parameters should be NULL and 0 because EXYNOS4
* uses GIC instead of VIC.
*/
s5p_init_irq(NULL, 0);
}
struct sysdev_class exynos4_sysclass = {
.name = "exynos4-core",
};
static struct sys_device exynos4_sysdev = {
.cls = &exynos4_sysclass,
};
static int __init exynos4_core_init(void)
{
return sysdev_class_register(&exynos4_sysclass);
}
core_initcall(exynos4_core_init);
#ifdef CONFIG_CACHE_L2X0
static int __init exynos4_l2x0_cache_init(void)
{
/* TAG, Data Latency Control: 2cycle */
__raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
if (soc_is_exynos4210())
__raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
else if (soc_is_exynos4212() || soc_is_exynos4412())
__raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
/* L2X0 Prefetch Control */
__raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
/* L2X0 Power Control */
__raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
S5P_VA_L2CC + L2X0_POWER_CTRL);
l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
return 0;
}
early_initcall(exynos4_l2x0_cache_init);
#endif
int __init exynos_init(void)
{
printk(KERN_INFO "EXYNOS: Initializing architecture\n");
/* set idle function */
pm_idle = exynos_idle;
/* set sw_reset function */
if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
s5p_reset_hook = exynos4_sw_reset;
return sysdev_register(&exynos4_sysdev);
}

12
arch/arm/mach-exynos/include/mach/map.h
View File

@ -149,7 +149,6 @@
#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG #define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
#define S3C_PA_UART EXYNOS4_PA_UART #define S3C_PA_UART EXYNOS4_PA_UART
#define S5P_PA_CHIPID EXYNOS4_PA_CHIPID
#define S5P_PA_EHCI EXYNOS4_PA_EHCI #define S5P_PA_EHCI EXYNOS4_PA_EHCI
#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0 #define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0
#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1 #define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1
@ -166,26 +165,17 @@
#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA #define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
#define S5P_PA_SDO EXYNOS4_PA_SDO #define S5P_PA_SDO EXYNOS4_PA_SDO
#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM #define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
#define S5P_PA_SROMC EXYNOS4_PA_SROMC
#define S5P_PA_SYSCON EXYNOS4_PA_SYSCON
#define S5P_PA_TIMER EXYNOS4_PA_TIMER
#define S5P_PA_VP EXYNOS4_PA_VP #define S5P_PA_VP EXYNOS4_PA_VP
#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC #define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1 #define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1
#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD #define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD
#define EXYNOS_PA_COMBINER EXYNOS4_PA_COMBINER
#define EXYNOS_PA_GIC_CPU EXYNOS4_PA_GIC_CPU
#define EXYNOS_PA_GIC_DIST EXYNOS4_PA_GIC_DIST
#define EXYNOS_PA_PMU EXYNOS4_PA_PMU
#define EXYNOS_PA_SYSTIMER EXYNOS4_PA_SYSTIMER
/* Compatibility UART */ /* Compatibility UART */
#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) #define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET)) #define S5P_PA_UART(x) (EXYNOS4_PA_UART + ((x) * S3C_UART_OFFSET))
#define S5P_PA_UART0 S5P_PA_UART(0) #define S5P_PA_UART0 S5P_PA_UART(0)
#define S5P_PA_UART1 S5P_PA_UART(1) #define S5P_PA_UART1 S5P_PA_UART(1)
#define S5P_PA_UART2 S5P_PA_UART(2) #define S5P_PA_UART2 S5P_PA_UART(2)

2
arch/arm/mach-exynos/include/mach/system.h
View File

@ -13,8 +13,6 @@
#ifndef __ASM_ARCH_SYSTEM_H #ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H __FILE__ #define __ASM_ARCH_SYSTEM_H __FILE__
#include <plat/system-reset.h>
static void arch_idle(void) static void arch_idle(void)
{ {
/* nothing here yet */ /* nothing here yet */

42
arch/arm/mach-exynos/init.c
View File

@ -1,42 +0,0 @@
/* linux/arch/arm/mach-exynos4/init.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/serial_core.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/regs-serial.h>
static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = {
[0] = {
.name = "uclk1",
.divisor = 1,
.min_baud = 0,
.max_baud = 0,
},
};
/* uart registration process */
void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
struct s3c2410_uartcfg *tcfg = cfg;
u32 ucnt;
for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
if (!tcfg->clocks) {
tcfg->has_fracval = 1;
tcfg->clocks = exynos4_serial_clocks;
tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks);
}
tcfg->flags |= NO_NEED_CHECK_CLKSRC;
}
s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
}

124
arch/arm/mach-exynos/irq-combiner.c
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@ -1,124 +0,0 @@
/* linux/arch/arm/mach-exynos4/irq-combiner.c
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Based on arch/arm/common/gic.c
*
* IRQ COMBINER support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/io.h>
#include <asm/mach/irq.h>
#define COMBINER_ENABLE_SET 0x0
#define COMBINER_ENABLE_CLEAR 0x4
#define COMBINER_INT_STATUS 0xC
static DEFINE_SPINLOCK(irq_controller_lock);
struct combiner_chip_data {
unsigned int irq_offset;
unsigned int irq_mask;
void __iomem *base;
};
static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
static inline void __iomem *combiner_base(struct irq_data *data)
{
struct combiner_chip_data *combiner_data =
irq_data_get_irq_chip_data(data);
return combiner_data->base;
}
static void combiner_mask_irq(struct irq_data *data)
{
u32 mask = 1 << (data->irq % 32);
__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
}
static void combiner_unmask_irq(struct irq_data *data)
{
u32 mask = 1 << (data->irq % 32);
__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
}
static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
{
struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
struct irq_chip *chip = irq_get_chip(irq);
unsigned int cascade_irq, combiner_irq;
unsigned long status;
chained_irq_enter(chip, desc);
spin_lock(&irq_controller_lock);
status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
spin_unlock(&irq_controller_lock);
status &= chip_data->irq_mask;
if (status == 0)
goto out;
combiner_irq = __ffs(status);
cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
if (unlikely(cascade_irq >= NR_IRQS))
do_bad_IRQ(cascade_irq, desc);
else
generic_handle_irq(cascade_irq);
out:
chained_irq_exit(chip, desc);
}
static struct irq_chip combiner_chip = {
.name = "COMBINER",
.irq_mask = combiner_mask_irq,
.irq_unmask = combiner_unmask_irq,
};
void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
{
if (combiner_nr >= MAX_COMBINER_NR)
BUG();
if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
BUG();
irq_set_chained_handler(irq, combiner_handle_cascade_irq);
}
void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
unsigned int irq_start)
{
unsigned int i;
if (combiner_nr >= MAX_COMBINER_NR)
BUG();
combiner_data[combiner_nr].base = base;
combiner_data[combiner_nr].irq_offset = irq_start;
combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
/* Disable all interrupts */
__raw_writel(combiner_data[combiner_nr].irq_mask,
base + COMBINER_ENABLE_CLEAR);
/* Setup the Linux IRQ subsystem */
for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
+ MAX_IRQ_IN_COMBINER; i++) {
irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
irq_set_chip_data(i, &combiner_data[combiner_nr]);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
}

237
arch/arm/mach-exynos/irq-eint.c
View File

@ -1,237 +0,0 @@
/* linux/arch/arm/mach-exynos4/irq-eint.c
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4 - IRQ EINT support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/sysdev.h>
#include <linux/gpio.h>
#include <plat/pm.h>
#include <plat/cpu.h>
#include <plat/gpio-cfg.h>
#include <mach/regs-gpio.h>
#include <asm/mach/irq.h>
static DEFINE_SPINLOCK(eint_lock);
static unsigned int eint0_15_data[16];
static unsigned int exynos4_get_irq_nr(unsigned int number)
{
u32 ret = 0;
switch (number) {
case 0 ... 3:
ret = (number + IRQ_EINT0);
break;
case 4 ... 7:
ret = (number + (IRQ_EINT4 - 4));
break;
case 8 ... 15:
ret = (number + (IRQ_EINT8 - 8));
break;
default:
printk(KERN_ERR "number available : %d\n", number);
}
return ret;
}
static inline void exynos4_irq_eint_mask(struct irq_data *data)
{
u32 mask;
spin_lock(&eint_lock);
mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
mask |= eint_irq_to_bit(data->irq);
__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
spin_unlock(&eint_lock);
}
static void exynos4_irq_eint_unmask(struct irq_data *data)
{
u32 mask;
spin_lock(&eint_lock);
mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
mask &= ~(eint_irq_to_bit(data->irq));
__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
spin_unlock(&eint_lock);
}
static inline void exynos4_irq_eint_ack(struct irq_data *data)
{
__raw_writel(eint_irq_to_bit(data->irq),
S5P_EINT_PEND(EINT_REG_NR(data->irq)));
}
static void exynos4_irq_eint_maskack(struct irq_data *data)
{
exynos4_irq_eint_mask(data);
exynos4_irq_eint_ack(data);
}
static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
{
int offs = EINT_OFFSET(data->irq);
int shift;
u32 ctrl, mask;
u32 newvalue = 0;
switch (type) {
case IRQ_TYPE_EDGE_RISING:
newvalue = S5P_IRQ_TYPE_EDGE_RISING;
break;
case IRQ_TYPE_EDGE_FALLING:
newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
break;
case IRQ_TYPE_EDGE_BOTH:
newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
break;
case IRQ_TYPE_LEVEL_LOW:
newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
break;
case IRQ_TYPE_LEVEL_HIGH:
newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
break;
default:
printk(KERN_ERR "No such irq type %d", type);
return -EINVAL;
}
shift = (offs & 0x7) * 4;
mask = 0x7 << shift;
spin_lock(&eint_lock);
ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
ctrl &= ~mask;
ctrl |= newvalue << shift;
__raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
spin_unlock(&eint_lock);
switch (offs) {
case 0 ... 7:
s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
break;
case 8 ... 15:
s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
break;
case 16 ... 23:
s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
break;
case 24 ... 31:
s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
break;
default:
printk(KERN_ERR "No such irq number %d", offs);
}
return 0;
}
static struct irq_chip exynos4_irq_eint = {
.name = "exynos4-eint",
.irq_mask = exynos4_irq_eint_mask,
.irq_unmask = exynos4_irq_eint_unmask,
.irq_mask_ack = exynos4_irq_eint_maskack,
.irq_ack = exynos4_irq_eint_ack,
.irq_set_type = exynos4_irq_eint_set_type,
#ifdef CONFIG_PM
.irq_set_wake = s3c_irqext_wake,
#endif
};
/* exynos4_irq_demux_eint
*
* This function demuxes the IRQ from from EINTs 16 to 31.
* It is designed to be inlined into the specific handler
* s5p_irq_demux_eintX_Y.
*
* Each EINT pend/mask registers handle eight of them.
*/
static inline void exynos4_irq_demux_eint(unsigned int start)
{
unsigned int irq;
u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
status &= ~mask;
status &= 0xff;
while (status) {
irq = fls(status) - 1;
generic_handle_irq(irq + start);
status &= ~(1 << irq);
}
}
static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
{
struct irq_chip *chip = irq_get_chip(irq);
chained_irq_enter(chip, desc);
exynos4_irq_demux_eint(IRQ_EINT(16));
exynos4_irq_demux_eint(IRQ_EINT(24));
chained_irq_exit(chip, desc);
}
static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
{
u32 *irq_data = irq_get_handler_data(irq);
struct irq_chip *chip = irq_get_chip(irq);
chained_irq_enter(chip, desc);
chip->irq_mask(&desc->irq_data);
if (chip->irq_ack)
chip->irq_ack(&desc->irq_data);
generic_handle_irq(*irq_data);
chip->irq_unmask(&desc->irq_data);
chained_irq_exit(chip, desc);
}
int __init exynos4_init_irq_eint(void)
{
int irq;
for (irq = 0 ; irq <= 31 ; irq++) {
irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
handle_level_irq);
set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
}
irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
for (irq = 0 ; irq <= 15 ; irq++) {
eint0_15_data[irq] = IRQ_EINT(irq);
irq_set_handler_data(exynos4_get_irq_nr(irq),
&eint0_15_data[irq]);
irq_set_chained_handler(exynos4_get_irq_nr(irq),
exynos4_irq_eint0_15);
}
return 0;
}
arch_initcall(exynos4_init_irq_eint);

6
arch/arm/mach-exynos/mach-armlex4210.c
View File

@ -21,7 +21,6 @@
#include <plat/cpu.h> #include <plat/cpu.h>
#include <plat/devs.h> #include <plat/devs.h>
#include <plat/exynos4.h>
#include <plat/gpio-cfg.h> #include <plat/gpio-cfg.h>
#include <plat/regs-serial.h> #include <plat/regs-serial.h>
#include <plat/regs-srom.h> #include <plat/regs-srom.h>
@ -29,6 +28,8 @@
#include <mach/map.h> #include <mach/map.h>
#include "common.h"
/* Following are default values for UCON, ULCON and UFCON UART registers */ /* Following are default values for UCON, ULCON and UFCON UART registers */
#define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ #define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \ S3C2410_UCON_RXILEVEL | \
@ -188,7 +189,7 @@ static void __init armlex4210_smsc911x_init(void)
static void __init armlex4210_map_io(void) static void __init armlex4210_map_io(void)
{ {
s5p_init_io(NULL, 0, S5P_VA_CHIPID); exynos_init_io(NULL, 0);
s3c24xx_init_clocks(24000000); s3c24xx_init_clocks(24000000);
s3c24xx_init_uarts(armlex4210_uartcfgs, s3c24xx_init_uarts(armlex4210_uartcfgs,
ARRAY_SIZE(armlex4210_uartcfgs)); ARRAY_SIZE(armlex4210_uartcfgs));
@ -214,4 +215,5 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
.handle_irq = gic_handle_irq, .handle_irq = gic_handle_irq,
.init_machine = armlex4210_machine_init, .init_machine = armlex4210_machine_init,
.timer = &exynos4_timer, .timer = &exynos4_timer,
.restart = exynos4_restart,
MACHINE_END MACHINE_END

6
arch/arm/mach-exynos/mach-nuri.c
View File

@ -38,7 +38,6 @@
#include <plat/adc.h> #include <plat/adc.h>
#include <plat/regs-fb-v4.h> #include <plat/regs-fb-v4.h>
#include <plat/regs-serial.h> #include <plat/regs-serial.h>
#include <plat/exynos4.h>
#include <plat/cpu.h> #include <plat/cpu.h>
#include <plat/devs.h> #include <plat/devs.h>
#include <plat/fb.h> #include <plat/fb.h>
@ -55,6 +54,8 @@
#include <mach/map.h> #include <mach/map.h>
#include "common.h"
/* Following are default values for UCON, ULCON and UFCON UART registers */ /* Following are default values for UCON, ULCON and UFCON UART registers */
#define NURI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ #define NURI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \ S3C2410_UCON_RXILEVEL | \
@ -1284,7 +1285,7 @@ static struct platform_device *nuri_devices[] __initdata = {
static void __init nuri_map_io(void) static void __init nuri_map_io(void)
{ {
s5p_init_io(NULL, 0, S5P_VA_CHIPID); exynos_init_io(NULL, 0);
s3c24xx_init_clocks(24000000); s3c24xx_init_clocks(24000000);
s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs)); s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
} }
@ -1338,4 +1339,5 @@ MACHINE_START(NURI, "NURI")
.init_machine = nuri_machine_init, .init_machine = nuri_machine_init,
.timer = &exynos4_timer, .timer = &exynos4_timer,
.reserve = &nuri_reserve, .reserve = &nuri_reserve,
.restart = exynos4_restart,
MACHINE_END MACHINE_END

6
arch/arm/mach-exynos/mach-origen.c
View File

@ -29,7 +29,6 @@
#include <plat/regs-serial.h> #include <plat/regs-serial.h>
#include <plat/regs-fb-v4.h> #include <plat/regs-fb-v4.h>
#include <plat/exynos4.h>
#include <plat/cpu.h> #include <plat/cpu.h>
#include <plat/devs.h> #include <plat/devs.h>
#include <plat/sdhci.h> #include <plat/sdhci.h>
@ -44,6 +43,8 @@
#include <mach/map.h> #include <mach/map.h>
#include "common.h"
/* Following are default values for UCON, ULCON and UFCON UART registers */ /* Following are default values for UCON, ULCON and UFCON UART registers */
#define ORIGEN_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ #define ORIGEN_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \ S3C2410_UCON_RXILEVEL | \
@ -639,7 +640,7 @@ static void s5p_tv_setup(void)
static void __init origen_map_io(void) static void __init origen_map_io(void)
{ {
s5p_init_io(NULL, 0, S5P_VA_CHIPID); exynos_init_io(NULL, 0);
s3c24xx_init_clocks(24000000); s3c24xx_init_clocks(24000000);
s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs)); s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
} }
@ -699,4 +700,5 @@ MACHINE_START(ORIGEN, "ORIGEN")
.init_machine = origen_machine_init, .init_machine = origen_machine_init,
.timer = &exynos4_timer, .timer = &exynos4_timer,
.reserve = &origen_reserve, .reserve = &origen_reserve,
.restart = exynos4_restart,
MACHINE_END MACHINE_END

7
arch/arm/mach-exynos/mach-smdk4x12.c
View File

@ -28,7 +28,6 @@
#include <plat/clock.h> #include <plat/clock.h>
#include <plat/cpu.h> #include <plat/cpu.h>
#include <plat/devs.h> #include <plat/devs.h>
#include <plat/exynos4.h>
#include <plat/gpio-cfg.h> #include <plat/gpio-cfg.h>
#include <plat/iic.h> #include <plat/iic.h>
#include <plat/keypad.h> #include <plat/keypad.h>
@ -37,6 +36,8 @@
#include <mach/map.h> #include <mach/map.h>
#include "common.h"
/* Following are default values for UCON, ULCON and UFCON UART registers */ /* Following are default values for UCON, ULCON and UFCON UART registers */
#define SMDK4X12_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ #define SMDK4X12_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \ S3C2410_UCON_RXILEVEL | \
@ -250,7 +251,7 @@ static void __init smdk4x12_map_io(void)
{ {
clk_xusbxti.rate = 24000000; clk_xusbxti.rate = 24000000;
s5p_init_io(NULL, 0, S5P_VA_CHIPID); exynos_init_io(NULL, 0);
s3c24xx_init_clocks(clk_xusbxti.rate); s3c24xx_init_clocks(clk_xusbxti.rate);
s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs)); s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
} }
@ -291,6 +292,7 @@ MACHINE_START(SMDK4212, "SMDK4212")
.handle_irq = gic_handle_irq, .handle_irq = gic_handle_irq,
.init_machine = smdk4x12_machine_init, .init_machine = smdk4x12_machine_init,
.timer = &exynos4_timer, .timer = &exynos4_timer,
.restart = exynos4_restart,
MACHINE_END MACHINE_END
MACHINE_START(SMDK4412, "SMDK4412") MACHINE_START(SMDK4412, "SMDK4412")
@ -302,4 +304,5 @@ MACHINE_START(SMDK4412, "SMDK4412")
.handle_irq = gic_handle_irq, .handle_irq = gic_handle_irq,
.init_machine = smdk4x12_machine_init, .init_machine = smdk4x12_machine_init,
.timer = &exynos4_timer, .timer = &exynos4_timer,
.restart = exynos4_restart,
MACHINE_END MACHINE_END

7
arch/arm/mach-exynos/mach-smdkv310.c
View File

@ -28,7 +28,6 @@
#include <plat/regs-serial.h> #include <plat/regs-serial.h>
#include <plat/regs-srom.h> #include <plat/regs-srom.h>
#include <plat/regs-fb-v4.h> #include <plat/regs-fb-v4.h>
#include <plat/exynos4.h>
#include <plat/cpu.h> #include <plat/cpu.h>
#include <plat/devs.h> #include <plat/devs.h>
#include <plat/fb.h> #include <plat/fb.h>
@ -44,6 +43,8 @@
#include <mach/map.h> #include <mach/map.h>
#include "common.h"
/* Following are default values for UCON, ULCON and UFCON UART registers */ /* Following are default values for UCON, ULCON and UFCON UART registers */
#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ #define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \ S3C2410_UCON_RXILEVEL | \
@ -333,7 +334,7 @@ static void s5p_tv_setup(void)
static void __init smdkv310_map_io(void) static void __init smdkv310_map_io(void)
{ {
s5p_init_io(NULL, 0, S5P_VA_CHIPID); exynos_init_io(NULL, 0);
s3c24xx_init_clocks(24000000); s3c24xx_init_clocks(24000000);
s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs)); s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
} }
@ -380,6 +381,7 @@ MACHINE_START(SMDKV310, "SMDKV310")
.init_machine = smdkv310_machine_init, .init_machine = smdkv310_machine_init,
.timer = &exynos4_timer, .timer = &exynos4_timer,
.reserve = &smdkv310_reserve, .reserve = &smdkv310_reserve,
.restart = exynos4_restart,
MACHINE_END MACHINE_END
MACHINE_START(SMDKC210, "SMDKC210") MACHINE_START(SMDKC210, "SMDKC210")
@ -390,4 +392,5 @@ MACHINE_START(SMDKC210, "SMDKC210")
.handle_irq = gic_handle_irq, .handle_irq = gic_handle_irq,
.init_machine = smdkv310_machine_init, .init_machine = smdkv310_machine_init,
.timer = &exynos4_timer, .timer = &exynos4_timer,
.restart = exynos4_restart,
MACHINE_END MACHINE_END

6
arch/arm/mach-exynos/mach-universal_c210.c
View File

@ -28,7 +28,6 @@
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <plat/regs-serial.h> #include <plat/regs-serial.h>
#include <plat/exynos4.h>
#include <plat/cpu.h> #include <plat/cpu.h>
#include <plat/devs.h> #include <plat/devs.h>
#include <plat/iic.h> #include <plat/iic.h>
@ -48,6 +47,8 @@
#include <media/s5p_fimc.h> #include <media/s5p_fimc.h>
#include <media/m5mols.h> #include <media/m5mols.h>
#include "common.h"
/* Following are default values for UCON, ULCON and UFCON UART registers */ /* Following are default values for UCON, ULCON and UFCON UART registers */
#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ #define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \ S3C2410_UCON_RXILEVEL | \
@ -993,7 +994,7 @@ static struct platform_device *universal_devices[] __initdata = {
static void __init universal_map_io(void) static void __init universal_map_io(void)
{ {
s5p_init_io(NULL, 0, S5P_VA_CHIPID); exynos_init_io(NULL, 0);
s3c24xx_init_clocks(24000000); s3c24xx_init_clocks(24000000);
s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
} }
@ -1063,4 +1064,5 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
.init_machine = universal_machine_init, .init_machine = universal_machine_init,
.timer = &exynos4_timer, .timer = &exynos4_timer,
.reserve = &universal_reserve, .reserve = &universal_reserve,
.restart = exynos4_restart,
MACHINE_END MACHINE_END

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