net: phy: marvell10g: add downshift tunable support
Add support for the downshift tunable for the Marvell 88x3310 PHY. Downshift is only usable with firmware 0.3.5.0 and later. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Russell King
David S. Miller
parent
75f81afb27
commit
4075a6a047
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@ -22,6 +22,7 @@
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* If both the fiber and copper ports are connected, the first to gain
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* link takes priority and the other port is completely locked out.
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*/
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#include <linux/bitfield.h>
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#include <linux/ctype.h>
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#include <linux/delay.h>
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#include <linux/hwmon.h>
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@ -33,6 +34,8 @@
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#define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe
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#define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa)
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#define MV_VERSION(a,b,c,d) ((a) << 24 | (b) << 16 | (c) << 8 | (d))
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enum {
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MV_PMA_FW_VER0 = 0xc011,
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MV_PMA_FW_VER1 = 0xc012,
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@ -62,6 +65,15 @@ enum {
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MV_PCS_CSCR1_MDIX_MDIX = 0x0020,
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MV_PCS_CSCR1_MDIX_AUTO = 0x0060,
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MV_PCS_DSC1 = 0x8003,
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MV_PCS_DSC1_ENABLE = BIT(9),
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MV_PCS_DSC1_10GBT = 0x01c0,
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MV_PCS_DSC1_1GBR = 0x0038,
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MV_PCS_DSC1_100BTX = 0x0007,
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MV_PCS_DSC2 = 0x8004,
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MV_PCS_DSC2_2P5G = 0xf000,
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MV_PCS_DSC2_5G = 0x0f00,
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MV_PCS_CSSR1 = 0x8008,
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MV_PCS_CSSR1_SPD1_MASK = 0xc000,
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MV_PCS_CSSR1_SPD1_SPD2 = 0xc000,
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@ -125,6 +137,7 @@ enum {
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};
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struct mv3310_chip {
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bool (*has_downshift)(struct phy_device *phydev);
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void (*init_supported_interfaces)(unsigned long *mask);
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int (*get_mactype)(struct phy_device *phydev);
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int (*init_interface)(struct phy_device *phydev, int mactype);
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@ -138,6 +151,7 @@ struct mv3310_priv {
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DECLARE_BITMAP(supported_interfaces, PHY_INTERFACE_MODE_MAX);
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u32 firmware_ver;
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bool has_downshift;
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bool rate_match;
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phy_interface_t const_interface;
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@ -330,6 +344,71 @@ static int mv3310_reset(struct phy_device *phydev, u32 unit)
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5000, 100000, true);
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}
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static int mv3310_get_downshift(struct phy_device *phydev, u8 *ds)
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{
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struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
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int val;
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if (!priv->has_downshift)
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return -EOPNOTSUPP;
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val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1);
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if (val < 0)
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return val;
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if (val & MV_PCS_DSC1_ENABLE)
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/* assume that all fields are the same */
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*ds = 1 + FIELD_GET(MV_PCS_DSC1_10GBT, (u16)val);
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else
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*ds = DOWNSHIFT_DEV_DISABLE;
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return 0;
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}
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static int mv3310_set_downshift(struct phy_device *phydev, u8 ds)
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{
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struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
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u16 val;
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int err;
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if (!priv->has_downshift)
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return -EOPNOTSUPP;
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if (ds == DOWNSHIFT_DEV_DISABLE)
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return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1,
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MV_PCS_DSC1_ENABLE);
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/* DOWNSHIFT_DEV_DEFAULT_COUNT is confusing. It looks like it should
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* set the default settings for the PHY. However, it is used for
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* "ethtool --set-phy-tunable ethN downshift on". The intention is
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* to enable downshift at a default number of retries. The default
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* settings for 88x3310 are for two retries with downshift disabled.
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* So let's use two retries with downshift enabled.
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*/
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if (ds == DOWNSHIFT_DEV_DEFAULT_COUNT)
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ds = 2;
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if (ds > 8)
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return -E2BIG;
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ds -= 1;
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val = FIELD_PREP(MV_PCS_DSC2_2P5G, ds);
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val |= FIELD_PREP(MV_PCS_DSC2_5G, ds);
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err = phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC2,
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MV_PCS_DSC2_2P5G | MV_PCS_DSC2_5G, val);
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if (err < 0)
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return err;
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val = MV_PCS_DSC1_ENABLE;
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val |= FIELD_PREP(MV_PCS_DSC1_10GBT, ds);
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val |= FIELD_PREP(MV_PCS_DSC1_1GBR, ds);
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val |= FIELD_PREP(MV_PCS_DSC1_100BTX, ds);
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return phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1,
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MV_PCS_DSC1_ENABLE | MV_PCS_DSC1_10GBT |
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MV_PCS_DSC1_1GBR | MV_PCS_DSC1_100BTX, val);
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}
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static int mv3310_get_edpd(struct phy_device *phydev, u16 *edpd)
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{
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int val;
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@ -448,6 +527,9 @@ static int mv3310_probe(struct phy_device *phydev)
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priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255,
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(priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255);
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if (chip->has_downshift)
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priv->has_downshift = chip->has_downshift(phydev);
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/* Powering down the port when not in use saves about 600mW */
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ret = mv3310_power_down(phydev);
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if (ret)
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@ -616,7 +698,16 @@ static int mv3310_config_init(struct phy_device *phydev)
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}
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/* Enable EDPD mode - saving 600mW */
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return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
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err = mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
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if (err)
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return err;
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/* Allow downshift */
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err = mv3310_set_downshift(phydev, DOWNSHIFT_DEV_DEFAULT_COUNT);
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if (err && err != -EOPNOTSUPP)
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return err;
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return 0;
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}
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static int mv3310_get_features(struct phy_device *phydev)
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@ -886,6 +977,8 @@ static int mv3310_get_tunable(struct phy_device *phydev,
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struct ethtool_tunable *tuna, void *data)
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{
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switch (tuna->id) {
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case ETHTOOL_PHY_DOWNSHIFT:
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return mv3310_get_downshift(phydev, data);
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case ETHTOOL_PHY_EDPD:
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return mv3310_get_edpd(phydev, data);
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default:
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@ -897,6 +990,8 @@ static int mv3310_set_tunable(struct phy_device *phydev,
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struct ethtool_tunable *tuna, const void *data)
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{
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switch (tuna->id) {
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case ETHTOOL_PHY_DOWNSHIFT:
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return mv3310_set_downshift(phydev, *(u8 *)data);
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case ETHTOOL_PHY_EDPD:
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return mv3310_set_edpd(phydev, *(u16 *)data);
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default:
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@ -904,6 +999,14 @@ static int mv3310_set_tunable(struct phy_device *phydev,
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}
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}
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static bool mv3310_has_downshift(struct phy_device *phydev)
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{
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struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
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/* Fails to downshift with firmware older than v0.3.5.0 */
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return priv->firmware_ver >= MV_VERSION(0,3,5,0);
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}
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static void mv3310_init_supported_interfaces(unsigned long *mask)
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{
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__set_bit(PHY_INTERFACE_MODE_SGMII, mask);
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@ -943,6 +1046,7 @@ static void mv2111_init_supported_interfaces(unsigned long *mask)
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}
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static const struct mv3310_chip mv3310_type = {
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.has_downshift = mv3310_has_downshift,
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.init_supported_interfaces = mv3310_init_supported_interfaces,
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.get_mactype = mv3310_get_mactype,
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.init_interface = mv3310_init_interface,
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@ -953,6 +1057,7 @@ static const struct mv3310_chip mv3310_type = {
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};
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static const struct mv3310_chip mv3340_type = {
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.has_downshift = mv3310_has_downshift,
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.init_supported_interfaces = mv3340_init_supported_interfaces,
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.get_mactype = mv3310_get_mactype,
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.init_interface = mv3340_init_interface,
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