clk: renesas: Updates for v4.18
- Add support for the MSIOF module clocks on R-Car M3-N, - Add support for the new RZ/G1C and R-Car E3 SoCs, - Small fixes and cleanups. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJa8yWkAAoJEEgEtLw/Ve77WtAQALNv1nbyp/tlh6+riqHlwN4J Mr98agjpY1vdrqHfWwdG20LySnnGHKehIC3YOfhWWQDzAgwtRkS+PhwJ9Hi8Q8Rt 0Fxi3Xo3TCxeqBzHXuWYe2NG/YB137bu+XL9vCGvQl7/8fUrM3HRpAnjwrH74LWw DjkgvcwvkZvVr5KpUuE7oybEcj5r9liZGjQda1xIoWmBlHM0SDfwm0O7XUFkoUuT G/A6epgIWoAetXbNY5JK/6Frl7TBtD3NlRg0kFL35qr7sqSZSvAToipCXRWM6yOj IfPWWhZMtJBqvM1qaXlxcpoQXoHlVK8dJdseaLoclZ5QyQQMaEYTr8CMpKKngTNT 2yHeO09RGvm9G0jFI6wDdQ5jMh3mMqHuPJeIG3kh0FfgYbZpCW6T//P2mnylPpqQ i6CBDxVnycD/FkWPd9TLdsnbc2smT9FQ5Cdsr+6Rce/nEUhcj3cdfyb8NVsFN3Ux iWuiOgr5OKPLD2wQTUGePCZam5ZdFnAikXPfvvS1K6cSF60YqYpn78f1PnGczhs9 uGZ1g7TRVw670JMjkWHEFszFa7bnfSzGZJElI1R/XLTdmOqtwAFbiWMJiGvxVAay r6TSdgQqJ69g2apRy0WEaOWj/d/FtbL7fcQYBDdGf5CWV/3YY79JvFA/8s476USJ Zv5OcrG3fcUNiveZZe1F =ednb -----END PGP SIGNATURE----- Merge tag 'clk-renesas-for-v4.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull renesas clk driver updates from Geert Uytterhoeven: - Add support for the MSIOF module clocks on R-Car M3-N - Add support for the new RZ/G1C and R-Car E3 SoCs * tag 'clk-renesas-for-v4.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: cpg-mssr: Add support for R-Car E3 clk: renesas: Add r8a77990 CPG Core Clock Definitions clk: renesas: rcar-gen2: Centralize quirks handling clk: renesas: r8a77980: Correct parent clock of PCIEC0 clk: renesas: r8a7794: Fix LB clock divider clk: renesas: r8a7792: Fix LB clock divider clk: renesas: r8a7791/r8a7793: Fix LB clock divider clk: renesas: r8a7745: Fix LB clock divider clk: renesas: r8a7743: Fix LB clock divider clk: renesas: cpg-mssr: Add r8a77470 support clk: renesas: Add r8a77470 CPG Core Clock Definitions clk: renesas: r8a77965: Add MSIOF controller clocks
This commit is contained in:
Stephen Boyd
commit
402b004207
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@ -15,6 +15,7 @@ Required Properties:
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- compatible: Must be one of:
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- "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
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- "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
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- "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)
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- "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
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- "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
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- "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
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@ -25,6 +26,7 @@ Required Properties:
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- "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
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- "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
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- "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
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- "renesas,r8a77990-cpg-mssr" for the r8a77990 SoC (R-Car E3)
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- "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
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- reg: Base address and length of the memory resource used by the CPG/MSSR
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@ -33,10 +35,12 @@ Required Properties:
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- clocks: References to external parent clocks, one entry for each entry in
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clock-names
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- clock-names: List of external parent clock names. Valid names are:
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- "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
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r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77995)
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- "extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7792,
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r8a7793, r8a7794, r8a7795, r8a7796, r8a77965, r8a77970,
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r8a77980, r8a77990, r8a77995)
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- "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
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- "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
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- "usb_extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7793,
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r8a7794)
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- #clock-cells: Must be 2
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- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
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@ -7,6 +7,7 @@ config CLK_RENESAS
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select CLK_R8A7740 if ARCH_R8A7740
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select CLK_R8A7743 if ARCH_R8A7743
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select CLK_R8A7745 if ARCH_R8A7745
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select CLK_R8A77470 if ARCH_R8A77470
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select CLK_R8A7778 if ARCH_R8A7778
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select CLK_R8A7779 if ARCH_R8A7779
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select CLK_R8A7790 if ARCH_R8A7790
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@ -18,6 +19,7 @@ config CLK_RENESAS
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select CLK_R8A77965 if ARCH_R8A77965
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select CLK_R8A77970 if ARCH_R8A77970
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select CLK_R8A77980 if ARCH_R8A77980
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select CLK_R8A77990 if ARCH_R8A77990
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select CLK_R8A77995 if ARCH_R8A77995
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select CLK_SH73A0 if ARCH_SH73A0
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@ -60,6 +62,10 @@ config CLK_R8A7745
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bool "RZ/G1E clock support" if COMPILE_TEST
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select CLK_RCAR_GEN2_CPG
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config CLK_R8A77470
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bool "RZ/G1C clock support" if COMPILE_TEST
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select CLK_RCAR_GEN2_CPG
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config CLK_R8A7778
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bool "R-Car M1A clock support" if COMPILE_TEST
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select CLK_RENESAS_CPG_MSTP
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@ -111,6 +117,10 @@ config CLK_R8A77980
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bool "R-Car V3H clock support" if COMPILE_TEST
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select CLK_RCAR_GEN3_CPG
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config CLK_R8A77990
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bool "R-Car E3 clock support" if COMPILE_TEST
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select CLK_RCAR_GEN3_CPG
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config CLK_R8A77995
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bool "R-Car D3 clock support" if COMPILE_TEST
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select CLK_RCAR_GEN3_CPG
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@ -6,6 +6,7 @@ obj-$(CONFIG_CLK_R8A73A4) += clk-r8a73a4.o
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obj-$(CONFIG_CLK_R8A7740) += clk-r8a7740.o
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obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7778) += clk-r8a7778.o
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obj-$(CONFIG_CLK_R8A7779) += clk-r8a7779.o
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obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
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@ -17,6 +18,7 @@ obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
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obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
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@ -52,7 +52,6 @@ static const struct cpg_core_clk r8a7743_core_clks[] __initconst = {
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/* Core Clock Outputs */
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DEF_BASE("z", R8A7743_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),
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DEF_BASE("lb", R8A7743_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
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DEF_BASE("sdh", R8A7743_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
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DEF_BASE("sd0", R8A7743_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
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DEF_BASE("qspi", R8A7743_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
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@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7743_core_clks[] __initconst = {
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DEF_FIXED("zs", R8A7743_CLK_ZS, CLK_PLL1, 6, 1),
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DEF_FIXED("hp", R8A7743_CLK_HP, CLK_PLL1, 12, 1),
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DEF_FIXED("b", R8A7743_CLK_B, CLK_PLL1, 12, 1),
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DEF_FIXED("lb", R8A7743_CLK_LB, CLK_PLL1, 24, 1),
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DEF_FIXED("p", R8A7743_CLK_P, CLK_PLL1, 24, 1),
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DEF_FIXED("cl", R8A7743_CLK_CL, CLK_PLL1, 48, 1),
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DEF_FIXED("m2", R8A7743_CLK_M2, CLK_PLL1, 8, 1),
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@ -51,7 +51,6 @@ static const struct cpg_core_clk r8a7745_core_clks[] __initconst = {
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DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
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/* Core Clock Outputs */
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DEF_BASE("lb", R8A7745_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
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DEF_BASE("sdh", R8A7745_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
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DEF_BASE("sd0", R8A7745_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
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DEF_BASE("qspi", R8A7745_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
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@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7745_core_clks[] __initconst = {
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DEF_FIXED("zs", R8A7745_CLK_ZS, CLK_PLL1, 6, 1),
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DEF_FIXED("hp", R8A7745_CLK_HP, CLK_PLL1, 12, 1),
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DEF_FIXED("b", R8A7745_CLK_B, CLK_PLL1, 12, 1),
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DEF_FIXED("lb", R8A7745_CLK_LB, CLK_PLL1, 24, 1),
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DEF_FIXED("p", R8A7745_CLK_P, CLK_PLL1, 24, 1),
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DEF_FIXED("cl", R8A7745_CLK_CL, CLK_PLL1, 48, 1),
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DEF_FIXED("cp", R8A7745_CLK_CP, CLK_PLL1, 48, 1),
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@ -0,0 +1,229 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* r8a77470 Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2018 Renesas Electronics Corp.
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*/
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/soc/renesas/rcar-rst.h>
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#include <dt-bindings/clock/r8a77470-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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#include "rcar-gen2-cpg.h"
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R8A77470_CLK_OSC,
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/* External Input Clocks */
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CLK_EXTAL,
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CLK_USB_EXTAL,
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/* Internal Core Clocks */
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CLK_MAIN,
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CLK_PLL0,
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CLK_PLL1,
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CLK_PLL3,
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CLK_PLL1_DIV2,
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/* Module Clocks */
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MOD_CLK_BASE
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};
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static const struct cpg_core_clk r8a77470_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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DEF_INPUT("usb_extal", CLK_USB_EXTAL),
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/* Internal Core Clocks */
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DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
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DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
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DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
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DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
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DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
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/* Core Clock Outputs */
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DEF_BASE("sdh", R8A77470_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
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DEF_BASE("sd0", R8A77470_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
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DEF_BASE("sd1", R8A77470_CLK_SD1, CLK_TYPE_GEN2_SD1, CLK_PLL1),
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DEF_BASE("qspi", R8A77470_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
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DEF_BASE("rcan", R8A77470_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
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DEF_FIXED("z2", R8A77470_CLK_Z2, CLK_PLL0, 1, 1),
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DEF_FIXED("zx", R8A77470_CLK_ZX, CLK_PLL1, 3, 1),
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DEF_FIXED("zs", R8A77470_CLK_ZS, CLK_PLL1, 6, 1),
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DEF_FIXED("hp", R8A77470_CLK_HP, CLK_PLL1, 12, 1),
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DEF_FIXED("b", R8A77470_CLK_B, CLK_PLL1, 12, 1),
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DEF_FIXED("lb", R8A77470_CLK_LB, CLK_PLL1, 24, 1),
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DEF_FIXED("p", R8A77470_CLK_P, CLK_PLL1, 24, 1),
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DEF_FIXED("cl", R8A77470_CLK_CL, CLK_PLL1, 48, 1),
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DEF_FIXED("cp", R8A77470_CLK_CP, CLK_PLL1, 48, 1),
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DEF_FIXED("m2", R8A77470_CLK_M2, CLK_PLL1, 8, 1),
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DEF_FIXED("zb3", R8A77470_CLK_ZB3, CLK_PLL3, 4, 1),
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DEF_FIXED("mp", R8A77470_CLK_MP, CLK_PLL1_DIV2, 15, 1),
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DEF_FIXED("cpex", R8A77470_CLK_CPEX, CLK_EXTAL, 2, 1),
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DEF_FIXED("r", R8A77470_CLK_R, CLK_PLL1, 49152, 1),
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DEF_FIXED("osc", R8A77470_CLK_OSC, CLK_PLL1, 12288, 1),
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DEF_DIV6P1("sd2", R8A77470_CLK_SD2, CLK_PLL1_DIV2, 0x078),
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};
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static const struct mssr_mod_clk r8a77470_mod_clks[] __initconst = {
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DEF_MOD("msiof0", 0, R8A77470_CLK_MP),
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DEF_MOD("vcp0", 101, R8A77470_CLK_ZS),
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DEF_MOD("vpc0", 103, R8A77470_CLK_ZS),
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DEF_MOD("tmu1", 111, R8A77470_CLK_P),
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DEF_MOD("3dg", 112, R8A77470_CLK_ZS),
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DEF_MOD("2d-dmac", 115, R8A77470_CLK_ZS),
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DEF_MOD("fdp1-0", 119, R8A77470_CLK_ZS),
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DEF_MOD("tmu3", 121, R8A77470_CLK_P),
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DEF_MOD("tmu2", 122, R8A77470_CLK_P),
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DEF_MOD("cmt0", 124, R8A77470_CLK_R),
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DEF_MOD("vsp1du0", 128, R8A77470_CLK_ZS),
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DEF_MOD("vsp1-sy", 131, R8A77470_CLK_ZS),
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DEF_MOD("msiof2", 205, R8A77470_CLK_MP),
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DEF_MOD("msiof1", 208, R8A77470_CLK_MP),
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DEF_MOD("sys-dmac1", 218, R8A77470_CLK_ZS),
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DEF_MOD("sys-dmac0", 219, R8A77470_CLK_ZS),
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DEF_MOD("sdhi2", 312, R8A77470_CLK_SD2),
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DEF_MOD("sdhi1", 313, R8A77470_CLK_SD1),
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DEF_MOD("sdhi0", 314, R8A77470_CLK_SD0),
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DEF_MOD("usbhs-dmac0-ch1", 326, R8A77470_CLK_HP),
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DEF_MOD("usbhs-dmac1-ch1", 327, R8A77470_CLK_HP),
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DEF_MOD("cmt1", 329, R8A77470_CLK_R),
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DEF_MOD("usbhs-dmac0-ch0", 330, R8A77470_CLK_HP),
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DEF_MOD("usbhs-dmac1-ch0", 331, R8A77470_CLK_HP),
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DEF_MOD("rwdt", 402, R8A77470_CLK_R),
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DEF_MOD("irqc", 407, R8A77470_CLK_CP),
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DEF_MOD("intc-sys", 408, R8A77470_CLK_ZS),
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DEF_MOD("audio-dmac0", 502, R8A77470_CLK_HP),
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DEF_MOD("pwm", 523, R8A77470_CLK_P),
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DEF_MOD("usb-ehci-0", 703, R8A77470_CLK_MP),
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DEF_MOD("usbhs-0", 704, R8A77470_CLK_HP),
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DEF_MOD("usb-ehci-1", 705, R8A77470_CLK_MP),
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DEF_MOD("usbhs-1", 706, R8A77470_CLK_HP),
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DEF_MOD("hscif2", 713, R8A77470_CLK_ZS),
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DEF_MOD("scif5", 714, R8A77470_CLK_P),
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DEF_MOD("scif4", 715, R8A77470_CLK_P),
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DEF_MOD("hscif1", 716, R8A77470_CLK_ZS),
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DEF_MOD("hscif0", 717, R8A77470_CLK_ZS),
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DEF_MOD("scif3", 718, R8A77470_CLK_P),
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DEF_MOD("scif2", 719, R8A77470_CLK_P),
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DEF_MOD("scif1", 720, R8A77470_CLK_P),
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DEF_MOD("scif0", 721, R8A77470_CLK_P),
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DEF_MOD("du1", 723, R8A77470_CLK_ZX),
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DEF_MOD("du0", 724, R8A77470_CLK_ZX),
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DEF_MOD("ipmmu-sgx", 800, R8A77470_CLK_ZX),
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DEF_MOD("etheravb", 812, R8A77470_CLK_HP),
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DEF_MOD("ether", 813, R8A77470_CLK_P),
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DEF_MOD("gpio5", 907, R8A77470_CLK_CP),
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DEF_MOD("gpio4", 908, R8A77470_CLK_CP),
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DEF_MOD("gpio3", 909, R8A77470_CLK_CP),
|
||||
DEF_MOD("gpio2", 910, R8A77470_CLK_CP),
|
||||
DEF_MOD("gpio1", 911, R8A77470_CLK_CP),
|
||||
DEF_MOD("gpio0", 912, R8A77470_CLK_CP),
|
||||
DEF_MOD("can1", 915, R8A77470_CLK_P),
|
||||
DEF_MOD("can0", 916, R8A77470_CLK_P),
|
||||
DEF_MOD("qspi_mod-1", 917, R8A77470_CLK_QSPI),
|
||||
DEF_MOD("qspi_mod-0", 918, R8A77470_CLK_QSPI),
|
||||
DEF_MOD("i2c4", 927, R8A77470_CLK_HP),
|
||||
DEF_MOD("i2c3", 928, R8A77470_CLK_HP),
|
||||
DEF_MOD("i2c2", 929, R8A77470_CLK_HP),
|
||||
DEF_MOD("i2c1", 930, R8A77470_CLK_HP),
|
||||
DEF_MOD("i2c0", 931, R8A77470_CLK_HP),
|
||||
DEF_MOD("ssi-all", 1005, R8A77470_CLK_P),
|
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("scu-all", 1017, R8A77470_CLK_P),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
|
||||
};
|
||||
|
||||
static const unsigned int r8a77470_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_ID(402), /* RWDT */
|
||||
MOD_CLK_ID(408), /* INTC-SYS (GIC) */
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL3
|
||||
* 14 13 (MHz) *1 *2
|
||||
*---------------------------------------------------
|
||||
* 0 0 20 x80 x78 x50
|
||||
* 0 1 26 x60 x60 x56
|
||||
* 1 0 Prohibitted setting
|
||||
* 1 1 30 x52 x52 x50
|
||||
*
|
||||
* *1 : Table 7.4 indicates VCO output (PLL0 = VCO)
|
||||
* *2 : Table 7.4 indicates VCO output (PLL1 = VCO)
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
|
||||
(((md) & BIT(13)) >> 13))
|
||||
|
||||
static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] __initconst = {
|
||||
/* EXTAL div PLL1 mult x2 PLL3 mult */
|
||||
{ 1, 156, 50, },
|
||||
{ 1, 120, 56, },
|
||||
{ /* Invalid*/ },
|
||||
{ 1, 104, 50, },
|
||||
};
|
||||
|
||||
static int __init r8a77470_cpg_mssr_init(struct device *dev)
|
||||
{
|
||||
const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
|
||||
u32 cpg_mode;
|
||||
int error;
|
||||
|
||||
error = rcar_rst_read_mode_pins(&cpg_mode);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
|
||||
return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);
|
||||
}
|
||||
|
||||
const struct cpg_mssr_info r8a77470_cpg_mssr_info __initconst = {
|
||||
/* Core Clocks */
|
||||
.core_clks = r8a77470_core_clks,
|
||||
.num_core_clks = ARRAY_SIZE(r8a77470_core_clks),
|
||||
.last_dt_core_clk = LAST_DT_CORE_CLK,
|
||||
.num_total_core_clks = MOD_CLK_BASE,
|
||||
|
||||
/* Module Clocks */
|
||||
.mod_clks = r8a77470_mod_clks,
|
||||
.num_mod_clks = ARRAY_SIZE(r8a77470_mod_clks),
|
||||
.num_hw_mod_clks = 12 * 32,
|
||||
|
||||
/* Critical Module Clocks */
|
||||
.crit_mod_clks = r8a77470_crit_mod_clks,
|
||||
.num_crit_mod_clks = ARRAY_SIZE(r8a77470_crit_mod_clks),
|
||||
|
||||
/* Callbacks */
|
||||
.init = r8a77470_cpg_mssr_init,
|
||||
.cpg_clk_register = rcar_gen2_cpg_clk_register,
|
||||
};
|
||||
|
|
@ -57,7 +57,6 @@ static struct cpg_core_clk r8a7791_core_clks[] __initdata = {
|
|||
|
||||
/* Core Clock Outputs */
|
||||
DEF_BASE("z", R8A7791_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),
|
||||
DEF_BASE("lb", R8A7791_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
|
||||
DEF_BASE("adsp", R8A7791_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
|
||||
DEF_BASE("sdh", R8A7791_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
|
||||
DEF_BASE("sd0", R8A7791_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
|
||||
|
|
@ -70,6 +69,7 @@ static struct cpg_core_clk r8a7791_core_clks[] __initdata = {
|
|||
DEF_FIXED("hp", R8A7791_CLK_HP, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("i", R8A7791_CLK_I, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED("b", R8A7791_CLK_B, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("lb", R8A7791_CLK_LB, CLK_PLL1, 24, 1),
|
||||
DEF_FIXED("p", R8A7791_CLK_P, CLK_PLL1, 24, 1),
|
||||
DEF_FIXED("cl", R8A7791_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("m2", R8A7791_CLK_M2, CLK_PLL1, 8, 1),
|
||||
|
|
|
|||
|
|
@ -53,7 +53,6 @@ static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
|
|||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_BASE("lb", R8A7792_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
|
||||
DEF_BASE("qspi", R8A7792_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
|
||||
|
||||
DEF_FIXED("z", R8A7792_CLK_Z, CLK_PLL0, 1, 1),
|
||||
|
|
@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
|
|||
DEF_FIXED("hp", R8A7792_CLK_HP, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("i", R8A7792_CLK_I, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED("b", R8A7792_CLK_B, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("lb", R8A7792_CLK_LB, CLK_PLL1, 24, 1),
|
||||
DEF_FIXED("p", R8A7792_CLK_P, CLK_PLL1, 24, 1),
|
||||
DEF_FIXED("cl", R8A7792_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("m2", R8A7792_CLK_M2, CLK_PLL1, 8, 1),
|
||||
|
|
|
|||
|
|
@ -55,7 +55,6 @@ static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
|
|||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_BASE("lb", R8A7794_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
|
||||
DEF_BASE("adsp", R8A7794_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
|
||||
DEF_BASE("sdh", R8A7794_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
|
||||
DEF_BASE("sd0", R8A7794_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
|
||||
|
|
@ -69,6 +68,7 @@ static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
|
|||
DEF_FIXED("hp", R8A7794_CLK_HP, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("i", R8A7794_CLK_I, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED("b", R8A7794_CLK_B, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("lb", R8A7794_CLK_LB, CLK_PLL1, 24, 1),
|
||||
DEF_FIXED("p", R8A7794_CLK_P, CLK_PLL1, 24, 1),
|
||||
DEF_FIXED("cl", R8A7794_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("cp", R8A7794_CLK_CP, CLK_PLL1, 48, 1),
|
||||
|
|
|
|||
|
|
@ -116,6 +116,10 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
|
|||
DEF_MOD("scif3", 204, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("scif1", 206, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("scif0", 207, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("msiof3", 208, R8A77965_CLK_MSO),
|
||||
DEF_MOD("msiof2", 209, R8A77965_CLK_MSO),
|
||||
DEF_MOD("msiof1", 210, R8A77965_CLK_MSO),
|
||||
DEF_MOD("msiof0", 211, R8A77965_CLK_MSO),
|
||||
DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S0D3),
|
||||
DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S0D3),
|
||||
DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3),
|
||||
|
|
|
|||
|
|
@ -116,7 +116,7 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
|
|||
DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3),
|
||||
DEF_MOD("tpu0", 304, R8A77980_CLK_S3D4),
|
||||
DEF_MOD("sdif", 314, R8A77980_CLK_SD0),
|
||||
DEF_MOD("pciec0", 319, R8A77980_CLK_S3D1),
|
||||
DEF_MOD("pciec0", 319, R8A77980_CLK_S2D2),
|
||||
DEF_MOD("intc-ex", 407, R8A77980_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3),
|
||||
DEF_MOD("hscif3", 517, R8A77980_CLK_S3D1),
|
||||
|
|
|
|||
|
|
@ -0,0 +1,289 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* r8a77990 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
*
|
||||
* Based on r8a7795-cpg-mssr.c
|
||||
*
|
||||
* Copyright (C) 2015 Glider bvba
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/soc/renesas/rcar-rst.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a77990-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen3-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A77990_CLK_CPEX,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL3,
|
||||
CLK_PLL0D4,
|
||||
CLK_PLL0D6,
|
||||
CLK_PLL0D8,
|
||||
CLK_PLL0D20,
|
||||
CLK_PLL0D24,
|
||||
CLK_PLL1D2,
|
||||
CLK_PE,
|
||||
CLK_S0,
|
||||
CLK_S1,
|
||||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 1, 100),
|
||||
DEF_FIXED(".pll0d4", CLK_PLL0D4, CLK_PLL0, 4, 1),
|
||||
DEF_FIXED(".pll0d6", CLK_PLL0D6, CLK_PLL0, 6, 1),
|
||||
DEF_FIXED(".pll0d8", CLK_PLL0D8, CLK_PLL0, 8, 1),
|
||||
DEF_FIXED(".pll0d20", CLK_PLL0D20, CLK_PLL0, 20, 1),
|
||||
DEF_FIXED(".pll0d24", CLK_PLL0D24, CLK_PLL0, 24, 1),
|
||||
DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".pe", CLK_PE, CLK_PLL0D20, 1, 1),
|
||||
DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1),
|
||||
DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1),
|
||||
DEF_FIXED("ztr", R8A77990_CLK_ZTR, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED("zt", R8A77990_CLK_ZT, CLK_PLL1, 4, 1),
|
||||
DEF_FIXED("zx", R8A77990_CLK_ZX, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED("s0d1", R8A77990_CLK_S0D1, CLK_S0, 1, 1),
|
||||
DEF_FIXED("s0d3", R8A77990_CLK_S0D3, CLK_S0, 3, 1),
|
||||
DEF_FIXED("s0d6", R8A77990_CLK_S0D6, CLK_S0, 6, 1),
|
||||
DEF_FIXED("s0d12", R8A77990_CLK_S0D12, CLK_S0, 12, 1),
|
||||
DEF_FIXED("s0d24", R8A77990_CLK_S0D24, CLK_S0, 24, 1),
|
||||
DEF_FIXED("s1d1", R8A77990_CLK_S1D1, CLK_S1, 1, 1),
|
||||
DEF_FIXED("s1d2", R8A77990_CLK_S1D2, CLK_S1, 2, 1),
|
||||
DEF_FIXED("s1d4", R8A77990_CLK_S1D4, CLK_S1, 4, 1),
|
||||
DEF_FIXED("s2d1", R8A77990_CLK_S2D1, CLK_S2, 1, 1),
|
||||
DEF_FIXED("s2d2", R8A77990_CLK_S2D2, CLK_S2, 2, 1),
|
||||
DEF_FIXED("s2d4", R8A77990_CLK_S2D4, CLK_S2, 4, 1),
|
||||
DEF_FIXED("s3d1", R8A77990_CLK_S3D1, CLK_S3, 1, 1),
|
||||
DEF_FIXED("s3d2", R8A77990_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A77990_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A77990_CLK_SD0, CLK_SDSRC, 0x0074),
|
||||
DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, CLK_SDSRC, 0x0078),
|
||||
DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, CLK_SDSRC, 0x026c),
|
||||
|
||||
DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("cp", R8A77990_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A77990_CLK_CPEX, CLK_EXTAL, 4, 1),
|
||||
DEF_FIXED("osc", R8A77990_CLK_OSC, CLK_EXTAL, 384, 1),
|
||||
DEF_FIXED("r", R8A77990_CLK_R, CLK_EXTAL, 1536, 1),
|
||||
|
||||
DEF_GEN3_PE("s0d6c", R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2),
|
||||
DEF_GEN3_PE("s3d1c", R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
|
||||
DEF_GEN3_PE("s3d2c", R8A77990_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
|
||||
DEF_GEN3_PE("s3d4c", R8A77990_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
|
||||
|
||||
DEF_DIV6P1("canfd", R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244),
|
||||
DEF_DIV6P1("csi0", R8A77990_CLK_CSI0, CLK_PLL1D2, 0x00c),
|
||||
DEF_DIV6P1("mso", R8A77990_CLK_MSO, CLK_PLL1D2, 0x014),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
|
||||
DEF_MOD("scif5", 202, R8A77990_CLK_S3D4C),
|
||||
DEF_MOD("scif4", 203, R8A77990_CLK_S3D4C),
|
||||
DEF_MOD("scif3", 204, R8A77990_CLK_S3D4C),
|
||||
DEF_MOD("scif1", 206, R8A77990_CLK_S3D4C),
|
||||
DEF_MOD("scif0", 207, R8A77990_CLK_S3D4C),
|
||||
DEF_MOD("msiof3", 208, R8A77990_CLK_MSO),
|
||||
DEF_MOD("msiof2", 209, R8A77990_CLK_MSO),
|
||||
DEF_MOD("msiof1", 210, R8A77990_CLK_MSO),
|
||||
DEF_MOD("msiof0", 211, R8A77990_CLK_MSO),
|
||||
DEF_MOD("sys-dmac2", 217, R8A77990_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac1", 218, R8A77990_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac0", 219, R8A77990_CLK_S3D1),
|
||||
|
||||
DEF_MOD("cmt3", 300, R8A77990_CLK_R),
|
||||
DEF_MOD("cmt2", 301, R8A77990_CLK_R),
|
||||
DEF_MOD("cmt1", 302, R8A77990_CLK_R),
|
||||
DEF_MOD("cmt0", 303, R8A77990_CLK_R),
|
||||
DEF_MOD("scif2", 310, R8A77990_CLK_S3D4C),
|
||||
DEF_MOD("sdif3", 311, R8A77990_CLK_SD3),
|
||||
DEF_MOD("sdif1", 313, R8A77990_CLK_SD1),
|
||||
DEF_MOD("sdif0", 314, R8A77990_CLK_SD0),
|
||||
DEF_MOD("pcie0", 319, R8A77990_CLK_S3D1),
|
||||
DEF_MOD("usb3-if0", 328, R8A77990_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac0", 330, R8A77990_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac1", 331, R8A77990_CLK_S3D1),
|
||||
|
||||
DEF_MOD("rwdt", 402, R8A77990_CLK_R),
|
||||
DEF_MOD("intc-ex", 407, R8A77990_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A77990_CLK_S0D3),
|
||||
|
||||
DEF_MOD("audmac0", 502, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("drif7", 508, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("drif6", 509, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("drif5", 510, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("drif4", 511, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("drif3", 512, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("drif2", 513, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("drif1", 514, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("drif0", 515, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("hscif4", 516, R8A77990_CLK_S3D1C),
|
||||
DEF_MOD("hscif3", 517, R8A77990_CLK_S3D1C),
|
||||
DEF_MOD("hscif2", 518, R8A77990_CLK_S3D1C),
|
||||
DEF_MOD("hscif1", 519, R8A77990_CLK_S3D1C),
|
||||
DEF_MOD("hscif0", 520, R8A77990_CLK_S3D1C),
|
||||
DEF_MOD("thermal", 522, R8A77990_CLK_CP),
|
||||
DEF_MOD("pwm", 523, R8A77990_CLK_S3D4C),
|
||||
|
||||
DEF_MOD("fcpvd1", 602, R8A77990_CLK_S1D2),
|
||||
DEF_MOD("fcpvd0", 603, R8A77990_CLK_S1D2),
|
||||
DEF_MOD("fcpvb0", 607, R8A77990_CLK_S0D1),
|
||||
DEF_MOD("fcpvi0", 611, R8A77990_CLK_S0D1),
|
||||
DEF_MOD("fcpf0", 615, R8A77990_CLK_S0D1),
|
||||
DEF_MOD("fcpcs", 619, R8A77990_CLK_S0D1),
|
||||
DEF_MOD("vspd1", 622, R8A77990_CLK_S1D2),
|
||||
DEF_MOD("vspd0", 623, R8A77990_CLK_S1D2),
|
||||
DEF_MOD("vspb", 626, R8A77990_CLK_S0D1),
|
||||
DEF_MOD("vspi0", 631, R8A77990_CLK_S0D1),
|
||||
|
||||
DEF_MOD("ehci0", 703, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("hsusb", 704, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("csi40", 716, R8A77990_CLK_CSI0),
|
||||
DEF_MOD("du1", 723, R8A77990_CLK_S2D1),
|
||||
DEF_MOD("du0", 724, R8A77990_CLK_S2D1),
|
||||
DEF_MOD("lvds", 727, R8A77990_CLK_S2D1),
|
||||
|
||||
DEF_MOD("vin5", 806, R8A77990_CLK_S1D2),
|
||||
DEF_MOD("vin4", 807, R8A77990_CLK_S1D2),
|
||||
DEF_MOD("etheravb", 812, R8A77990_CLK_S3D2),
|
||||
|
||||
DEF_MOD("gpio6", 906, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("gpio5", 907, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("gpio4", 908, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("gpio3", 909, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("gpio2", 910, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("gpio1", 911, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("gpio0", 912, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("can-fd", 914, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("can-if1", 915, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("can-if0", 916, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("i2c6", 918, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("i2c5", 919, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("i2c-dvfs", 926, R8A77990_CLK_CP),
|
||||
DEF_MOD("i2c4", 927, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("i2c3", 928, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("i2c2", 929, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("i2c1", 930, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("i2c0", 931, R8A77990_CLK_S3D2),
|
||||
|
||||
DEF_MOD("ssi-all", 1005, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("scu-all", 1017, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
|
||||
};
|
||||
|
||||
static const unsigned int r8a77990_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_ID(408), /* INTC-AP (GIC) */
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD19 EXTAL (MHz) PLL0 PLL1 PLL3
|
||||
*--------------------------------------------------------------------
|
||||
* 0 48 x 1 x100/4 x100/3 x100/3
|
||||
* 1 48 x 1 x100/4 x100/3 x58/3
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div */
|
||||
{ 1, 100, 3, 100, 3, },
|
||||
{ 1, 100, 3, 58, 3, },
|
||||
};
|
||||
|
||||
static int __init r8a77990_cpg_mssr_init(struct device *dev)
|
||||
{
|
||||
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
|
||||
u32 cpg_mode;
|
||||
int error;
|
||||
|
||||
error = rcar_rst_read_mode_pins(&cpg_mode);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
|
||||
return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode);
|
||||
}
|
||||
|
||||
const struct cpg_mssr_info r8a77990_cpg_mssr_info __initconst = {
|
||||
/* Core Clocks */
|
||||
.core_clks = r8a77990_core_clks,
|
||||
.num_core_clks = ARRAY_SIZE(r8a77990_core_clks),
|
||||
.last_dt_core_clk = LAST_DT_CORE_CLK,
|
||||
.num_total_core_clks = MOD_CLK_BASE,
|
||||
|
||||
/* Module Clocks */
|
||||
.mod_clks = r8a77990_mod_clks,
|
||||
.num_mod_clks = ARRAY_SIZE(r8a77990_mod_clks),
|
||||
.num_hw_mod_clks = 12 * 32,
|
||||
|
||||
/* Critical Module Clocks */
|
||||
.crit_mod_clks = r8a77990_crit_mod_clks,
|
||||
.num_crit_mod_clks = ARRAY_SIZE(r8a77990_crit_mod_clks),
|
||||
|
||||
/* Callbacks */
|
||||
.init = r8a77990_cpg_mssr_init,
|
||||
.cpg_clk_register = rcar_gen3_cpg_clk_register,
|
||||
};
|
||||
|
|
@ -16,6 +16,7 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/sys_soc.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen2-cpg.h"
|
||||
|
|
@ -260,6 +261,17 @@ static const struct clk_div_table cpg_sd01_div_table[] = {
|
|||
static const struct rcar_gen2_cpg_pll_config *cpg_pll_config __initdata;
|
||||
static unsigned int cpg_pll0_div __initdata;
|
||||
static u32 cpg_mode __initdata;
|
||||
static u32 cpg_quirks __initdata;
|
||||
|
||||
#define SD_SKIP_FIRST BIT(0) /* Skip first clock in SD table */
|
||||
|
||||
static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
|
||||
{
|
||||
.soc_id = "r8a77470",
|
||||
.data = (void *)SD_SKIP_FIRST,
|
||||
},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
|
||||
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
|
||||
|
|
@ -327,11 +339,17 @@ struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
|
|||
|
||||
case CLK_TYPE_GEN2_SD0:
|
||||
table = cpg_sd01_div_table;
|
||||
if (cpg_quirks & SD_SKIP_FIRST)
|
||||
table++;
|
||||
|
||||
shift = 4;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN2_SD1:
|
||||
table = cpg_sd01_div_table;
|
||||
if (cpg_quirks & SD_SKIP_FIRST)
|
||||
table++;
|
||||
|
||||
shift = 0;
|
||||
break;
|
||||
|
||||
|
|
@ -360,9 +378,15 @@ struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
|
|||
int __init rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config,
|
||||
unsigned int pll0_div, u32 mode)
|
||||
{
|
||||
const struct soc_device_attribute *attr;
|
||||
|
||||
cpg_pll_config = config;
|
||||
cpg_pll0_div = pll0_div;
|
||||
cpg_mode = mode;
|
||||
attr = soc_device_match(cpg_quirks_match);
|
||||
if (attr)
|
||||
cpg_quirks = (uintptr_t)attr->data;
|
||||
pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);
|
||||
|
||||
spin_lock_init(&cpg_lock);
|
||||
|
||||
|
|
|
|||
|
|
@ -652,6 +652,12 @@ static const struct of_device_id cpg_mssr_match[] = {
|
|||
.data = &r8a7745_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R8A77470
|
||||
{
|
||||
.compatible = "renesas,r8a77470-cpg-mssr",
|
||||
.data = &r8a77470_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R8A7790
|
||||
{
|
||||
.compatible = "renesas,r8a7790-cpg-mssr",
|
||||
|
|
@ -711,6 +717,12 @@ static const struct of_device_id cpg_mssr_match[] = {
|
|||
.data = &r8a77980_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R8A77990
|
||||
{
|
||||
.compatible = "renesas,r8a77990-cpg-mssr",
|
||||
.data = &r8a77990_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R8A77995
|
||||
{
|
||||
.compatible = "renesas,r8a77995-cpg-mssr",
|
||||
|
|
|
|||
|
|
@ -133,6 +133,7 @@ struct cpg_mssr_info {
|
|||
|
||||
extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a77470_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a7790_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a7791_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a7792_cpg_mssr_info;
|
||||
|
|
@ -142,6 +143,7 @@ extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
|
|||
extern const struct cpg_mssr_info r8a77965_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a77970_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a77980_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a77990_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,36 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* r8a77470 CPG Core Clocks */
|
||||
#define R8A77470_CLK_Z2 0
|
||||
#define R8A77470_CLK_ZTR 1
|
||||
#define R8A77470_CLK_ZTRD2 2
|
||||
#define R8A77470_CLK_ZT 3
|
||||
#define R8A77470_CLK_ZX 4
|
||||
#define R8A77470_CLK_ZS 5
|
||||
#define R8A77470_CLK_HP 6
|
||||
#define R8A77470_CLK_B 7
|
||||
#define R8A77470_CLK_LB 8
|
||||
#define R8A77470_CLK_P 9
|
||||
#define R8A77470_CLK_CL 10
|
||||
#define R8A77470_CLK_CP 11
|
||||
#define R8A77470_CLK_M2 12
|
||||
#define R8A77470_CLK_ZB3 13
|
||||
#define R8A77470_CLK_SDH 14
|
||||
#define R8A77470_CLK_SD0 15
|
||||
#define R8A77470_CLK_SD1 16
|
||||
#define R8A77470_CLK_SD2 17
|
||||
#define R8A77470_CLK_MP 18
|
||||
#define R8A77470_CLK_QSPI 19
|
||||
#define R8A77470_CLK_CPEX 20
|
||||
#define R8A77470_CLK_RCAN 21
|
||||
#define R8A77470_CLK_R 22
|
||||
#define R8A77470_CLK_OSC 23
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ */
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* r8a77990 CPG Core Clocks */
|
||||
#define R8A77990_CLK_Z2 0
|
||||
#define R8A77990_CLK_ZR 1
|
||||
#define R8A77990_CLK_ZG 2
|
||||
#define R8A77990_CLK_ZTR 3
|
||||
#define R8A77990_CLK_ZT 4
|
||||
#define R8A77990_CLK_ZX 5
|
||||
#define R8A77990_CLK_S0D1 6
|
||||
#define R8A77990_CLK_S0D3 7
|
||||
#define R8A77990_CLK_S0D6 8
|
||||
#define R8A77990_CLK_S0D12 9
|
||||
#define R8A77990_CLK_S0D24 10
|
||||
#define R8A77990_CLK_S1D1 11
|
||||
#define R8A77990_CLK_S1D2 12
|
||||
#define R8A77990_CLK_S1D4 13
|
||||
#define R8A77990_CLK_S2D1 14
|
||||
#define R8A77990_CLK_S2D2 15
|
||||
#define R8A77990_CLK_S2D4 16
|
||||
#define R8A77990_CLK_S3D1 17
|
||||
#define R8A77990_CLK_S3D2 18
|
||||
#define R8A77990_CLK_S3D4 19
|
||||
#define R8A77990_CLK_S0D6C 20
|
||||
#define R8A77990_CLK_S3D1C 21
|
||||
#define R8A77990_CLK_S3D2C 22
|
||||
#define R8A77990_CLK_S3D4C 23
|
||||
#define R8A77990_CLK_LB 24
|
||||
#define R8A77990_CLK_CL 25
|
||||
#define R8A77990_CLK_ZB3 26
|
||||
#define R8A77990_CLK_ZB3D2 27
|
||||
#define R8A77990_CLK_CR 28
|
||||
#define R8A77990_CLK_CRD2 29
|
||||
#define R8A77990_CLK_SD0H 30
|
||||
#define R8A77990_CLK_SD0 31
|
||||
#define R8A77990_CLK_SD1H 32
|
||||
#define R8A77990_CLK_SD1 33
|
||||
#define R8A77990_CLK_SD3H 34
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#define R8A77990_CLK_SD3 35
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#define R8A77990_CLK_RPC 36
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#define R8A77990_CLK_RPCD2 37
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#define R8A77990_CLK_ZA2 38
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#define R8A77990_CLK_ZA8 39
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#define R8A77990_CLK_Z2D 40
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#define R8A77990_CLK_CANFD 41
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#define R8A77990_CLK_MSO 42
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#define R8A77990_CLK_R 43
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#define R8A77990_CLK_OSC 44
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#define R8A77990_CLK_LV0 45
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#define R8A77990_CLK_LV1 46
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#define R8A77990_CLK_CSI0 47
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#define R8A77990_CLK_CP 48
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#define R8A77990_CLK_CPEX 49
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#endif /* __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ */
|
||||
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Reference in New Issue