iwlwifi: use pci registers defined in pci_regs.h
This patch replaces where possible usage of pci register defined in the driver by ones defined in pci_regs.h Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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3fdb68de22
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@ -229,12 +229,6 @@ struct iwl3945_eeprom {
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/* End of EEPROM */
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#define PCI_LINK_CTRL 0x0F0
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#define PCI_POWER_SOURCE 0x0C8
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#define PCI_REG_WUM8 0x0E8
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#define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000)
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#define PCI_CFG_REV_ID_BIT_BASIC_SKU (0x40) /* bit 6 */
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#define PCI_CFG_REV_ID_BIT_RTP (0x80) /* bit 7 */
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@ -905,22 +905,18 @@ u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
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static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
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{
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int rc;
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int ret;
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unsigned long flags;
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spin_lock_irqsave(&priv->lock, flags);
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rc = iwl_grab_nic_access(priv);
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if (rc) {
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ret = iwl_grab_nic_access(priv);
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if (ret) {
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spin_unlock_irqrestore(&priv->lock, flags);
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return rc;
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return ret;
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}
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if (src == IWL_PWR_SRC_VAUX) {
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u32 val;
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rc = pci_read_config_dword(priv->pci_dev,
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PCI_POWER_SOURCE, &val);
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if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
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if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
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iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
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APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
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~APMG_PS_CTRL_MSK_PWR_SRC);
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@ -929,8 +925,9 @@ static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
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iwl_poll_bit(priv, CSR_GPIO_IN,
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CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
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CSR_GPIO_IN_BIT_AUX_POWER, 5000);
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} else
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} else {
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iwl_release_nic_access(priv);
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}
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} else {
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iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
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APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
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@ -942,7 +939,7 @@ static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
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}
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spin_unlock_irqrestore(&priv->lock, flags);
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return rc;
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return ret;
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}
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static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
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@ -92,19 +92,12 @@
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#define IWL49_RSSI_OFFSET 44
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/* PCI registers */
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#define PCI_CFG_RETRY_TIMEOUT 0x041
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#define PCI_CFG_POWER_SOURCE 0x0C8
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#define PCI_REG_WUM8 0x0E8
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#define PCI_CFG_LINK_CTRL 0x0F0
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/* PCI register values */
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#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
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#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
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#define PCI_CFG_CMD_REG_INT_DIS_MSK 0x04
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#define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000)
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#define IWL_NUM_SCAN_RATES (2)
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@ -381,27 +381,30 @@ out:
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static void iwl4965_nic_config(struct iwl_priv *priv)
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{
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unsigned long flags;
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u32 val;
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u16 dctl;
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u16 radio_cfg;
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u16 link;
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u16 lctl;
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spin_lock_irqsave(&priv->lock, flags);
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if ((priv->rev_id & 0x80) == 0x80 && (priv->rev_id & 0x7f) < 8) {
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pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
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int pos = pci_find_capability(priv->pci_dev, PCI_CAP_ID_EXP);
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pci_read_config_word(priv->pci_dev, pos + PCI_EXP_DEVCTL, &dctl);
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/* Enable No Snoop field */
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pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
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val & ~(1 << 11));
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pci_write_config_word(priv->pci_dev, pos + PCI_EXP_DEVCTL,
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dctl & ~PCI_EXP_DEVCTL_NOSNOOP_EN);
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}
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pci_read_config_word(priv->pci_dev, PCI_CFG_LINK_CTRL, &link);
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lctl = iwl_pcie_link_ctl(priv);
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/* L1 is enabled by BIOS */
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if ((link & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
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/* disable L0S disabled L1A enabled */
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/* HW bug W/A - negligible power consumption */
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/* L1-ASPM is enabled by BIOS */
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if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
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/* L1-ASPM enabled: disable L0S */
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iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
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else
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/* L0S enabled L1A disabled */
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/* L1-ASPM disabled: enable L0S */
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iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
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radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
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@ -219,18 +219,19 @@ static void iwl5000_nic_config(struct iwl_priv *priv)
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{
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unsigned long flags;
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u16 radio_cfg;
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u16 link;
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u16 lctl;
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spin_lock_irqsave(&priv->lock, flags);
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pci_read_config_word(priv->pci_dev, PCI_CFG_LINK_CTRL, &link);
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lctl = iwl_pcie_link_ctl(priv);
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/* L1 is enabled by BIOS */
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if ((link & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
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/* disable L0S disabled L1A enabled */
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/* HW bug W/A */
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/* L1-ASPM is enabled by BIOS */
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if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
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/* L1-APSM enabled: disable L0S */
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iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
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else
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/* L0S enabled L1A disabled */
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/* L1-ASPM disabled: enable L0S */
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iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
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radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
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@ -940,11 +940,7 @@ int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
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goto err;
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if (src == IWL_PWR_SRC_VAUX) {
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u32 val;
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ret = pci_read_config_dword(priv->pci_dev, PCI_CFG_POWER_SOURCE,
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&val);
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if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT)
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if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
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iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
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APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
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~APMG_PS_CTRL_MSK_PWR_SRC);
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@ -410,6 +410,14 @@ int iwl_send_card_state(struct iwl_priv *priv, u32 flags,
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*****************************************************/
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void iwl_disable_interrupts(struct iwl_priv *priv);
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void iwl_enable_interrupts(struct iwl_priv *priv);
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static inline u16 iwl_pcie_link_ctl(struct iwl_priv *priv)
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{
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int pos;
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u16 pci_lnk_ctl;
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pos = pci_find_capability(priv->pci_dev, PCI_CAP_ID_EXP);
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pci_read_config_word(priv->pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
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return pci_lnk_ctl;
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}
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/*****************************************************
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* Error Handling Debugging
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@ -141,7 +141,7 @@ static void iwl_power_init_handle(struct iwl_priv *priv)
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int size = sizeof(struct iwl_power_vec_entry) * IWL_POWER_MAX;
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struct iwl_powertable_cmd *cmd;
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int i;
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u16 pci_pm;
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u16 lctl;
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IWL_DEBUG_POWER(priv, "Initialize power \n");
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@ -153,14 +153,14 @@ static void iwl_power_init_handle(struct iwl_priv *priv)
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memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
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memcpy(&pow_data->pwr_range_2[0], &range_2[0], size);
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pci_read_config_word(priv->pci_dev, PCI_CFG_LINK_CTRL, &pci_pm);
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lctl = iwl_pcie_link_ctl(priv);
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IWL_DEBUG_POWER(priv, "adjust power command flags\n");
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for (i = 0; i < IWL_POWER_MAX; i++) {
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cmd = &pow_data->pwr_range_0[i].cmd;
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if (pci_pm & PCI_CFG_LINK_CTRL_VAL_L0S_EN)
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if (lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN)
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cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
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else
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cmd->flags |= IWL_POWER_PCI_PM_MSK;
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