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ASoC: dwc: Use fifo depth to program FCR 

This patch makes Designware I2S driver use the fifo
depth value to program the fifo configuration register
instead of using hardcoded values.

Signed-off-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Jose Abreu 2016-04-07 17:53:57 +01:00 committed by Mark Brown
parent 613c7c4003
commit 3fafd14d94
1 changed files with 7 additions and 2 deletions
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9
sound/soc/dwc/designware_i2s.c
View File

@ -100,6 +100,7 @@ struct dw_i2s_dev {
struct device *dev; struct device *dev;
u32 ccr; u32 ccr;
u32 xfer_resolution; u32 xfer_resolution;
u32 fifo_th;
/* data related to DMA transfers b/w i2s and DMAC */ /* data related to DMA transfers b/w i2s and DMAC */
union dw_i2s_snd_dma_data play_dma_data; union dw_i2s_snd_dma_data play_dma_data;
@ -232,14 +233,16 @@ static void dw_i2s_config(struct dw_i2s_dev *dev, int stream)
if (stream == SNDRV_PCM_STREAM_PLAYBACK) { if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
i2s_write_reg(dev->i2s_base, TCR(ch_reg), i2s_write_reg(dev->i2s_base, TCR(ch_reg),
dev->xfer_resolution); dev->xfer_resolution);
i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02); i2s_write_reg(dev->i2s_base, TFCR(ch_reg),
dev->fifo_th - 1);
irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg)); irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30); i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30);
i2s_write_reg(dev->i2s_base, TER(ch_reg), 1); i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
} else { } else {
i2s_write_reg(dev->i2s_base, RCR(ch_reg), i2s_write_reg(dev->i2s_base, RCR(ch_reg),
dev->xfer_resolution); dev->xfer_resolution);
i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07); i2s_write_reg(dev->i2s_base, RFCR(ch_reg),
dev->fifo_th - 1);
irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg)); irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03); i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03);
i2s_write_reg(dev->i2s_base, RER(ch_reg), 1); i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
@ -499,6 +502,7 @@ static int dw_configure_dai(struct dw_i2s_dev *dev,
*/ */
u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1); u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2); u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2);
u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
u32 idx; u32 idx;
if (dev->capability & DWC_I2S_RECORD && if (dev->capability & DWC_I2S_RECORD &&
@ -537,6 +541,7 @@ static int dw_configure_dai(struct dw_i2s_dev *dev,
dev->capability |= DW_I2S_SLAVE; dev->capability |= DW_I2S_SLAVE;
} }
dev->fifo_th = fifo_depth / 2;
return 0; return 0;
} }