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drm/i915/tv: Rip out pipe-disabling nonsense from ->mode_set 

The pipe and plane _are_ disabled when we call this. So replace it
all with the corresponding assert (as self-documenting code) and
rip out all the lore.

Checking for a disabled plane would require us to export those macros
from intel_display.c, but if the pipe is off the plane isn't working
either. So this single check is good enough.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter 2014-04-24 23:54:42 +02:00
parent 5da92eeff8
commit 3fa2dd14cf
1 changed files with 18 additions and 38 deletions
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56
drivers/gpu/drm/i915/intel_tv.c
View File

@ -1026,7 +1026,8 @@ static void intel_tv_mode_set(struct intel_encoder *encoder)
const struct video_levels *video_levels; const struct video_levels *video_levels;
const struct color_conversion *color_conversion; const struct color_conversion *color_conversion;
bool burst_ena; bool burst_ena;
int pipe = intel_crtc->pipe; int xpos = 0x0, ypos = 0x0;
unsigned int xsize, ysize;
if (!tv_mode) if (!tv_mode)
return; /* can't happen (mode_prepare prevents this) */ return; /* can't happen (mode_prepare prevents this) */
@ -1110,46 +1111,25 @@ static void intel_tv_mode_set(struct intel_encoder *encoder)
I915_WRITE(TV_CLR_LEVEL, I915_WRITE(TV_CLR_LEVEL,
((video_levels->black << TV_BLACK_LEVEL_SHIFT) | ((video_levels->black << TV_BLACK_LEVEL_SHIFT) |
(video_levels->blank << TV_BLANK_LEVEL_SHIFT))); (video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
{
int pipeconf_reg = PIPECONF(pipe);
int dspcntr_reg = DSPCNTR(intel_crtc->plane);
int pipeconf = I915_READ(pipeconf_reg);
int dspcntr = I915_READ(dspcntr_reg);
int xpos = 0x0, ypos = 0x0;
unsigned int xsize, ysize;
/* Pipe must be off here */
I915_WRITE(dspcntr_reg, dspcntr & ~DISPLAY_PLANE_ENABLE);
intel_flush_primary_plane(dev_priv, intel_crtc->plane);
/* Wait for vblank for the disable to take effect */ assert_pipe_disabled(dev_priv, intel_crtc->pipe);
if (IS_GEN2(dev))
intel_wait_for_vblank(dev, intel_crtc->pipe);
I915_WRITE(pipeconf_reg, pipeconf & ~PIPECONF_ENABLE); /* Filter ctl must be set before TV_WIN_SIZE */
/* Wait for vblank for the disable to take effect. */ I915_WRITE(TV_FILTER_CTL_1, TV_AUTO_SCALE);
intel_wait_for_pipe_off(dev, intel_crtc->pipe); xsize = tv_mode->hblank_start - tv_mode->hblank_end;
if (tv_mode->progressive)
ysize = tv_mode->nbr_end + 1;
else
ysize = 2*tv_mode->nbr_end + 1;
/* Filter ctl must be set before TV_WIN_SIZE */ xpos += intel_tv->margin[TV_MARGIN_LEFT];
I915_WRITE(TV_FILTER_CTL_1, TV_AUTO_SCALE); ypos += intel_tv->margin[TV_MARGIN_TOP];
xsize = tv_mode->hblank_start - tv_mode->hblank_end; xsize -= (intel_tv->margin[TV_MARGIN_LEFT] +
if (tv_mode->progressive) intel_tv->margin[TV_MARGIN_RIGHT]);
ysize = tv_mode->nbr_end + 1; ysize -= (intel_tv->margin[TV_MARGIN_TOP] +
else intel_tv->margin[TV_MARGIN_BOTTOM]);
ysize = 2*tv_mode->nbr_end + 1; I915_WRITE(TV_WIN_POS, (xpos<<16)|ypos);
I915_WRITE(TV_WIN_SIZE, (xsize<<16)|ysize);
xpos += intel_tv->margin[TV_MARGIN_LEFT];
ypos += intel_tv->margin[TV_MARGIN_TOP];
xsize -= (intel_tv->margin[TV_MARGIN_LEFT] +
intel_tv->margin[TV_MARGIN_RIGHT]);
ysize -= (intel_tv->margin[TV_MARGIN_TOP] +
intel_tv->margin[TV_MARGIN_BOTTOM]);
I915_WRITE(TV_WIN_POS, (xpos<<16)|ypos);
I915_WRITE(TV_WIN_SIZE, (xsize<<16)|ysize);
I915_WRITE(pipeconf_reg, pipeconf);
I915_WRITE(dspcntr_reg, dspcntr);
intel_flush_primary_plane(dev_priv, intel_crtc->plane);
}
j = 0; j = 0;
for (i = 0; i < 60; i++) for (i = 0; i < 60; i++)