phy: for 4.8 -rc
*) Fix to get host-only mode working in sun4i *) Fix a compilation error because of missing header file *) Other minor fixes Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJXtwY5AAoJEA5ceFyATYLZkzgP/j6isWrCorGIAlWA2CZB5se/ /jUDNT9rEDRni1gwLNvVL7qi+1lVuqrddphv+1/TtM0PT2QeFCH3KkBfiGFJT/b8 fUIHaEC8ro27zg0dZAo3IbCnmOdHmBM0qsEO4yQuxNlhx1qYd0LDP8jqVfci6/CO E0BS+N4Q2DG/O7Thm9l3Qj/ikb6Ry7QZNykot/oJldlOoi1vpDHOFQtTBAaObVEz jhsXus8GdfkixPtdka18qoTDiToWtVKjJES0cngX37HwQ3Bt6tGMxwtpv90Icp5o wHpgrJSbXsX7SzRobkrQwllpOMunb8SaFwFwVTlo7Azxh+K39JlNMfci6KlzEi1i takezcw4OV2Ot/HmSXhhiTg7Qj6vSM7SVM9yYe/DoF8qQYuo1qZ7W9UfE+88bEe+ kgXgMT9bm2a3JyS8xEaj9qQua5ZMqjt9xwiSxaaDqx9Y0qBIj8TGXJRbb61Jai8h Cfw6yxUsKRrICW1nh9L8DZSZ4iA5GoZMjuf8GWtoD+rVVxfhlp+iQNZUkEvqEoXO NhIl73akrNGB2HKIU824SlB/KRKBAaMMk6LJefM1pteMWLU7wgUOvdgGZExL1Q4V ygnNFoJuLKcwns/AGzfU9vZq8+jQtLRg0mI9Hdwh3Ry1HjcTfsdp1PuQXMR/phsS 34eoIK/YyxXaPX45SgJz =cK9O -----END PGP SIGNATURE----- Merge tag 'phy-for-4.8-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-linus Kishon writes: phy: for 4.8 -rc *) Fix to get host-only mode working in sun4i *) Fix a compilation error because of missing header file *) Other minor fixes Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Greg Kroah-Hartman
commit
3fa2a81e6e
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@ -367,7 +367,7 @@ static int brcm_sata_phy_init(struct phy *phy)
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rc = -ENODEV;
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};
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return 0;
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return rc;
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}
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static const struct phy_ops phy_ops = {
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@ -40,6 +40,7 @@
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#include <linux/power_supply.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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#include <linux/usb/of.h>
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#include <linux/workqueue.h>
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#define REG_ISCR 0x00
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@ -110,6 +111,7 @@ struct sun4i_usb_phy_cfg {
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struct sun4i_usb_phy_data {
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void __iomem *base;
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const struct sun4i_usb_phy_cfg *cfg;
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enum usb_dr_mode dr_mode;
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struct mutex mutex;
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struct sun4i_usb_phy {
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struct phy *phy;
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@ -120,6 +122,7 @@ struct sun4i_usb_phy_data {
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bool regulator_on;
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int index;
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} phys[MAX_PHYS];
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int first_phy;
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/* phy0 / otg related variables */
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struct extcon_dev *extcon;
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bool phy0_init;
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@ -285,16 +288,10 @@ static int sun4i_usb_phy_init(struct phy *_phy)
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sun4i_usb_phy0_update_iscr(_phy, 0, ISCR_DPDM_PULLUP_EN);
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sun4i_usb_phy0_update_iscr(_phy, 0, ISCR_ID_PULLUP_EN);
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if (data->id_det_gpio) {
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/* OTG mode, force ISCR and cable state updates */
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data->id_det = -1;
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data->vbus_det = -1;
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queue_delayed_work(system_wq, &data->detect, 0);
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} else {
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/* Host only mode */
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sun4i_usb_phy0_set_id_detect(_phy, 0);
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sun4i_usb_phy0_set_vbus_detect(_phy, 1);
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}
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/* Force ISCR and cable state updates */
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data->id_det = -1;
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data->vbus_det = -1;
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queue_delayed_work(system_wq, &data->detect, 0);
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}
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return 0;
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@ -319,6 +316,19 @@ static int sun4i_usb_phy_exit(struct phy *_phy)
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return 0;
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}
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static int sun4i_usb_phy0_get_id_det(struct sun4i_usb_phy_data *data)
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{
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switch (data->dr_mode) {
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case USB_DR_MODE_OTG:
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return gpiod_get_value_cansleep(data->id_det_gpio);
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case USB_DR_MODE_HOST:
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return 0;
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case USB_DR_MODE_PERIPHERAL:
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default:
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return 1;
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}
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}
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static int sun4i_usb_phy0_get_vbus_det(struct sun4i_usb_phy_data *data)
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{
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if (data->vbus_det_gpio)
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@ -432,7 +442,10 @@ static void sun4i_usb_phy0_id_vbus_det_scan(struct work_struct *work)
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struct phy *phy0 = data->phys[0].phy;
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int id_det, vbus_det, id_notify = 0, vbus_notify = 0;
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id_det = gpiod_get_value_cansleep(data->id_det_gpio);
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if (phy0 == NULL)
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return;
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id_det = sun4i_usb_phy0_get_id_det(data);
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vbus_det = sun4i_usb_phy0_get_vbus_det(data);
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mutex_lock(&phy0->mutex);
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@ -448,7 +461,8 @@ static void sun4i_usb_phy0_id_vbus_det_scan(struct work_struct *work)
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* without vbus detection report vbus low for long enough for
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* the musb-ip to end the current device session.
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*/
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if (!sun4i_usb_phy0_have_vbus_det(data) && id_det == 0) {
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if (data->dr_mode == USB_DR_MODE_OTG &&
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!sun4i_usb_phy0_have_vbus_det(data) && id_det == 0) {
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sun4i_usb_phy0_set_vbus_detect(phy0, 0);
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msleep(200);
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sun4i_usb_phy0_set_vbus_detect(phy0, 1);
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@ -474,7 +488,8 @@ static void sun4i_usb_phy0_id_vbus_det_scan(struct work_struct *work)
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* without vbus detection report vbus low for long enough to
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* the musb-ip to end the current host session.
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*/
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if (!sun4i_usb_phy0_have_vbus_det(data) && id_det == 1) {
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if (data->dr_mode == USB_DR_MODE_OTG &&
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!sun4i_usb_phy0_have_vbus_det(data) && id_det == 1) {
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mutex_lock(&phy0->mutex);
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sun4i_usb_phy0_set_vbus_detect(phy0, 0);
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msleep(1000);
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@ -519,7 +534,8 @@ static struct phy *sun4i_usb_phy_xlate(struct device *dev,
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{
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struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
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if (args->args[0] >= data->cfg->num_phys)
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if (args->args[0] < data->first_phy ||
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args->args[0] >= data->cfg->num_phys)
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return ERR_PTR(-ENODEV);
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return data->phys[args->args[0]].phy;
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@ -593,13 +609,17 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
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return -EPROBE_DEFER;
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}
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/* vbus_det without id_det makes no sense, and is not supported */
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if (sun4i_usb_phy0_have_vbus_det(data) && !data->id_det_gpio) {
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dev_err(dev, "usb0_id_det missing or invalid\n");
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return -ENODEV;
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}
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if (data->id_det_gpio) {
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data->dr_mode = of_usb_get_dr_mode_by_phy(np, 0);
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switch (data->dr_mode) {
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case USB_DR_MODE_OTG:
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/* otg without id_det makes no sense, and is not supported */
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if (!data->id_det_gpio) {
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dev_err(dev, "usb0_id_det missing or invalid\n");
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return -ENODEV;
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}
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/* fall through */
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case USB_DR_MODE_HOST:
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case USB_DR_MODE_PERIPHERAL:
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data->extcon = devm_extcon_dev_allocate(dev,
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sun4i_usb_phy0_cable);
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if (IS_ERR(data->extcon))
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@ -610,9 +630,13 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
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dev_err(dev, "failed to register extcon: %d\n", ret);
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return ret;
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}
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break;
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default:
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dev_info(dev, "dr_mode unknown, not registering usb phy0\n");
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data->first_phy = 1;
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}
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for (i = 0; i < data->cfg->num_phys; i++) {
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for (i = data->first_phy; i < data->cfg->num_phys; i++) {
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struct sun4i_usb_phy *phy = data->phys + i;
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char name[16];
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@ -141,9 +141,9 @@ static int sun9i_usb_phy_probe(struct platform_device *pdev)
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}
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phy->hsic_clk = devm_clk_get(dev, "hsic_12M");
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if (IS_ERR(phy->clk)) {
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if (IS_ERR(phy->hsic_clk)) {
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dev_err(dev, "failed to get hsic_12M clock\n");
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return PTR_ERR(phy->clk);
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return PTR_ERR(phy->hsic_clk);
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}
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phy->reset = devm_reset_control_get(dev, "hsic");
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@ -0,0 +1,153 @@
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/*
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* TI DaVinci DA8xx CHIPCFGx registers for syscon consumers.
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*
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* Copyright (C) 2016 David Lechner <david@lechnology.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __LINUX_MFD_DA8XX_CFGCHIP_H
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#define __LINUX_MFD_DA8XX_CFGCHIP_H
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#include <linux/bitops.h>
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/* register offset (32-bit registers) */
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#define CFGCHIP(n) ((n) * 4)
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/* CFGCHIP0 (PLL0/EDMA3_0) register bits */
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#define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
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#define CFGCHIP0_EDMA30TC1DBS(n) ((n) << 2)
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#define CFGCHIP0_EDMA30TC1DBS_MASK CFGCHIP0_EDMA30TC1DBS(0x3)
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#define CFGCHIP0_EDMA30TC1DBS_16 CFGCHIP0_EDMA30TC1DBS(0x0)
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#define CFGCHIP0_EDMA30TC1DBS_32 CFGCHIP0_EDMA30TC1DBS(0x1)
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#define CFGCHIP0_EDMA30TC1DBS_64 CFGCHIP0_EDMA30TC1DBS(0x2)
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#define CFGCHIP0_EDMA30TC0DBS(n) ((n) << 0)
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#define CFGCHIP0_EDMA30TC0DBS_MASK CFGCHIP0_EDMA30TC0DBS(0x3)
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#define CFGCHIP0_EDMA30TC0DBS_16 CFGCHIP0_EDMA30TC0DBS(0x0)
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#define CFGCHIP0_EDMA30TC0DBS_32 CFGCHIP0_EDMA30TC0DBS(0x1)
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#define CFGCHIP0_EDMA30TC0DBS_64 CFGCHIP0_EDMA30TC0DBS(0x2)
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/* CFGCHIP1 (eCAP/HPI/EDMA3_1/eHRPWM TBCLK/McASP0 AMUTEIN) register bits */
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#define CFGCHIP1_CAP2SRC(n) ((n) << 27)
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#define CFGCHIP1_CAP2SRC_MASK CFGCHIP1_CAP2SRC(0x1f)
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#define CFGCHIP1_CAP2SRC_ECAP_PIN CFGCHIP1_CAP2SRC(0x0)
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#define CFGCHIP1_CAP2SRC_MCASP0_TX CFGCHIP1_CAP2SRC(0x1)
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#define CFGCHIP1_CAP2SRC_MCASP0_RX CFGCHIP1_CAP2SRC(0x2)
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#define CFGCHIP1_CAP2SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP2SRC(0x7)
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#define CFGCHIP1_CAP2SRC_EMAC_C0_RX CFGCHIP1_CAP2SRC(0x8)
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#define CFGCHIP1_CAP2SRC_EMAC_C0_TX CFGCHIP1_CAP2SRC(0x9)
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#define CFGCHIP1_CAP2SRC_EMAC_C0_MISC CFGCHIP1_CAP2SRC(0xa)
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#define CFGCHIP1_CAP2SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP2SRC(0xb)
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#define CFGCHIP1_CAP2SRC_EMAC_C1_RX CFGCHIP1_CAP2SRC(0xc)
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#define CFGCHIP1_CAP2SRC_EMAC_C1_TX CFGCHIP1_CAP2SRC(0xd)
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#define CFGCHIP1_CAP2SRC_EMAC_C1_MISC CFGCHIP1_CAP2SRC(0xe)
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#define CFGCHIP1_CAP2SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP2SRC(0xf)
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#define CFGCHIP1_CAP2SRC_EMAC_C2_RX CFGCHIP1_CAP2SRC(0x10)
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#define CFGCHIP1_CAP2SRC_EMAC_C2_TX CFGCHIP1_CAP2SRC(0x11)
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#define CFGCHIP1_CAP2SRC_EMAC_C2_MISC CFGCHIP1_CAP2SRC(0x12)
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#define CFGCHIP1_CAP1SRC(n) ((n) << 22)
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#define CFGCHIP1_CAP1SRC_MASK CFGCHIP1_CAP1SRC(0x1f)
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#define CFGCHIP1_CAP1SRC_ECAP_PIN CFGCHIP1_CAP1SRC(0x0)
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#define CFGCHIP1_CAP1SRC_MCASP0_TX CFGCHIP1_CAP1SRC(0x1)
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#define CFGCHIP1_CAP1SRC_MCASP0_RX CFGCHIP1_CAP1SRC(0x2)
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#define CFGCHIP1_CAP1SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP1SRC(0x7)
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#define CFGCHIP1_CAP1SRC_EMAC_C0_RX CFGCHIP1_CAP1SRC(0x8)
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#define CFGCHIP1_CAP1SRC_EMAC_C0_TX CFGCHIP1_CAP1SRC(0x9)
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#define CFGCHIP1_CAP1SRC_EMAC_C0_MISC CFGCHIP1_CAP1SRC(0xa)
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#define CFGCHIP1_CAP1SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP1SRC(0xb)
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#define CFGCHIP1_CAP1SRC_EMAC_C1_RX CFGCHIP1_CAP1SRC(0xc)
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#define CFGCHIP1_CAP1SRC_EMAC_C1_TX CFGCHIP1_CAP1SRC(0xd)
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#define CFGCHIP1_CAP1SRC_EMAC_C1_MISC CFGCHIP1_CAP1SRC(0xe)
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#define CFGCHIP1_CAP1SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP1SRC(0xf)
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#define CFGCHIP1_CAP1SRC_EMAC_C2_RX CFGCHIP1_CAP1SRC(0x10)
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#define CFGCHIP1_CAP1SRC_EMAC_C2_TX CFGCHIP1_CAP1SRC(0x11)
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#define CFGCHIP1_CAP1SRC_EMAC_C2_MISC CFGCHIP1_CAP1SRC(0x12)
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#define CFGCHIP1_CAP0SRC(n) ((n) << 17)
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#define CFGCHIP1_CAP0SRC_MASK CFGCHIP1_CAP0SRC(0x1f)
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#define CFGCHIP1_CAP0SRC_ECAP_PIN CFGCHIP1_CAP0SRC(0x0)
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#define CFGCHIP1_CAP0SRC_MCASP0_TX CFGCHIP1_CAP0SRC(0x1)
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#define CFGCHIP1_CAP0SRC_MCASP0_RX CFGCHIP1_CAP0SRC(0x2)
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#define CFGCHIP1_CAP0SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP0SRC(0x7)
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#define CFGCHIP1_CAP0SRC_EMAC_C0_RX CFGCHIP1_CAP0SRC(0x8)
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#define CFGCHIP1_CAP0SRC_EMAC_C0_TX CFGCHIP1_CAP0SRC(0x9)
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#define CFGCHIP1_CAP0SRC_EMAC_C0_MISC CFGCHIP1_CAP0SRC(0xa)
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#define CFGCHIP1_CAP0SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP0SRC(0xb)
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#define CFGCHIP1_CAP0SRC_EMAC_C1_RX CFGCHIP1_CAP0SRC(0xc)
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#define CFGCHIP1_CAP0SRC_EMAC_C1_TX CFGCHIP1_CAP0SRC(0xd)
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#define CFGCHIP1_CAP0SRC_EMAC_C1_MISC CFGCHIP1_CAP0SRC(0xe)
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#define CFGCHIP1_CAP0SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP0SRC(0xf)
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#define CFGCHIP1_CAP0SRC_EMAC_C2_RX CFGCHIP1_CAP0SRC(0x10)
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#define CFGCHIP1_CAP0SRC_EMAC_C2_TX CFGCHIP1_CAP0SRC(0x11)
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#define CFGCHIP1_CAP0SRC_EMAC_C2_MISC CFGCHIP1_CAP0SRC(0x12)
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#define CFGCHIP1_HPIBYTEAD BIT(16)
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#define CFGCHIP1_HPIENA BIT(15)
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#define CFGCHIP0_EDMA31TC0DBS(n) ((n) << 13)
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#define CFGCHIP0_EDMA31TC0DBS_MASK CFGCHIP0_EDMA31TC0DBS(0x3)
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#define CFGCHIP0_EDMA31TC0DBS_16 CFGCHIP0_EDMA31TC0DBS(0x0)
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#define CFGCHIP0_EDMA31TC0DBS_32 CFGCHIP0_EDMA31TC0DBS(0x1)
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#define CFGCHIP0_EDMA31TC0DBS_64 CFGCHIP0_EDMA31TC0DBS(0x2)
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#define CFGCHIP1_TBCLKSYNC BIT(12)
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#define CFGCHIP1_AMUTESEL0(n) ((n) << 0)
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#define CFGCHIP1_AMUTESEL0_MASK CFGCHIP1_AMUTESEL0(0xf)
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#define CFGCHIP1_AMUTESEL0_LOW CFGCHIP1_AMUTESEL0(0x0)
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#define CFGCHIP1_AMUTESEL0_BANK_0 CFGCHIP1_AMUTESEL0(0x1)
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#define CFGCHIP1_AMUTESEL0_BANK_1 CFGCHIP1_AMUTESEL0(0x2)
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#define CFGCHIP1_AMUTESEL0_BANK_2 CFGCHIP1_AMUTESEL0(0x3)
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#define CFGCHIP1_AMUTESEL0_BANK_3 CFGCHIP1_AMUTESEL0(0x4)
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#define CFGCHIP1_AMUTESEL0_BANK_4 CFGCHIP1_AMUTESEL0(0x5)
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#define CFGCHIP1_AMUTESEL0_BANK_5 CFGCHIP1_AMUTESEL0(0x6)
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#define CFGCHIP1_AMUTESEL0_BANK_6 CFGCHIP1_AMUTESEL0(0x7)
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#define CFGCHIP1_AMUTESEL0_BANK_7 CFGCHIP1_AMUTESEL0(0x8)
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/* CFGCHIP2 (USB PHY) register bits */
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#define CFGCHIP2_PHYCLKGD BIT(17)
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#define CFGCHIP2_VBUSSENSE BIT(16)
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#define CFGCHIP2_RESET BIT(15)
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#define CFGCHIP2_OTGMODE(n) ((n) << 13)
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#define CFGCHIP2_OTGMODE_MASK CFGCHIP2_OTGMODE(0x3)
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#define CFGCHIP2_OTGMODE_NO_OVERRIDE CFGCHIP2_OTGMODE(0x0)
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#define CFGCHIP2_OTGMODE_FORCE_HOST CFGCHIP2_OTGMODE(0x1)
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#define CFGCHIP2_OTGMODE_FORCE_DEVICE CFGCHIP2_OTGMODE(0x2)
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#define CFGCHIP2_OTGMODE_FORCE_HOST_VBUS_LOW CFGCHIP2_OTGMODE(0x3)
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#define CFGCHIP2_USB1PHYCLKMUX BIT(12)
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#define CFGCHIP2_USB2PHYCLKMUX BIT(11)
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#define CFGCHIP2_PHYPWRDN BIT(10)
|
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#define CFGCHIP2_OTGPWRDN BIT(9)
|
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#define CFGCHIP2_DATPOL BIT(8)
|
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#define CFGCHIP2_USB1SUSPENDM BIT(7)
|
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#define CFGCHIP2_PHY_PLLON BIT(6)
|
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#define CFGCHIP2_SESENDEN BIT(5)
|
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#define CFGCHIP2_VBDTCTEN BIT(4)
|
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#define CFGCHIP2_REFFREQ(n) ((n) << 0)
|
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#define CFGCHIP2_REFFREQ_MASK CFGCHIP2_REFFREQ(0xf)
|
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#define CFGCHIP2_REFFREQ_12MHZ CFGCHIP2_REFFREQ(0x1)
|
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#define CFGCHIP2_REFFREQ_24MHZ CFGCHIP2_REFFREQ(0x2)
|
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#define CFGCHIP2_REFFREQ_48MHZ CFGCHIP2_REFFREQ(0x3)
|
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#define CFGCHIP2_REFFREQ_19_2MHZ CFGCHIP2_REFFREQ(0x4)
|
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#define CFGCHIP2_REFFREQ_38_4MHZ CFGCHIP2_REFFREQ(0x5)
|
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#define CFGCHIP2_REFFREQ_13MHZ CFGCHIP2_REFFREQ(0x6)
|
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#define CFGCHIP2_REFFREQ_26MHZ CFGCHIP2_REFFREQ(0x7)
|
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#define CFGCHIP2_REFFREQ_20MHZ CFGCHIP2_REFFREQ(0x8)
|
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#define CFGCHIP2_REFFREQ_40MHZ CFGCHIP2_REFFREQ(0x9)
|
||||
|
||||
/* CFGCHIP3 (EMAC/uPP/PLL1/ASYNC3/PRU/DIV4.5/EMIFA) register bits */
|
||||
#define CFGCHIP3_RMII_SEL BIT(8)
|
||||
#define CFGCHIP3_UPP_TX_CLKSRC BIT(6)
|
||||
#define CFGCHIP3_PLL1_MASTER_LOCK BIT(5)
|
||||
#define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
|
||||
#define CFGCHIP3_PRUEVTSEL BIT(3)
|
||||
#define CFGCHIP3_DIV45PENA BIT(2)
|
||||
#define CFGCHIP3_EMA_CLKSRC BIT(1)
|
||||
|
||||
/* CFGCHIP4 (McASP0 AMUNTEIN) register bits */
|
||||
#define CFGCHIP4_AMUTECLR0 BIT(0)
|
||||
|
||||
#endif /* __LINUX_MFD_DA8XX_CFGCHIP_H */
|
||||
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Reference in New Issue