i2c: iproc: add polling support
Add polling support to the iProc I2C driver. Polling mode is activated when the driver fails to obtain an interrupt ID from device tree Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Signed-off-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
Rayagonda Kokatanur
Wolfram Sang
parent
682587080d
commit
3f98ad45e5
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@ -371,13 +371,98 @@ static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c)
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}
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}
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static void bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev *iproc_i2c)
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{
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struct i2c_msg *msg = iproc_i2c->msg;
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unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes;
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unsigned int i;
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u32 val;
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/* can only fill up to the FIFO size */
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tx_bytes = min_t(unsigned int, tx_bytes, M_TX_RX_FIFO_SIZE);
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for (i = 0; i < tx_bytes; i++) {
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/* start from where we left over */
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unsigned int idx = iproc_i2c->tx_bytes + i;
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val = msg->buf[idx];
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/* mark the last byte */
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if (idx == msg->len - 1) {
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val |= BIT(M_TX_WR_STATUS_SHIFT);
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if (iproc_i2c->irq) {
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u32 tmp;
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/*
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* Since this is the last byte, we should now
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* disable TX FIFO underrun interrupt
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*/
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tmp = readl(iproc_i2c->base + IE_OFFSET);
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tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT);
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writel(tmp, iproc_i2c->base + IE_OFFSET);
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}
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}
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/* load data into TX FIFO */
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writel(val, iproc_i2c->base + M_TX_OFFSET);
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}
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/* update number of transferred bytes */
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iproc_i2c->tx_bytes += tx_bytes;
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}
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static void bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev *iproc_i2c)
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{
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struct i2c_msg *msg = iproc_i2c->msg;
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u32 bytes_left, val;
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bcm_iproc_i2c_read_valid_bytes(iproc_i2c);
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bytes_left = msg->len - iproc_i2c->rx_bytes;
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if (bytes_left == 0) {
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if (iproc_i2c->irq) {
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/* finished reading all data, disable rx thld event */
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val = readl(iproc_i2c->base + IE_OFFSET);
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val &= ~BIT(IS_M_RX_THLD_SHIFT);
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writel(val, iproc_i2c->base + IE_OFFSET);
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}
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} else if (bytes_left < iproc_i2c->thld_bytes) {
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/* set bytes left as threshold */
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val = readl(iproc_i2c->base + M_FIFO_CTRL_OFFSET);
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val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
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val |= (bytes_left << M_FIFO_RX_THLD_SHIFT);
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writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
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iproc_i2c->thld_bytes = bytes_left;
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}
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/*
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* bytes_left >= iproc_i2c->thld_bytes,
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* hence no need to change the THRESHOLD SET.
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* It will remain as iproc_i2c->thld_bytes itself
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*/
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}
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static void bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev *iproc_i2c,
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u32 status)
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{
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/* TX FIFO is empty and we have more data to send */
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if (status & BIT(IS_M_TX_UNDERRUN_SHIFT))
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bcm_iproc_i2c_send(iproc_i2c);
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/* RX FIFO threshold is reached and data needs to be read out */
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if (status & BIT(IS_M_RX_THLD_SHIFT))
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bcm_iproc_i2c_read(iproc_i2c);
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/* transfer is done */
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if (status & BIT(IS_M_START_BUSY_SHIFT)) {
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iproc_i2c->xfer_is_done = 1;
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if (iproc_i2c->irq)
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complete(&iproc_i2c->done);
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}
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}
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static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data)
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{
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struct bcm_iproc_i2c_dev *iproc_i2c = data;
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u32 status = readl(iproc_i2c->base + IS_OFFSET);
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u32 tmp;
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bool ret;
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u32 sl_status = status & ISR_MASK_SLAVE;
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@ -390,76 +475,11 @@ static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data)
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}
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status &= ISR_MASK;
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if (!status)
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return IRQ_NONE;
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/* TX FIFO is empty and we have more data to send */
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if (status & BIT(IS_M_TX_UNDERRUN_SHIFT)) {
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struct i2c_msg *msg = iproc_i2c->msg;
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unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes;
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unsigned int i;
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u32 val;
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/* can only fill up to the FIFO size */
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tx_bytes = min_t(unsigned int, tx_bytes, M_TX_RX_FIFO_SIZE);
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for (i = 0; i < tx_bytes; i++) {
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/* start from where we left over */
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unsigned int idx = iproc_i2c->tx_bytes + i;
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val = msg->buf[idx];
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/* mark the last byte */
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if (idx == msg->len - 1) {
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val |= BIT(M_TX_WR_STATUS_SHIFT);
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/*
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* Since this is the last byte, we should
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* now disable TX FIFO underrun interrupt
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*/
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tmp = readl(iproc_i2c->base + IE_OFFSET);
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tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT);
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writel(tmp, iproc_i2c->base + IE_OFFSET);
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}
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/* load data into TX FIFO */
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writel(val, iproc_i2c->base + M_TX_OFFSET);
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}
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/* update number of transferred bytes */
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iproc_i2c->tx_bytes += tx_bytes;
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}
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if (status & BIT(IS_M_RX_THLD_SHIFT)) {
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struct i2c_msg *msg = iproc_i2c->msg;
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u32 bytes_left;
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bcm_iproc_i2c_read_valid_bytes(iproc_i2c);
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bytes_left = msg->len - iproc_i2c->rx_bytes;
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if (bytes_left == 0) {
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/* finished reading all data, disable rx thld event */
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tmp = readl(iproc_i2c->base + IE_OFFSET);
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tmp &= ~BIT(IS_M_RX_THLD_SHIFT);
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writel(tmp, iproc_i2c->base + IE_OFFSET);
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} else if (bytes_left < iproc_i2c->thld_bytes) {
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/* set bytes left as threshold */
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tmp = readl(iproc_i2c->base + M_FIFO_CTRL_OFFSET);
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tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
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tmp |= (bytes_left << M_FIFO_RX_THLD_SHIFT);
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writel(tmp, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
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iproc_i2c->thld_bytes = bytes_left;
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}
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/*
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* bytes_left >= iproc_i2c->thld_bytes,
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* hence no need to change the THRESHOLD SET.
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* It will remain as iproc_i2c->thld_bytes itself
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*/
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}
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if (status & BIT(IS_M_START_BUSY_SHIFT)) {
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iproc_i2c->xfer_is_done = 1;
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complete(&iproc_i2c->done);
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}
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/* process all master based events */
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bcm_iproc_i2c_process_m_event(iproc_i2c, status);
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writel(status, iproc_i2c->base + IS_OFFSET);
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return IRQ_HANDLED;
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@ -558,14 +578,71 @@ static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c,
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}
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}
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static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c,
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struct i2c_msg *msg,
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u32 cmd)
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{
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unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MSEC);
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u32 val, status;
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int ret;
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writel(cmd, iproc_i2c->base + M_CMD_OFFSET);
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if (iproc_i2c->irq) {
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time_left = wait_for_completion_timeout(&iproc_i2c->done,
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time_left);
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/* disable all interrupts */
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writel(0, iproc_i2c->base + IE_OFFSET);
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/* read it back to flush the write */
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readl(iproc_i2c->base + IE_OFFSET);
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/* make sure the interrupt handler isn't running */
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synchronize_irq(iproc_i2c->irq);
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} else { /* polling mode */
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unsigned long timeout = jiffies + time_left;
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do {
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status = readl(iproc_i2c->base + IS_OFFSET) & ISR_MASK;
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bcm_iproc_i2c_process_m_event(iproc_i2c, status);
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writel(status, iproc_i2c->base + IS_OFFSET);
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if (time_after(jiffies, timeout)) {
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time_left = 0;
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break;
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}
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cpu_relax();
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cond_resched();
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} while (!iproc_i2c->xfer_is_done);
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}
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if (!time_left && !iproc_i2c->xfer_is_done) {
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dev_err(iproc_i2c->device, "transaction timed out\n");
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/* flush both TX/RX FIFOs */
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val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
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writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
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return -ETIMEDOUT;
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}
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ret = bcm_iproc_i2c_check_status(iproc_i2c, msg);
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if (ret) {
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/* flush both TX/RX FIFOs */
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val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
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writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
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return ret;
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}
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return 0;
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}
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static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c,
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struct i2c_msg *msg)
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{
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int ret, i;
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int i;
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u8 addr;
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u32 val, tmp, val_intr_en;
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unsigned int tx_bytes;
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unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MSEC);
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/* check if bus is busy */
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if (!!(readl(iproc_i2c->base + M_CMD_OFFSET) &
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@ -600,7 +677,9 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c,
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}
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/* mark as incomplete before starting the transaction */
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reinit_completion(&iproc_i2c->done);
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if (iproc_i2c->irq)
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reinit_completion(&iproc_i2c->done);
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iproc_i2c->xfer_is_done = 0;
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/*
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@ -645,39 +724,11 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c,
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} else {
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val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT);
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}
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writel(val_intr_en, iproc_i2c->base + IE_OFFSET);
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writel(val, iproc_i2c->base + M_CMD_OFFSET);
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time_left = wait_for_completion_timeout(&iproc_i2c->done, time_left);
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if (iproc_i2c->irq)
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writel(val_intr_en, iproc_i2c->base + IE_OFFSET);
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/* disable all interrupts */
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writel(0, iproc_i2c->base + IE_OFFSET);
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/* read it back to flush the write */
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readl(iproc_i2c->base + IE_OFFSET);
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/* make sure the interrupt handler isn't running */
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synchronize_irq(iproc_i2c->irq);
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if (!time_left && !iproc_i2c->xfer_is_done) {
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dev_err(iproc_i2c->device, "transaction timed out\n");
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/* flush FIFOs */
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val = (1 << M_FIFO_RX_FLUSH_SHIFT) |
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(1 << M_FIFO_TX_FLUSH_SHIFT);
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writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
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return -ETIMEDOUT;
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}
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ret = bcm_iproc_i2c_check_status(iproc_i2c, msg);
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if (ret) {
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/* flush both TX/RX FIFOs */
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val = (1 << M_FIFO_RX_FLUSH_SHIFT) |
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(1 << M_FIFO_TX_FLUSH_SHIFT);
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writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
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return ret;
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}
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return 0;
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return bcm_iproc_i2c_xfer_wait(iproc_i2c, msg, val);
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}
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static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter,
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@ -779,17 +830,20 @@ static int bcm_iproc_i2c_probe(struct platform_device *pdev)
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return ret;
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irq = platform_get_irq(pdev, 0);
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if (irq <= 0) {
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dev_err(iproc_i2c->device, "no irq resource\n");
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return irq;
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}
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iproc_i2c->irq = irq;
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if (irq > 0) {
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ret = devm_request_irq(iproc_i2c->device, irq,
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bcm_iproc_i2c_isr, 0, pdev->name,
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iproc_i2c);
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if (ret < 0) {
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dev_err(iproc_i2c->device,
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"unable to request irq %i\n", irq);
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return ret;
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}
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ret = devm_request_irq(iproc_i2c->device, irq, bcm_iproc_i2c_isr, 0,
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pdev->name, iproc_i2c);
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if (ret < 0) {
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dev_err(iproc_i2c->device, "unable to request irq %i\n", irq);
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return ret;
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iproc_i2c->irq = irq;
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} else {
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dev_warn(iproc_i2c->device,
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"no irq resource, falling back to poll mode\n");
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}
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bcm_iproc_i2c_enable_disable(iproc_i2c, true);
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@ -809,10 +863,15 @@ static int bcm_iproc_i2c_remove(struct platform_device *pdev)
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{
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struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev);
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/* make sure there's no pending interrupt when we remove the adapter */
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writel(0, iproc_i2c->base + IE_OFFSET);
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readl(iproc_i2c->base + IE_OFFSET);
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synchronize_irq(iproc_i2c->irq);
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if (iproc_i2c->irq) {
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/*
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* Make sure there's no pending interrupt when we remove the
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* adapter
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*/
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writel(0, iproc_i2c->base + IE_OFFSET);
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readl(iproc_i2c->base + IE_OFFSET);
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synchronize_irq(iproc_i2c->irq);
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}
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i2c_del_adapter(&iproc_i2c->adapter);
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bcm_iproc_i2c_enable_disable(iproc_i2c, false);
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@ -826,10 +885,15 @@ static int bcm_iproc_i2c_suspend(struct device *dev)
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{
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struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
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/* make sure there's no pending interrupt when we go into suspend */
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writel(0, iproc_i2c->base + IE_OFFSET);
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readl(iproc_i2c->base + IE_OFFSET);
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synchronize_irq(iproc_i2c->irq);
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if (iproc_i2c->irq) {
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/*
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* Make sure there's no pending interrupt when we go into
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* suspend
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*/
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writel(0, iproc_i2c->base + IE_OFFSET);
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readl(iproc_i2c->base + IE_OFFSET);
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synchronize_irq(iproc_i2c->irq);
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}
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/* now disable the controller */
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bcm_iproc_i2c_enable_disable(iproc_i2c, false);
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