drm/i915: Preserve the FDI line reversal override bit on CPT
The FDI link has supported link reversal to make the PCB layout engineer's life easier for quite a while and we have always presered this bit as we programmed FDI_RX_CTL with a read/modify/write sequence. We're trying to take a bit more control over what the BIOS leaves in various register and with the introduction of DDI, started to program FDI_RX_CTL fully. There's a fused bit to indicate DMI link reversal and FDI defaults to mirroring that configuration. We have a bit to override that behaviour that we need to preserve from the BIOS. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: stable@vger.kernel.org Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -1040,7 +1040,7 @@ typedef struct drm_i915_private {
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bool hw_contexts_disabled;
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uint32_t hw_context_size;
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bool fdi_rx_polarity_reversed;
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u32 fdi_rx_config;
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struct i915_suspend_saved_registers regfile;
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@ -3911,7 +3911,7 @@
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#define FDI_10BPC (1<<16)
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#define FDI_6BPC (2<<16)
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#define FDI_12BPC (3<<16)
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#define FDI_LINK_REVERSE_OVERWRITE (1<<15)
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#define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15)
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#define FDI_DMI_LINK_REVERSE_MASK (1<<14)
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#define FDI_RX_PLL_ENABLE (1<<13)
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#define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
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@ -801,10 +801,14 @@ void intel_crt_init(struct drm_device *dev)
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dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
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/*
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* TODO: find a proper way to discover whether we need to set the
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* polarity reversal bit or not, instead of relying on the BIOS.
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* TODO: find a proper way to discover whether we need to set the the
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* polarity and link reversal bits or not, instead of relying on the
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* BIOS.
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*/
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if (HAS_PCH_LPT(dev))
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dev_priv->fdi_rx_polarity_reversed =
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!!(I915_READ(_FDI_RXA_CTL) & FDI_RX_POLARITY_REVERSED_LPT);
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if (HAS_PCH_LPT(dev)) {
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u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
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FDI_RX_LINK_REVERSAL_OVERRIDE;
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dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config;
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}
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}
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@ -180,10 +180,8 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
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FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
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/* Enable the PCH Receiver FDI PLL */
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rx_ctl_val = FDI_RX_PLL_ENABLE | FDI_RX_ENHANCE_FRAME_ENABLE |
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((intel_crtc->fdi_lanes - 1) << 19);
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if (dev_priv->fdi_rx_polarity_reversed)
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rx_ctl_val |= FDI_RX_POLARITY_REVERSED_LPT;
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rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
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FDI_RX_PLL_ENABLE | ((intel_crtc->fdi_lanes - 1) << 19);
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I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
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POSTING_READ(_FDI_RXA_CTL);
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udelay(220);
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