x86/mce/amd, edac: Remove report_gart_errors
... because no one should be interested in spurious MCEs anyway. Make the filtering unconditional and move it to amd_filter_mce(). Signed-off-by: Borislav Petkov <bp@suse.de> Tested-by: Tony Luck <tony.luck@intel.com> Link: https://lkml.kernel.org/r/20200407163414.18058-2-bp@alien8.de
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@ -127,6 +127,8 @@
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#define MSR_AMD64_SMCA_MCx_DEADDR(x) (MSR_AMD64_SMCA_MC0_DEADDR + 0x10*(x))
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#define MSR_AMD64_SMCA_MCx_MISCy(x, y) ((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x)))
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#define XEC(x, mask) (((x) >> 16) & mask)
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/*
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* This structure contains all data related to the MCE log. Also
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* carries a signature to make it easier to find from external
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@ -347,5 +349,4 @@ umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { return
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#endif
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static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_amd_feature_init(c); }
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#endif /* _ASM_X86_MCE_H */
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@ -577,14 +577,19 @@ bool amd_filter_mce(struct mce *m)
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{
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enum smca_bank_types bank_type = smca_get_bank_type(m->bank);
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struct cpuinfo_x86 *c = &boot_cpu_data;
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u8 xec = (m->status >> 16) & 0x3F;
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/* See Family 17h Models 10h-2Fh Erratum #1114. */
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if (c->x86 == 0x17 &&
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c->x86_model >= 0x10 && c->x86_model <= 0x2F &&
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bank_type == SMCA_IF && xec == 10)
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bank_type == SMCA_IF && XEC(m->status, 0x3f) == 10)
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return true;
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/* NB GART TLB error reporting is disabled by default. */
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if (c->x86 < 0x17) {
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if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5)
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return true;
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}
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return false;
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}
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@ -4,9 +4,6 @@
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static struct edac_pci_ctl_info *pci_ctl;
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static int report_gart_errors;
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module_param(report_gart_errors, int, 0644);
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/*
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* Set by command line parameter. If BIOS has enabled the ECC, this override is
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* cleared to prevent re-enabling the hardware by this driver.
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@ -3681,9 +3678,6 @@ static int __init amd64_edac_init(void)
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}
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/* register stuff with EDAC MCE */
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if (report_gart_errors)
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amd_report_gart_errors(true);
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if (boot_cpu_data.x86 >= 0x17)
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amd_register_ecc_decoder(decode_umc_error);
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else
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@ -3718,8 +3712,6 @@ static void __exit amd64_edac_exit(void)
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edac_pci_release_generic_ctl(pci_ctl);
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/* unregister from EDAC MCE */
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amd_report_gart_errors(false);
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if (boot_cpu_data.x86 >= 0x17)
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amd_unregister_ecc_decoder(decode_umc_error);
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else
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@ -10,15 +10,8 @@ static struct amd_decoder_ops fam_ops;
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static u8 xec_mask = 0xf;
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static bool report_gart_errors;
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static void (*decode_dram_ecc)(int node_id, struct mce *m);
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void amd_report_gart_errors(bool v)
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{
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report_gart_errors = v;
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}
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EXPORT_SYMBOL_GPL(amd_report_gart_errors);
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void amd_register_ecc_decoder(void (*f)(int, struct mce *))
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{
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decode_dram_ecc = f;
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@ -1030,20 +1023,6 @@ static inline void amd_decode_err_code(u16 ec)
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pr_cont("\n");
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}
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/*
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* Filter out unwanted MCE signatures here.
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*/
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static bool ignore_mce(struct mce *m)
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{
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/*
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* NB GART TLB error reporting is disabled by default.
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*/
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if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5 && !report_gart_errors)
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return true;
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return false;
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}
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static const char *decode_error_status(struct mce *m)
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{
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if (m->status & MCI_STATUS_UC) {
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@ -1067,9 +1046,6 @@ amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
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unsigned int fam = x86_family(m->cpuid);
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int ecc;
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if (ignore_mce(m))
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return NOTIFY_STOP;
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pr_emerg(HW_ERR "%s\n", decode_error_status(m));
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pr_emerg(HW_ERR "CPU:%d (%x:%x:%x) MC%d_STATUS[%s|%s|%s|%s|%s",
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@ -7,7 +7,6 @@
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#include <asm/mce.h>
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#define EC(x) ((x) & 0xffff)
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#define XEC(x, mask) (((x) >> 16) & mask)
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#define LOW_SYNDROME(x) (((x) >> 15) & 0xff)
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#define HIGH_SYNDROME(x) (((x) >> 24) & 0xff)
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@ -77,7 +76,6 @@ struct amd_decoder_ops {
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bool (*mc2_mce)(u16, u8);
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};
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void amd_report_gart_errors(bool);
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void amd_register_ecc_decoder(void (*f)(int, struct mce *));
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void amd_unregister_ecc_decoder(void (*f)(int, struct mce *));
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