Add NetXen 1G/10G ethernet driver.
Signed-off-by: Amit S. Kale <amitkale@netxen.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Amit S. Kale
Jeff Garzik
parent
f3d1fca3eb
commit
3d396eb17e
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@ -2132,6 +2132,13 @@ L: netdev@vger.kernel.org
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T: git kernel.org:/pub/scm/linux/kernel/git/linville/wireless-2.6.git
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S: Maintained
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NETXEN (1/10) GbE SUPPORT
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P: Amit S. Kale
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M: amitkale@netxen.com
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L: netdev@vger.kernel.org
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W: http://www.netxen.com
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S: Supported
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IPVS
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P: Wensong Zhang
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M: wensong@linux-vs.org
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@ -2447,6 +2447,11 @@ config MYRI10GE
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<file:Documentation/networking/net-modules.txt>. The module
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will be called myri10ge.
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config NETXEN_NIC
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tristate "NetXen Multi port (1/10) Gigabit Ethernet NIC"
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help
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This enables the support for NetXen's Gigabit Ethernet card.
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endmenu
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source "drivers/net/tokenring/Kconfig"
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@ -213,3 +213,4 @@ obj-$(CONFIG_NETCONSOLE) += netconsole.o
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obj-$(CONFIG_FS_ENET) += fs_enet/
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obj-$(CONFIG_NETXEN_NIC) += netxen/
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@ -0,0 +1,35 @@
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# Copyright (C) 2003 - 2006 NetXen, Inc.
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# All rights reserved.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License
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# as published by the Free Software Foundation; either version 2
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# of the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful, but
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# WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place - Suite 330, Boston,
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# MA 02111-1307, USA.
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#
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# The full GNU General Public License is included in this distribution
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# in the file called LICENSE.
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#
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# Contact Information:
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# info@netxen.com
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# NetXen,
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# 3965 Freedom Circle, Fourth floor,
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# Santa Clara, CA 95054
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#
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# Makefile for the NetXen NIC Driver
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#
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obj-$(CONFIG_NETXEN_NIC) := netxen_nic.o
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netxen_nic-y := netxen_nic_hw.o netxen_nic_main.o netxen_nic_init.o \
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netxen_nic_isr.o netxen_nic_ethtool.o netxen_nic_niu.o
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@ -0,0 +1,910 @@
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/*
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* Copyright (C) 2003 - 2006 NetXen, Inc.
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston,
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* MA 02111-1307, USA.
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*
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.
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*
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* Contact Information:
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* info@netxen.com
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* NetXen,
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* 3965 Freedom Circle, Fourth floor,
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* Santa Clara, CA 95054
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*/
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#ifndef _NETXEN_NIC_H_
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#define _NETXEN_NIC_H_
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/compiler.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/pci.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/ip.h>
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#include <linux/in.h>
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#include <linux/tcp.h>
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#include <linux/skbuff.h>
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#include <linux/version.h>
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#include <linux/ethtool.h>
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#include <linux/mii.h>
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#include <linux/interrupt.h>
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#include <linux/timer.h>
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#include <linux/mm.h>
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#include <linux/mman.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/byteorder.h>
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#include <asm/uaccess.h>
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#include <asm/pgtable.h>
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#include "netxen_nic_hw.h"
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#define NETXEN_NIC_BUILD_NO "232"
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#define _NETXEN_NIC_LINUX_MAJOR 2
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#define _NETXEN_NIC_LINUX_MINOR 3
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#define _NETXEN_NIC_LINUX_SUBVERSION 57
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#define NETXEN_NIC_LINUX_VERSIONID "2.3.57"
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#define NETXEN_NIC_FW_VERSIONID "2.3.57"
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#define RCV_DESC_RINGSIZE \
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(sizeof(struct rcv_desc) * adapter->max_rx_desc_count)
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#define STATUS_DESC_RINGSIZE \
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(sizeof(struct status_desc)* adapter->max_rx_desc_count)
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#define TX_RINGSIZE \
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(sizeof(struct netxen_cmd_buffer) * adapter->max_tx_desc_count)
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#define RCV_BUFFSIZE \
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(sizeof(struct netxen_rx_buffer) * rcv_desc->max_rx_desc_count)
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#define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
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#define NETXEN_NETDEV_STATUS 0x1
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#define ADDR_IN_WINDOW1(off) \
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((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
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/*
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* normalize a 64MB crb address to 32MB PCI window
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* To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
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*/
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#define NETXEN_CRB_NORMALIZE(adapter, reg) \
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((adapter)->ahw.pci_base + (reg) \
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- NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
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#define MAX_RX_BUFFER_LENGTH 2000
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#define MAX_RX_JUMBO_BUFFER_LENGTH 9046
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#define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - NET_IP_ALIGN)
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#define RX_JUMBO_DMA_MAP_LEN \
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(MAX_RX_JUMBO_BUFFER_LENGTH - NET_IP_ALIGN)
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#define NETXEN_ROM_ROUNDUP 0x80000000ULL
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/*
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* Maximum number of ring contexts
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*/
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#define MAX_RING_CTX 1
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/* Opcodes to be used with the commands */
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enum {
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TX_ETHER_PKT = 0x01,
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/* The following opcodes are for IP checksum */
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TX_TCP_PKT,
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TX_UDP_PKT,
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TX_IP_PKT,
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TX_TCP_LSO,
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TX_IPSEC,
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TX_IPSEC_CMD
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};
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/* The following opcodes are for internal consumption. */
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#define NETXEN_CONTROL_OP 0x10
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#define PEGNET_REQUEST 0x11
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#define MAX_NUM_CARDS 4
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#define MAX_BUFFERS_PER_CMD 32
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/*
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* Following are the states of the Phantom. Phantom will set them and
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* Host will read to check if the fields are correct.
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*/
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#define PHAN_INITIALIZE_START 0xff00
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#define PHAN_INITIALIZE_FAILED 0xffff
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#define PHAN_INITIALIZE_COMPLETE 0xff01
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/* Host writes the following to notify that it has done the init-handshake */
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#define PHAN_INITIALIZE_ACK 0xf00f
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#define NUM_RCV_DESC_RINGS 2 /* No of Rcv Descriptor contexts */
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/* descriptor types */
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#define RCV_DESC_NORMAL 0x01
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#define RCV_DESC_JUMBO 0x02
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#define RCV_DESC_NORMAL_CTXID 0
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#define RCV_DESC_JUMBO_CTXID 1
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#define RCV_DESC_TYPE(ID) \
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((ID == RCV_DESC_JUMBO_CTXID) ? RCV_DESC_JUMBO : RCV_DESC_NORMAL)
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#define MAX_CMD_DESCRIPTORS 1024
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#define MAX_RCV_DESCRIPTORS 32768
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#define MAX_JUMBO_RCV_DESCRIPTORS 1024
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#define MAX_RCVSTATUS_DESCRIPTORS MAX_RCV_DESCRIPTORS
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#define MAX_JUMBO_RCV_DESC MAX_JUMBO_RCV_DESCRIPTORS
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#define MAX_RCV_DESC MAX_RCV_DESCRIPTORS
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#define MAX_RCVSTATUS_DESC MAX_RCV_DESCRIPTORS
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#define NUM_RCV_DESC (MAX_RCV_DESC + MAX_JUMBO_RCV_DESCRIPTORS)
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#define MAX_EPG_DESCRIPTORS (MAX_CMD_DESCRIPTORS * 8)
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#define MIN_TX_COUNT 4096
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#define MIN_RX_COUNT 4096
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#define MAX_FRAME_SIZE 0x10000 /* 64K MAX size for LSO */
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#define PHAN_PEG_RCV_INITIALIZED 0xff01
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#define PHAN_PEG_RCV_START_INITIALIZE 0xff00
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#define get_next_index(index, length) \
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(((index) + 1) & ((length) - 1))
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#define get_index_range(index,length,count) \
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(((index) + (count)) & ((length) - 1))
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/*
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* Following data structures describe the descriptors that will be used.
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* Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
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* we are doing LSO (above the 1500 size packet) only.
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*/
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/*
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* The size of reference handle been changed to 16 bits to pass the MSS fields
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* for the LSO packet
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*/
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#define FLAGS_CHECKSUM_ENABLED 0x01
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#define FLAGS_LSO_ENABLED 0x02
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#define FLAGS_IPSEC_SA_ADD 0x04
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#define FLAGS_IPSEC_SA_DELETE 0x08
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#define FLAGS_VLAN_TAGGED 0x10
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#define CMD_DESC_TOTAL_LENGTH(cmd_desc) \
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((cmd_desc)->length_tcp_hdr & 0x00FFFFFF)
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#define CMD_DESC_TCP_HDR_OFFSET(cmd_desc) \
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(((cmd_desc)->length_tcp_hdr >> 24) & 0x0FF)
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#define CMD_DESC_PORT(cmd_desc) ((cmd_desc)->port_ctxid & 0x0F)
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#define CMD_DESC_CTX_ID(cmd_desc) (((cmd_desc)->port_ctxid >> 4) & 0x0F)
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#define CMD_DESC_TOTAL_LENGTH_WRT(cmd_desc, var) \
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((cmd_desc)->length_tcp_hdr |= ((var) & 0x00FFFFFF))
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#define CMD_DESC_TCP_HDR_OFFSET_WRT(cmd_desc, var) \
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((cmd_desc)->length_tcp_hdr |= (((var) << 24) & 0xFF000000))
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#define CMD_DESC_PORT_WRT(cmd_desc, var) \
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((cmd_desc)->port_ctxid |= ((var) & 0x0F))
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struct cmd_desc_type0 {
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u64 netxen_next; /* for fragments handled by Phantom */
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union {
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struct {
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u32 addr_low_part2;
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u32 addr_high_part2;
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};
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u64 addr_buffer2;
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};
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/* Bit pattern: 0-23 total length, 24-32 tcp header offset */
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u32 length_tcp_hdr;
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u8 ip_hdr_offset; /* For LSO only */
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u8 num_of_buffers; /* total number of segments */
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u8 flags; /* as defined above */
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u8 opcode;
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u16 reference_handle; /* changed to u16 to add mss */
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u16 mss; /* passed by NDIS_PACKET for LSO */
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/* Bit pattern 0-3 port, 0-3 ctx id */
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u8 port_ctxid;
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u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
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u16 conn_id; /* IPSec offoad only */
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union {
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struct {
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u32 addr_low_part3;
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u32 addr_high_part3;
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};
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u64 addr_buffer3;
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};
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union {
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struct {
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u32 addr_low_part1;
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u32 addr_high_part1;
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};
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u64 addr_buffer1;
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};
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u16 buffer1_length;
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u16 buffer2_length;
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u16 buffer3_length;
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u16 buffer4_length;
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union {
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struct {
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u32 addr_low_part4;
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u32 addr_high_part4;
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};
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u64 addr_buffer4;
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};
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} __attribute__ ((aligned(64)));
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/* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
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struct rcv_desc {
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u16 reference_handle;
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u16 reserved;
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u32 buffer_length; /* allocated buffer length (usually 2K) */
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u64 addr_buffer;
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};
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/* opcode field in status_desc */
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#define RCV_NIC_PKT (0xA)
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#define STATUS_NIC_PKT ((RCV_NIC_PKT) << 12)
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/* for status field in status_desc */
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#define STATUS_NEED_CKSUM (1)
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#define STATUS_CKSUM_OK (2)
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/* owner bits of status_desc */
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#define STATUS_OWNER_HOST (0x1)
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#define STATUS_OWNER_PHANTOM (0x2)
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#define NETXEN_PROT_IP (1)
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#define NETXEN_PROT_UNKNOWN (0)
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/* Note: sizeof(status_desc) should always be a mutliple of 2 */
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#define STATUS_DESC_PORT(status_desc) \
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((status_desc)->port_status_type_op & 0x0F)
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#define STATUS_DESC_STATUS(status_desc) \
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(((status_desc)->port_status_type_op >> 4) & 0x0F)
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#define STATUS_DESC_TYPE(status_desc) \
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(((status_desc)->port_status_type_op >> 8) & 0x0F)
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#define STATUS_DESC_OPCODE(status_desc) \
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(((status_desc)->port_status_type_op >> 12) & 0x0F)
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struct status_desc {
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/* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-15 opcode */
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u16 port_status_type_op;
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u16 total_length; /* NIC mode */
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u16 reference_handle; /* handle for the associated packet */
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/* Bit pattern: 0-1 owner, 2-5 protocol */
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u16 owner; /* Owner of the descriptor */
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} __attribute__ ((aligned(8)));
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enum {
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NETXEN_RCV_PEG_0 = 0,
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NETXEN_RCV_PEG_1
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};
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/* The version of the main data structure */
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#define NETXEN_BDINFO_VERSION 1
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/* Magic number to let user know flash is programmed */
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#define NETXEN_BDINFO_MAGIC 0x12345678
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/* Max number of Gig ports on a Phantom board */
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#define NETXEN_MAX_PORTS 4
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typedef enum {
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NETXEN_BRDTYPE_P1_BD = 0x0000,
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NETXEN_BRDTYPE_P1_SB = 0x0001,
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NETXEN_BRDTYPE_P1_SMAX = 0x0002,
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NETXEN_BRDTYPE_P1_SOCK = 0x0003,
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NETXEN_BRDTYPE_P2_SOCK_31 = 0x0008,
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NETXEN_BRDTYPE_P2_SOCK_35 = 0x0009,
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NETXEN_BRDTYPE_P2_SB35_4G = 0x000a,
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NETXEN_BRDTYPE_P2_SB31_10G = 0x000b,
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NETXEN_BRDTYPE_P2_SB31_2G = 0x000c,
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NETXEN_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d,
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NETXEN_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e,
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NETXEN_BRDTYPE_P2_SB31_10G_CX4 = 0x000f
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} netxen_brdtype_t;
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typedef enum {
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NETXEN_BRDMFG_INVENTEC = 1
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} netxen_brdmfg;
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typedef enum {
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MEM_ORG_128Mbx4 = 0x0, /* DDR1 only */
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MEM_ORG_128Mbx8 = 0x1, /* DDR1 only */
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MEM_ORG_128Mbx16 = 0x2, /* DDR1 only */
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MEM_ORG_256Mbx4 = 0x3,
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MEM_ORG_256Mbx8 = 0x4,
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MEM_ORG_256Mbx16 = 0x5,
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MEM_ORG_512Mbx4 = 0x6,
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MEM_ORG_512Mbx8 = 0x7,
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MEM_ORG_512Mbx16 = 0x8,
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MEM_ORG_1Gbx4 = 0x9,
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MEM_ORG_1Gbx8 = 0xa,
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MEM_ORG_1Gbx16 = 0xb,
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MEM_ORG_2Gbx4 = 0xc,
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MEM_ORG_2Gbx8 = 0xd,
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MEM_ORG_2Gbx16 = 0xe,
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MEM_ORG_128Mbx32 = 0x10002, /* GDDR only */
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MEM_ORG_256Mbx32 = 0x10005 /* GDDR only */
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} netxen_mn_mem_org_t;
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typedef enum {
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MEM_ORG_512Kx36 = 0x0,
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MEM_ORG_1Mx36 = 0x1,
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MEM_ORG_2Mx36 = 0x2
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} netxen_sn_mem_org_t;
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typedef enum {
|
||||
MEM_DEPTH_4MB = 0x1,
|
||||
MEM_DEPTH_8MB = 0x2,
|
||||
MEM_DEPTH_16MB = 0x3,
|
||||
MEM_DEPTH_32MB = 0x4,
|
||||
MEM_DEPTH_64MB = 0x5,
|
||||
MEM_DEPTH_128MB = 0x6,
|
||||
MEM_DEPTH_256MB = 0x7,
|
||||
MEM_DEPTH_512MB = 0x8,
|
||||
MEM_DEPTH_1GB = 0x9,
|
||||
MEM_DEPTH_2GB = 0xa,
|
||||
MEM_DEPTH_4GB = 0xb,
|
||||
MEM_DEPTH_8GB = 0xc,
|
||||
MEM_DEPTH_16GB = 0xd,
|
||||
MEM_DEPTH_32GB = 0xe
|
||||
} netxen_mem_depth_t;
|
||||
|
||||
struct netxen_board_info {
|
||||
u32 header_version;
|
||||
|
||||
u32 board_mfg;
|
||||
u32 board_type;
|
||||
u32 board_num;
|
||||
u32 chip_id;
|
||||
u32 chip_minor;
|
||||
u32 chip_major;
|
||||
u32 chip_pkg;
|
||||
u32 chip_lot;
|
||||
|
||||
u32 port_mask; /* available niu ports */
|
||||
u32 peg_mask; /* available pegs */
|
||||
u32 icache_ok; /* can we run with icache? */
|
||||
u32 dcache_ok; /* can we run with dcache? */
|
||||
u32 casper_ok;
|
||||
|
||||
u32 mac_addr_lo_0;
|
||||
u32 mac_addr_lo_1;
|
||||
u32 mac_addr_lo_2;
|
||||
u32 mac_addr_lo_3;
|
||||
|
||||
/* MN-related config */
|
||||
u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */
|
||||
u32 mn_sync_shift_cclk;
|
||||
u32 mn_sync_shift_mclk;
|
||||
u32 mn_wb_en;
|
||||
u32 mn_crystal_freq; /* in MHz */
|
||||
u32 mn_speed; /* in MHz */
|
||||
u32 mn_org;
|
||||
u32 mn_depth;
|
||||
u32 mn_ranks_0; /* ranks per slot */
|
||||
u32 mn_ranks_1; /* ranks per slot */
|
||||
u32 mn_rd_latency_0;
|
||||
u32 mn_rd_latency_1;
|
||||
u32 mn_rd_latency_2;
|
||||
u32 mn_rd_latency_3;
|
||||
u32 mn_rd_latency_4;
|
||||
u32 mn_rd_latency_5;
|
||||
u32 mn_rd_latency_6;
|
||||
u32 mn_rd_latency_7;
|
||||
u32 mn_rd_latency_8;
|
||||
u32 mn_dll_val[18];
|
||||
u32 mn_mode_reg; /* MIU DDR Mode Register */
|
||||
u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */
|
||||
u32 mn_timing_0; /* MIU Memory Control Timing Rgister */
|
||||
u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */
|
||||
u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */
|
||||
|
||||
/* SN-related config */
|
||||
u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */
|
||||
u32 sn_pt_mode; /* pass through mode */
|
||||
u32 sn_ecc_en;
|
||||
u32 sn_wb_en;
|
||||
u32 sn_crystal_freq;
|
||||
u32 sn_speed;
|
||||
u32 sn_org;
|
||||
u32 sn_depth;
|
||||
u32 sn_dll_tap;
|
||||
u32 sn_rd_latency;
|
||||
|
||||
u32 mac_addr_hi_0;
|
||||
u32 mac_addr_hi_1;
|
||||
u32 mac_addr_hi_2;
|
||||
u32 mac_addr_hi_3;
|
||||
|
||||
u32 magic; /* indicates flash has been initialized */
|
||||
|
||||
u32 mn_rdimm;
|
||||
u32 mn_dll_override;
|
||||
|
||||
};
|
||||
|
||||
#define FLASH_NUM_PORTS (4)
|
||||
|
||||
struct netxen_flash_mac_addr {
|
||||
u32 flash_addr[32];
|
||||
};
|
||||
|
||||
struct netxen_user_old_info {
|
||||
u8 flash_md5[16];
|
||||
u8 crbinit_md5[16];
|
||||
u8 brdcfg_md5[16];
|
||||
/* bootloader */
|
||||
u32 bootld_version;
|
||||
u32 bootld_size;
|
||||
u8 bootld_md5[16];
|
||||
/* image */
|
||||
u32 image_version;
|
||||
u32 image_size;
|
||||
u8 image_md5[16];
|
||||
/* primary image status */
|
||||
u32 primary_status;
|
||||
u32 secondary_present;
|
||||
|
||||
/* MAC address , 4 ports */
|
||||
struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
|
||||
};
|
||||
#define FLASH_NUM_MAC_PER_PORT 32
|
||||
struct netxen_user_info {
|
||||
u8 flash_md5[16 * 64];
|
||||
/* bootloader */
|
||||
u32 bootld_version;
|
||||
u32 bootld_size;
|
||||
/* image */
|
||||
u32 image_version;
|
||||
u32 image_size;
|
||||
/* primary image status */
|
||||
u32 primary_status;
|
||||
u32 secondary_present;
|
||||
|
||||
/* MAC address , 4 ports, 32 address per port */
|
||||
u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
|
||||
u32 sub_sys_id;
|
||||
u8 serial_num[32];
|
||||
|
||||
/* Any user defined data */
|
||||
};
|
||||
|
||||
/*
|
||||
* Flash Layout - new format.
|
||||
*/
|
||||
struct netxen_new_user_info {
|
||||
u8 flash_md5[16 * 64];
|
||||
/* bootloader */
|
||||
u32 bootld_version;
|
||||
u32 bootld_size;
|
||||
/* image */
|
||||
u32 image_version;
|
||||
u32 image_size;
|
||||
/* primary image status */
|
||||
u32 primary_status;
|
||||
u32 secondary_present;
|
||||
|
||||
/* MAC address , 4 ports, 32 address per port */
|
||||
u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
|
||||
u32 sub_sys_id;
|
||||
u8 serial_num[32];
|
||||
|
||||
/* Any user defined data */
|
||||
};
|
||||
|
||||
#define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
|
||||
#define SECONDARY_IMAGE_ABSENT 0xffffffff
|
||||
#define PRIMARY_IMAGE_GOOD 0x5a5a5a5a
|
||||
#define PRIMARY_IMAGE_BAD 0xffffffff
|
||||
|
||||
/* Flash memory map */
|
||||
typedef enum {
|
||||
CRBINIT_START = 0, /* Crbinit section */
|
||||
BRDCFG_START = 0x4000, /* board config */
|
||||
INITCODE_START = 0x6000, /* pegtune code */
|
||||
BOOTLD_START = 0x10000, /* bootld */
|
||||
IMAGE_START = 0x43000, /* compressed image */
|
||||
SECONDARY_START = 0x200000, /* backup images */
|
||||
PXE_START = 0x3E0000, /* user defined region */
|
||||
USER_START = 0x3E8000, /* User defined region for new boards */
|
||||
FIXED_START = 0x3F0000 /* backup of crbinit */
|
||||
} netxen_flash_map_t;
|
||||
|
||||
#define USER_START_OLD PXE_START /* for backward compatibility */
|
||||
|
||||
#define FLASH_START (CRBINIT_START)
|
||||
#define INIT_SECTOR (0)
|
||||
#define PRIMARY_START (BOOTLD_START)
|
||||
#define FLASH_CRBINIT_SIZE (0x4000)
|
||||
#define FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info))
|
||||
#define FLASH_USER_SIZE (sizeof(netxen_user_info)/sizeof(u32))
|
||||
#define FLASH_SECONDARY_SIZE (USER_START-SECONDARY_START)
|
||||
#define NUM_PRIMARY_SECTORS (0x20)
|
||||
#define NUM_CONFIG_SECTORS (1)
|
||||
#define PFX "netxen: "
|
||||
|
||||
/* Note: Make sure to not call this before adapter->port is valid */
|
||||
#if !defined(NETXEN_DEBUG)
|
||||
#define DPRINTK(klevel, fmt, args...) do { \
|
||||
} while (0)
|
||||
#else
|
||||
#define DPRINTK(klevel, fmt, args...) do { \
|
||||
printk(KERN_##klevel PFX "%s: %s: " fmt, __FUNCTION__,\
|
||||
(adapter != NULL && adapter->port != NULL && \
|
||||
adapter->port[0] != NULL && \
|
||||
adapter->port[0]->netdev != NULL) ? \
|
||||
adapter->port[0]->netdev->name : NULL, \
|
||||
## args); } while(0)
|
||||
#endif
|
||||
|
||||
/* Number of status descriptors to handle per interrupt */
|
||||
#define MAX_STATUS_HANDLE (128)
|
||||
|
||||
/*
|
||||
* netxen_skb_frag{} is to contain mapping info for each SG list. This
|
||||
* has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
|
||||
*/
|
||||
struct netxen_skb_frag {
|
||||
u64 dma;
|
||||
u32 length;
|
||||
};
|
||||
|
||||
/* Following defines are for the state of the buffers */
|
||||
#define NETXEN_BUFFER_FREE 0
|
||||
#define NETXEN_BUFFER_BUSY 1
|
||||
|
||||
/*
|
||||
* There will be one netxen_buffer per skb packet. These will be
|
||||
* used to save the dma info for pci_unmap_page()
|
||||
*/
|
||||
struct netxen_cmd_buffer {
|
||||
struct sk_buff *skb;
|
||||
struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
|
||||
u32 total_length;
|
||||
u32 mss;
|
||||
u16 port;
|
||||
u8 cmd;
|
||||
u8 frag_count;
|
||||
unsigned long time_stamp;
|
||||
u32 state;
|
||||
u32 no_of_descriptors;
|
||||
};
|
||||
|
||||
/* In rx_buffer, we do not need multiple fragments as is a single buffer */
|
||||
struct netxen_rx_buffer {
|
||||
struct sk_buff *skb;
|
||||
u64 dma;
|
||||
u16 ref_handle;
|
||||
u16 state;
|
||||
};
|
||||
|
||||
/* Board types */
|
||||
#define NETXEN_NIC_GBE 0x01
|
||||
#define NETXEN_NIC_XGBE 0x02
|
||||
|
||||
/*
|
||||
* One hardware_context{} per adapter
|
||||
* contains interrupt info as well shared hardware info.
|
||||
*/
|
||||
struct netxen_hardware_context {
|
||||
struct pci_dev *pdev;
|
||||
void __iomem *pci_base; /* base of mapped phantom memory */
|
||||
u8 revision_id;
|
||||
u16 board_type;
|
||||
u16 max_ports;
|
||||
struct netxen_board_info boardcfg;
|
||||
u32 xg_linkup;
|
||||
/* Address of cmd ring in Phantom */
|
||||
struct cmd_desc_type0 *cmd_desc_head;
|
||||
dma_addr_t cmd_desc_phys_addr;
|
||||
struct netxen_adapter *adapter;
|
||||
};
|
||||
|
||||
#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
|
||||
#define ETHERNET_FCS_SIZE 4
|
||||
|
||||
struct netxen_adapter_stats {
|
||||
u64 ints;
|
||||
u64 hostints;
|
||||
u64 otherints;
|
||||
u64 process_rcv;
|
||||
u64 process_xmit;
|
||||
u64 noxmitdone;
|
||||
u64 xmitcsummed;
|
||||
u64 post_called;
|
||||
u64 posted;
|
||||
u64 lastposted;
|
||||
u64 goodskbposts;
|
||||
};
|
||||
|
||||
/*
|
||||
* Rcv Descriptor Context. One such per Rcv Descriptor. There may
|
||||
* be one Rcv Descriptor for normal packets, one for jumbo and may be others.
|
||||
*/
|
||||
struct netxen_rcv_desc_ctx {
|
||||
u32 flags;
|
||||
u32 producer;
|
||||
u32 rcv_pending; /* Num of bufs posted in phantom */
|
||||
u32 rcv_free; /* Num of bufs in free list */
|
||||
dma_addr_t phys_addr;
|
||||
struct rcv_desc *desc_head; /* address of rx ring in Phantom */
|
||||
u32 max_rx_desc_count;
|
||||
u32 dma_size;
|
||||
u32 skb_size;
|
||||
struct netxen_rx_buffer *rx_buf_arr; /* rx buffers for receive */
|
||||
int begin_alloc;
|
||||
};
|
||||
|
||||
/*
|
||||
* Receive context. There is one such structure per instance of the
|
||||
* receive processing. Any state information that is relevant to
|
||||
* the receive, and is must be in this structure. The global data may be
|
||||
* present elsewhere.
|
||||
*/
|
||||
struct netxen_recv_context {
|
||||
struct netxen_rcv_desc_ctx rcv_desc[NUM_RCV_DESC_RINGS];
|
||||
u32 status_rx_producer;
|
||||
u32 status_rx_consumer;
|
||||
dma_addr_t rcv_status_desc_phys_addr;
|
||||
struct status_desc *rcv_status_desc_head;
|
||||
};
|
||||
|
||||
#define NETXEN_NIC_MSI_ENABLED 0x02
|
||||
|
||||
struct netxen_drvops;
|
||||
|
||||
struct netxen_adapter {
|
||||
struct netxen_hardware_context ahw;
|
||||
int port_count; /* Number of configured ports */
|
||||
int active_ports; /* Number of open ports */
|
||||
struct netxen_port *port[NETXEN_MAX_PORTS]; /* ptr to each port */
|
||||
spinlock_t tx_lock;
|
||||
spinlock_t lock;
|
||||
struct work_struct watchdog_task;
|
||||
struct work_struct tx_timeout_task;
|
||||
struct timer_list watchdog_timer;
|
||||
|
||||
u32 curr_window;
|
||||
|
||||
u32 cmd_producer;
|
||||
u32 cmd_consumer;
|
||||
|
||||
u32 last_cmd_consumer;
|
||||
u32 max_tx_desc_count;
|
||||
u32 max_rx_desc_count;
|
||||
u32 max_jumbo_rx_desc_count;
|
||||
/* Num of instances active on cmd buffer ring */
|
||||
u32 proc_cmd_buf_counter;
|
||||
|
||||
u32 num_threads, total_threads; /*Use to keep track of xmit threads */
|
||||
|
||||
u32 flags;
|
||||
u32 irq;
|
||||
int driver_mismatch;
|
||||
|
||||
struct netxen_adapter_stats stats;
|
||||
|
||||
struct netxen_cmd_buffer *cmd_buf_arr; /* Command buffers for xmit */
|
||||
|
||||
/*
|
||||
* Receive instances. These can be either one per port,
|
||||
* or one per peg, etc.
|
||||
*/
|
||||
struct netxen_recv_context recv_ctx[MAX_RCV_CTX];
|
||||
|
||||
int is_up;
|
||||
int work_done;
|
||||
struct netxen_drvops *ops;
|
||||
}; /* netxen_adapter structure */
|
||||
|
||||
/* Max number of xmit producer threads that can run simultaneously */
|
||||
#define MAX_XMIT_PRODUCERS 16
|
||||
|
||||
struct netxen_port_stats {
|
||||
u64 rcvdbadskb;
|
||||
u64 xmitcalled;
|
||||
u64 xmitedframes;
|
||||
u64 xmitfinished;
|
||||
u64 badskblen;
|
||||
u64 nocmddescriptor;
|
||||
u64 polled;
|
||||
u64 uphappy;
|
||||
u64 updropped;
|
||||
u64 uplcong;
|
||||
u64 uphcong;
|
||||
u64 upmcong;
|
||||
u64 updunno;
|
||||
u64 skbfreed;
|
||||
u64 txdropped;
|
||||
u64 txnullskb;
|
||||
u64 csummed;
|
||||
u64 no_rcv;
|
||||
u64 rxbytes;
|
||||
u64 txbytes;
|
||||
};
|
||||
|
||||
struct netxen_port {
|
||||
struct netxen_adapter *adapter;
|
||||
|
||||
u16 portnum; /* GBE port number */
|
||||
u16 link_speed;
|
||||
u16 link_duplex;
|
||||
u16 link_autoneg;
|
||||
|
||||
int flags;
|
||||
|
||||
struct net_device *netdev;
|
||||
struct pci_dev *pdev;
|
||||
struct net_device_stats net_stats;
|
||||
struct netxen_port_stats stats;
|
||||
};
|
||||
|
||||
struct netxen_drvops {
|
||||
int (*enable_phy_interrupts) (struct netxen_adapter *, int);
|
||||
int (*disable_phy_interrupts) (struct netxen_adapter *, int);
|
||||
void (*handle_phy_intr) (struct netxen_adapter *);
|
||||
int (*macaddr_set) (struct netxen_port *, netxen_ethernet_macaddr_t);
|
||||
int (*set_mtu) (struct netxen_port *, int);
|
||||
int (*set_promisc) (struct netxen_adapter *, int,
|
||||
netxen_niu_prom_mode_t);
|
||||
int (*unset_promisc) (struct netxen_adapter *, int,
|
||||
netxen_niu_prom_mode_t);
|
||||
int (*phy_read) (struct netxen_adapter *, long phy, long reg, u32 *);
|
||||
int (*phy_write) (struct netxen_adapter *, long phy, long reg, u32 val);
|
||||
int (*init_port) (struct netxen_adapter *, int);
|
||||
void (*init_niu) (struct netxen_adapter *);
|
||||
int (*stop_port) (struct netxen_adapter *, int);
|
||||
};
|
||||
|
||||
extern char netxen_nic_driver_name[];
|
||||
|
||||
int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter,
|
||||
int port);
|
||||
int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter,
|
||||
int port);
|
||||
int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter,
|
||||
int port);
|
||||
int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter,
|
||||
int port);
|
||||
int netxen_niu_xgbe_clear_phy_interrupts(struct netxen_adapter *adapter,
|
||||
int port);
|
||||
int netxen_niu_gbe_clear_phy_interrupts(struct netxen_adapter *adapter,
|
||||
int port);
|
||||
void netxen_nic_xgbe_handle_phy_intr(struct netxen_adapter *adapter);
|
||||
void netxen_nic_gbe_handle_phy_intr(struct netxen_adapter *adapter);
|
||||
void netxen_niu_gbe_set_mii_mode(struct netxen_adapter *adapter, int port,
|
||||
long enable);
|
||||
void netxen_niu_gbe_set_gmii_mode(struct netxen_adapter *adapter, int port,
|
||||
long enable);
|
||||
int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long phy, long reg,
|
||||
__le32 * readval);
|
||||
int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, long phy,
|
||||
long reg, __le32 val);
|
||||
|
||||
/* Functions available from netxen_nic_hw.c */
|
||||
int netxen_niu_xginit(struct netxen_adapter *);
|
||||
int netxen_nic_set_mtu_xgb(struct netxen_port *port, int new_mtu);
|
||||
int netxen_nic_set_mtu_gb(struct netxen_port *port, int new_mtu);
|
||||
void netxen_nic_init_niu_gb(struct netxen_adapter *adapter);
|
||||
void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw);
|
||||
void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val);
|
||||
int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off);
|
||||
void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value);
|
||||
void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value);
|
||||
|
||||
int netxen_nic_get_board_info(struct netxen_adapter *adapter);
|
||||
int netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
|
||||
int len);
|
||||
int netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
|
||||
int len);
|
||||
void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
|
||||
unsigned long off, int data);
|
||||
|
||||
/* Functions from netxen_nic_init.c */
|
||||
void netxen_phantom_init(struct netxen_adapter *adapter);
|
||||
void netxen_load_firmware(struct netxen_adapter *adapter);
|
||||
int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
|
||||
int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
|
||||
|
||||
/* Functions from netxen_nic_isr.c */
|
||||
void netxen_nic_isr_other(struct netxen_adapter *adapter);
|
||||
void netxen_indicate_link_status(struct netxen_adapter *adapter, u32 port,
|
||||
u32 link);
|
||||
void netxen_handle_port_int(struct netxen_adapter *adapter, u32 port,
|
||||
u32 enable);
|
||||
void netxen_nic_stop_all_ports(struct netxen_adapter *adapter);
|
||||
void netxen_initialize_adapter_sw(struct netxen_adapter *adapter);
|
||||
void netxen_initialize_adapter_hw(struct netxen_adapter *adapter);
|
||||
void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
|
||||
int netxen_init_firmware(struct netxen_adapter *adapter);
|
||||
void netxen_free_hw_resources(struct netxen_adapter *adapter);
|
||||
void netxen_tso_check(struct netxen_adapter *adapter,
|
||||
struct cmd_desc_type0 *desc, struct sk_buff *skb);
|
||||
int netxen_nic_hw_resources(struct netxen_adapter *adapter);
|
||||
void netxen_nic_clear_stats(struct netxen_adapter *adapter);
|
||||
int
|
||||
netxen_nic_do_ioctl(struct netxen_adapter *adapter, void *u_data,
|
||||
struct netxen_port *port);
|
||||
int netxen_nic_rx_has_work(struct netxen_adapter *adapter);
|
||||
int netxen_nic_tx_has_work(struct netxen_adapter *adapter);
|
||||
void netxen_watchdog_task(unsigned long v);
|
||||
void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx,
|
||||
u32 ringid);
|
||||
void netxen_process_cmd_ring(unsigned long data);
|
||||
u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctx, int max);
|
||||
void netxen_nic_set_multi(struct net_device *netdev);
|
||||
int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
|
||||
int netxen_nic_set_mac(struct net_device *netdev, void *p);
|
||||
struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
|
||||
|
||||
static inline void netxen_nic_disable_int(struct netxen_adapter *adapter)
|
||||
{
|
||||
/*
|
||||
* ISR_INT_MASK: Can be read from window 0 or 1.
|
||||
*/
|
||||
writel(0x7ff, (void __iomem *)(adapter->ahw.pci_base + ISR_INT_MASK));
|
||||
}
|
||||
|
||||
static inline void netxen_nic_enable_int(struct netxen_adapter *adapter)
|
||||
{
|
||||
u32 mask;
|
||||
|
||||
switch (adapter->ahw.board_type) {
|
||||
case NETXEN_NIC_GBE:
|
||||
mask = 0x77b;
|
||||
break;
|
||||
case NETXEN_NIC_XGBE:
|
||||
mask = 0x77f;
|
||||
break;
|
||||
default:
|
||||
mask = 0x7ff;
|
||||
break;
|
||||
}
|
||||
|
||||
writel(mask, (void __iomem *)(adapter->ahw.pci_base + ISR_INT_MASK));
|
||||
|
||||
if (!(adapter->flags & NETXEN_NIC_MSI_ENABLED)) {
|
||||
mask = 0xbff;
|
||||
writel(mask, (void __iomem *)
|
||||
(adapter->ahw.pci_base + ISR_INT_TARGET_MASK));
|
||||
}
|
||||
}
|
||||
|
||||
int netxen_is_flash_supported(struct netxen_adapter *adapter);
|
||||
int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 mac[]);
|
||||
|
||||
extern void netxen_change_ringparam(struct netxen_adapter *adapter);
|
||||
extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
|
||||
int *valp);
|
||||
|
||||
extern struct ethtool_ops netxen_nic_ethtool_ops;
|
||||
|
||||
#endif /* __NETXEN_NIC_H_ */
|
||||
|
|
@ -0,0 +1,715 @@
|
|||
/*
|
||||
* Copyright (C) 2003 - 2006 NetXen, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston,
|
||||
* MA 02111-1307, USA.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution
|
||||
* in the file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* info@netxen.com
|
||||
* NetXen,
|
||||
* 3965 Freedom Circle, Fourth floor,
|
||||
* Santa Clara, CA 95054
|
||||
*
|
||||
*
|
||||
* ethtool support for netxen nic
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <asm/uaccess.h>
|
||||
#include <linux/pci.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/ethtool.h>
|
||||
#include <linux/version.h>
|
||||
|
||||
#include "netxen_nic_hw.h"
|
||||
#include "netxen_nic.h"
|
||||
#include "netxen_nic_phan_reg.h"
|
||||
#include "netxen_nic_ioctl.h"
|
||||
|
||||
struct netxen_nic_stats {
|
||||
char stat_string[ETH_GSTRING_LEN];
|
||||
int sizeof_stat;
|
||||
int stat_offset;
|
||||
};
|
||||
|
||||
#define NETXEN_NIC_STAT(m) sizeof(((struct netxen_port *)0)->m), \
|
||||
offsetof(struct netxen_port, m)
|
||||
|
||||
static const struct netxen_nic_stats netxen_nic_gstrings_stats[] = {
|
||||
{"rcvd_bad_skb", NETXEN_NIC_STAT(stats.rcvdbadskb)},
|
||||
{"xmit_called", NETXEN_NIC_STAT(stats.xmitcalled)},
|
||||
{"xmited_frames", NETXEN_NIC_STAT(stats.xmitedframes)},
|
||||
{"xmit_finished", NETXEN_NIC_STAT(stats.xmitfinished)},
|
||||
{"bad_skb_len", NETXEN_NIC_STAT(stats.badskblen)},
|
||||
{"no_cmd_desc", NETXEN_NIC_STAT(stats.nocmddescriptor)},
|
||||
{"polled", NETXEN_NIC_STAT(stats.polled)},
|
||||
{"uphappy", NETXEN_NIC_STAT(stats.uphappy)},
|
||||
{"updropped", NETXEN_NIC_STAT(stats.updropped)},
|
||||
{"uplcong", NETXEN_NIC_STAT(stats.uplcong)},
|
||||
{"uphcong", NETXEN_NIC_STAT(stats.uphcong)},
|
||||
{"upmcong", NETXEN_NIC_STAT(stats.upmcong)},
|
||||
{"updunno", NETXEN_NIC_STAT(stats.updunno)},
|
||||
{"skb_freed", NETXEN_NIC_STAT(stats.skbfreed)},
|
||||
{"tx_dropped", NETXEN_NIC_STAT(stats.txdropped)},
|
||||
{"tx_null_skb", NETXEN_NIC_STAT(stats.txnullskb)},
|
||||
{"csummed", NETXEN_NIC_STAT(stats.csummed)},
|
||||
{"no_rcv", NETXEN_NIC_STAT(stats.no_rcv)},
|
||||
{"rx_bytes", NETXEN_NIC_STAT(stats.rxbytes)},
|
||||
{"tx_bytes", NETXEN_NIC_STAT(stats.txbytes)},
|
||||
};
|
||||
|
||||
#define NETXEN_NIC_STATS_LEN \
|
||||
sizeof(netxen_nic_gstrings_stats) / sizeof(struct netxen_nic_stats)
|
||||
|
||||
static const char netxen_nic_gstrings_test[][ETH_GSTRING_LEN] = {
|
||||
"Register_Test_offline", "EEPROM_Test_offline",
|
||||
"Interrupt_Test_offline", "Loopback_Test_offline",
|
||||
"Link_Test_on_offline"
|
||||
};
|
||||
|
||||
#define NETXEN_NIC_TEST_LEN sizeof(netxen_nic_gstrings_test) / ETH_GSTRING_LEN
|
||||
|
||||
#define NETXEN_NIC_REGS_COUNT 42
|
||||
#define NETXEN_NIC_REGS_LEN (NETXEN_NIC_REGS_COUNT * sizeof(__le32))
|
||||
#define NETXEN_MAX_EEPROM_LEN 1024
|
||||
|
||||
static int netxen_nic_get_eeprom_len(struct net_device *dev)
|
||||
{
|
||||
struct netxen_port *port = netdev_priv(dev);
|
||||
struct netxen_adapter *adapter = port->adapter;
|
||||
int n;
|
||||
|
||||
if ((netxen_rom_fast_read(adapter, 0, &n) == 0)
|
||||
&& (n & NETXEN_ROM_ROUNDUP)) {
|
||||
n &= ~NETXEN_ROM_ROUNDUP;
|
||||
if (n < NETXEN_MAX_EEPROM_LEN)
|
||||
return n;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
netxen_nic_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo)
|
||||
{
|
||||
struct netxen_port *port = netdev_priv(dev);
|
||||
struct netxen_adapter *adapter = port->adapter;
|
||||
uint32_t fw_major = 0;
|
||||
uint32_t fw_minor = 0;
|
||||
uint32_t fw_build = 0;
|
||||
|
||||
strncpy(drvinfo->driver, "netxen_nic", 32);
|
||||
strncpy(drvinfo->version, NETXEN_NIC_LINUX_VERSIONID, 32);
|
||||
fw_major = readl(NETXEN_CRB_NORMALIZE(adapter,
|
||||
NETXEN_FW_VERSION_MAJOR));
|
||||
fw_minor = readl(NETXEN_CRB_NORMALIZE(adapter,
|
||||
NETXEN_FW_VERSION_MINOR));
|
||||
fw_build = readl(NETXEN_CRB_NORMALIZE(adapter, NETXEN_FW_VERSION_SUB));
|
||||
sprintf(drvinfo->fw_version, "%d.%d.%d", fw_major, fw_minor, fw_build);
|
||||
|
||||
strncpy(drvinfo->bus_info, pci_name(port->pdev), 32);
|
||||
drvinfo->n_stats = NETXEN_NIC_STATS_LEN;
|
||||
drvinfo->testinfo_len = NETXEN_NIC_TEST_LEN;
|
||||
drvinfo->regdump_len = NETXEN_NIC_REGS_LEN;
|
||||
drvinfo->eedump_len = netxen_nic_get_eeprom_len(dev);
|
||||
}
|
||||
|
||||
static int
|
||||
netxen_nic_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
|
||||
{
|
||||
struct netxen_port *port = netdev_priv(dev);
|
||||
struct netxen_adapter *adapter = port->adapter;
|
||||
|
||||
/* read which mode */
|
||||
if (adapter->ahw.board_type == NETXEN_NIC_GBE) {
|
||||
ecmd->supported = (SUPPORTED_10baseT_Half |
|
||||
SUPPORTED_10baseT_Full |
|
||||
SUPPORTED_100baseT_Half |
|
||||
SUPPORTED_100baseT_Full |
|
||||
SUPPORTED_1000baseT_Half |
|
||||
SUPPORTED_1000baseT_Full |
|
||||
SUPPORTED_TP |
|
||||
SUPPORTED_MII | SUPPORTED_Autoneg);
|
||||
|
||||
ecmd->advertising = (ADVERTISED_100baseT_Half |
|
||||
ADVERTISED_100baseT_Full |
|
||||
ADVERTISED_1000baseT_Half |
|
||||
ADVERTISED_1000baseT_Full |
|
||||
ADVERTISED_TP |
|
||||
ADVERTISED_MII | ADVERTISED_Autoneg);
|
||||
|
||||
ecmd->port = PORT_TP;
|
||||
|
||||
if (netif_running(dev)) {
|
||||
ecmd->speed = port->link_speed;
|
||||
ecmd->duplex = port->link_duplex;
|
||||
} else
|
||||
return -EIO; /* link absent */
|
||||
|
||||
ecmd->phy_address = port->portnum;
|
||||
ecmd->transceiver = XCVR_EXTERNAL;
|
||||
|
||||
/* get autoneg settings */
|
||||
ecmd->autoneg = port->link_autoneg;
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (adapter->ahw.board_type == NETXEN_NIC_XGBE) {
|
||||
ecmd->supported = (SUPPORTED_TP |
|
||||
SUPPORTED_1000baseT_Full |
|
||||
SUPPORTED_10000baseT_Full);
|
||||
ecmd->advertising = (ADVERTISED_TP |
|
||||
ADVERTISED_1000baseT_Full |
|
||||
ADVERTISED_10000baseT_Full);
|
||||
ecmd->port = PORT_TP;
|
||||
|
||||
ecmd->speed = SPEED_10000;
|
||||
ecmd->duplex = DUPLEX_FULL;
|
||||
ecmd->phy_address = port->portnum;
|
||||
ecmd->transceiver = XCVR_EXTERNAL;
|
||||
ecmd->autoneg = AUTONEG_DISABLE;
|
||||
return 0;
|
||||
}
|
||||
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
static int
|
||||
netxen_nic_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
|
||||
{
|
||||
struct netxen_port *port = netdev_priv(dev);
|
||||
struct netxen_adapter *adapter = port->adapter;
|
||||
__le32 status;
|
||||
|
||||
/* read which mode */
|
||||
if (adapter->ahw.board_type == NETXEN_NIC_GBE) {
|
||||
/* autonegotiation */
|
||||
if (adapter->ops->phy_write
|
||||
&& adapter->ops->phy_write(adapter, port->portnum,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
|
||||
(__le32) ecmd->autoneg) != 0)
|
||||
return -EIO;
|
||||
else
|
||||
port->link_autoneg = ecmd->autoneg;
|
||||
|
||||
if (adapter->ops->phy_read
|
||||
&& adapter->ops->phy_read(adapter, port->portnum,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
|
||||
&status) != 0)
|
||||
return -EIO;
|
||||
|
||||
/* speed */
|
||||
switch (ecmd->speed) {
|
||||
case SPEED_10:
|
||||
netxen_set_phy_speed(status, 0);
|
||||
break;
|
||||
case SPEED_100:
|
||||
netxen_set_phy_speed(status, 1);
|
||||
break;
|
||||
case SPEED_1000:
|
||||
netxen_set_phy_speed(status, 2);
|
||||
break;
|
||||
}
|
||||
/* set duplex mode */
|
||||
if (ecmd->duplex == DUPLEX_HALF)
|
||||
netxen_clear_phy_duplex(status);
|
||||
if (ecmd->duplex == DUPLEX_FULL)
|
||||
netxen_set_phy_duplex(status);
|
||||
if (adapter->ops->phy_write
|
||||
&& adapter->ops->phy_write(adapter, port->portnum,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
|
||||
*((int *)&status)) != 0)
|
||||
return -EIO;
|
||||
else {
|
||||
port->link_speed = ecmd->speed;
|
||||
port->link_duplex = ecmd->duplex;
|
||||
}
|
||||
} else
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
if (netif_running(dev)) {
|
||||
dev->stop(dev);
|
||||
dev->open(dev);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int netxen_nic_get_regs_len(struct net_device *dev)
|
||||
{
|
||||
return NETXEN_NIC_REGS_LEN;
|
||||
}
|
||||
|
||||
struct netxen_niu_regs {
|
||||
__le32 reg[NETXEN_NIC_REGS_COUNT];
|
||||
};
|
||||
|
||||
static struct netxen_niu_regs niu_registers[] = {
|
||||
{
|
||||
/* GB Mode */
|
||||
{
|
||||
NETXEN_NIU_GB_SERDES_RESET,
|
||||
NETXEN_NIU_GB0_MII_MODE,
|
||||
NETXEN_NIU_GB1_MII_MODE,
|
||||
NETXEN_NIU_GB2_MII_MODE,
|
||||
NETXEN_NIU_GB3_MII_MODE,
|
||||
NETXEN_NIU_GB0_GMII_MODE,
|
||||
NETXEN_NIU_GB1_GMII_MODE,
|
||||
NETXEN_NIU_GB2_GMII_MODE,
|
||||
NETXEN_NIU_GB3_GMII_MODE,
|
||||
NETXEN_NIU_REMOTE_LOOPBACK,
|
||||
NETXEN_NIU_GB0_HALF_DUPLEX,
|
||||
NETXEN_NIU_GB1_HALF_DUPLEX,
|
||||
NETXEN_NIU_RESET_SYS_FIFOS,
|
||||
NETXEN_NIU_GB_CRC_DROP,
|
||||
NETXEN_NIU_GB_DROP_WRONGADDR,
|
||||
NETXEN_NIU_TEST_MUX_CTL,
|
||||
|
||||
NETXEN_NIU_GB_MAC_CONFIG_0(0),
|
||||
NETXEN_NIU_GB_MAC_CONFIG_1(0),
|
||||
NETXEN_NIU_GB_HALF_DUPLEX_CTRL(0),
|
||||
NETXEN_NIU_GB_MAX_FRAME_SIZE(0),
|
||||
NETXEN_NIU_GB_TEST_REG(0),
|
||||
NETXEN_NIU_GB_MII_MGMT_CONFIG(0),
|
||||
NETXEN_NIU_GB_MII_MGMT_COMMAND(0),
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR(0),
|
||||
NETXEN_NIU_GB_MII_MGMT_CTRL(0),
|
||||
NETXEN_NIU_GB_MII_MGMT_STATUS(0),
|
||||
NETXEN_NIU_GB_MII_MGMT_INDICATE(0),
|
||||
NETXEN_NIU_GB_INTERFACE_CTRL(0),
|
||||
NETXEN_NIU_GB_INTERFACE_STATUS(0),
|
||||
NETXEN_NIU_GB_STATION_ADDR_0(0),
|
||||
NETXEN_NIU_GB_STATION_ADDR_1(0),
|
||||
-1,
|
||||
}
|
||||
},
|
||||
{
|
||||
/* XG Mode */
|
||||
{
|
||||
NETXEN_NIU_XG_SINGLE_TERM,
|
||||
NETXEN_NIU_XG_DRIVE_HI,
|
||||
NETXEN_NIU_XG_DRIVE_LO,
|
||||
NETXEN_NIU_XG_DTX,
|
||||
NETXEN_NIU_XG_DEQ,
|
||||
NETXEN_NIU_XG_WORD_ALIGN,
|
||||
NETXEN_NIU_XG_RESET,
|
||||
NETXEN_NIU_XG_POWER_DOWN,
|
||||
NETXEN_NIU_XG_RESET_PLL,
|
||||
NETXEN_NIU_XG_SERDES_LOOPBACK,
|
||||
NETXEN_NIU_XG_DO_BYTE_ALIGN,
|
||||
NETXEN_NIU_XG_TX_ENABLE,
|
||||
NETXEN_NIU_XG_RX_ENABLE,
|
||||
NETXEN_NIU_XG_STATUS,
|
||||
NETXEN_NIU_XG_PAUSE_THRESHOLD,
|
||||
NETXEN_NIU_XGE_CONFIG_0,
|
||||
NETXEN_NIU_XGE_CONFIG_1,
|
||||
NETXEN_NIU_XGE_IPG,
|
||||
NETXEN_NIU_XGE_STATION_ADDR_0_HI,
|
||||
NETXEN_NIU_XGE_STATION_ADDR_0_1,
|
||||
NETXEN_NIU_XGE_STATION_ADDR_1_LO,
|
||||
NETXEN_NIU_XGE_STATUS,
|
||||
NETXEN_NIU_XGE_MAX_FRAME_SIZE,
|
||||
NETXEN_NIU_XGE_PAUSE_FRAME_VALUE,
|
||||
NETXEN_NIU_XGE_TX_BYTE_CNT,
|
||||
NETXEN_NIU_XGE_TX_FRAME_CNT,
|
||||
NETXEN_NIU_XGE_RX_BYTE_CNT,
|
||||
NETXEN_NIU_XGE_RX_FRAME_CNT,
|
||||
NETXEN_NIU_XGE_AGGR_ERROR_CNT,
|
||||
NETXEN_NIU_XGE_MULTICAST_FRAME_CNT,
|
||||
NETXEN_NIU_XGE_UNICAST_FRAME_CNT,
|
||||
NETXEN_NIU_XGE_CRC_ERROR_CNT,
|
||||
NETXEN_NIU_XGE_OVERSIZE_FRAME_ERR,
|
||||
NETXEN_NIU_XGE_UNDERSIZE_FRAME_ERR,
|
||||
NETXEN_NIU_XGE_LOCAL_ERROR_CNT,
|
||||
NETXEN_NIU_XGE_REMOTE_ERROR_CNT,
|
||||
NETXEN_NIU_XGE_CONTROL_CHAR_CNT,
|
||||
NETXEN_NIU_XGE_PAUSE_FRAME_CNT,
|
||||
-1,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
static void
|
||||
netxen_nic_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *p)
|
||||
{
|
||||
struct netxen_port *port = netdev_priv(dev);
|
||||
struct netxen_adapter *adapter = port->adapter;
|
||||
__le32 mode, *regs_buff = p;
|
||||
void __iomem *addr;
|
||||
int i, window;
|
||||
|
||||
memset(p, 0, NETXEN_NIC_REGS_LEN);
|
||||
regs->version = (1 << 24) | (adapter->ahw.revision_id << 16) |
|
||||
(port->pdev)->device;
|
||||
/* which mode */
|
||||
NETXEN_NIC_LOCKED_READ_REG(NETXEN_NIU_MODE, ®s_buff[0]);
|
||||
mode = regs_buff[0];
|
||||
|
||||
/* Common registers to all the modes */
|
||||
NETXEN_NIC_LOCKED_READ_REG(NETXEN_NIU_STRAP_VALUE_SAVE_HIGHER,
|
||||
®s_buff[2]);
|
||||
/* GB/XGB Mode */
|
||||
mode = (mode / 2) - 1;
|
||||
window = 0;
|
||||
if (mode <= 1) {
|
||||
for (i = 3; niu_registers[mode].reg[i - 3] != -1; i++) {
|
||||
/* GB: port specific registers */
|
||||
if (mode == 0 && i >= 19)
|
||||
window = port->portnum * 0x10000;
|
||||
|
||||
NETXEN_NIC_LOCKED_READ_REG(niu_registers[mode].
|
||||
reg[i - 3] + window,
|
||||
®s_buff[i]);
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
netxen_nic_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
|
||||
{
|
||||
wol->supported = WAKE_UCAST | WAKE_MCAST | WAKE_BCAST | WAKE_MAGIC;
|
||||
wol->wolopts = 0; /* options can be added depending upon the mode */
|
||||
}
|
||||
|
||||
static u32 netxen_nic_get_link(struct net_device *dev)
|
||||
{
|
||||
struct netxen_port *port = netdev_priv(dev);
|
||||
struct netxen_adapter *adapter = port->adapter;
|
||||
__le32 status;
|
||||
|
||||
/* read which mode */
|
||||
if (adapter->ahw.board_type == NETXEN_NIC_GBE) {
|
||||
if (adapter->ops->phy_read
|
||||
&& adapter->ops->phy_read(adapter, port->portnum,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
|
||||
&status) != 0)
|
||||
return -EIO;
|
||||
else
|
||||
return (netxen_get_phy_link(status));
|
||||
} else if (adapter->ahw.board_type == NETXEN_NIC_XGBE) {
|
||||
int val = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_XG_STATE));
|
||||
return val == XG_LINK_UP;
|
||||
}
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
static int
|
||||
netxen_nic_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
|
||||
u8 * bytes)
|
||||
{
|
||||
struct netxen_port *port = netdev_priv(dev);
|
||||
struct netxen_adapter *adapter = port->adapter;
|
||||
int offset;
|
||||
|
||||
if (eeprom->len == 0)
|
||||
return -EINVAL;
|
||||
|
||||
eeprom->magic = (port->pdev)->vendor | ((port->pdev)->device << 16);
|
||||
for (offset = 0; offset < eeprom->len; offset++)
|
||||
if (netxen_rom_fast_read
|
||||
(adapter, (8 * offset) + 8, (int *)eeprom->data) == -1)
|
||||
return -EIO;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
netxen_nic_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ring)
|
||||
{
|
||||
struct netxen_port *port = netdev_priv(dev);
|
||||
struct netxen_adapter *adapter = port->adapter;
|
||||
int i, j;
|
||||
|
||||
ring->rx_pending = 0;
|
||||
for (i = 0; i < MAX_RCV_CTX; ++i) {
|
||||
for (j = 0; j < NUM_RCV_DESC_RINGS; j++)
|
||||
ring->rx_pending +=
|
||||
adapter->recv_ctx[i].rcv_desc[j].rcv_pending;
|
||||
}
|
||||
|
||||
ring->rx_max_pending = adapter->max_rx_desc_count;
|
||||
ring->tx_max_pending = adapter->max_tx_desc_count;
|
||||
ring->rx_mini_max_pending = 0;
|
||||
ring->rx_mini_pending = 0;
|
||||
ring->rx_jumbo_max_pending = 0;
|
||||
ring->rx_jumbo_pending = 0;
|
||||
}
|
||||
|
||||
static void
|
||||
netxen_nic_get_pauseparam(struct net_device *dev,
|
||||
struct ethtool_pauseparam *pause)
|
||||
{
|
||||
struct netxen_port *port = netdev_priv(dev);
|
||||
struct netxen_adapter *adapter = port->adapter;
|
||||
__le32 val;
|
||||
|
||||
if (adapter->ahw.board_type == NETXEN_NIC_GBE) {
|
||||
/* get flow control settings */
|
||||
netxen_nic_read_w0(adapter,
|
||||
NETXEN_NIU_GB_MAC_CONFIG_0(port->portnum),
|
||||
(u32 *) & val);
|
||||
pause->rx_pause = netxen_gb_get_rx_flowctl(val);
|
||||
pause->tx_pause = netxen_gb_get_tx_flowctl(val);
|
||||
/* get autoneg settings */
|
||||
pause->autoneg = port->link_autoneg;
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
netxen_nic_set_pauseparam(struct net_device *dev,
|
||||
struct ethtool_pauseparam *pause)
|
||||
{
|
||||
struct netxen_port *port = netdev_priv(dev);
|
||||
struct netxen_adapter *adapter = port->adapter;
|
||||
__le32 val;
|
||||
unsigned int autoneg;
|
||||
|
||||
/* read mode */
|
||||
if (adapter->ahw.board_type == NETXEN_NIC_GBE) {
|
||||
/* set flow control */
|
||||
netxen_nic_read_w0(adapter,
|
||||
NETXEN_NIU_GB_MAC_CONFIG_0(port->portnum),
|
||||
(u32 *) & val);
|
||||
if (pause->tx_pause)
|
||||
netxen_gb_tx_flowctl(val);
|
||||
else
|
||||
netxen_gb_unset_tx_flowctl(val);
|
||||
if (pause->rx_pause)
|
||||
netxen_gb_rx_flowctl(val);
|
||||
else
|
||||
netxen_gb_unset_rx_flowctl(val);
|
||||
|
||||
netxen_nic_write_w0(adapter,
|
||||
NETXEN_NIU_GB_MAC_CONFIG_0(port->portnum),
|
||||
*(u32 *) (&val));
|
||||
/* set autoneg */
|
||||
autoneg = pause->autoneg;
|
||||
if (adapter->ops->phy_write
|
||||
&& adapter->ops->phy_write(adapter, port->portnum,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
|
||||
(__le32) autoneg) != 0)
|
||||
return -EIO;
|
||||
else {
|
||||
port->link_autoneg = pause->autoneg;
|
||||
return 0;
|
||||
}
|
||||
} else
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
static int netxen_nic_reg_test(struct net_device *dev)
|
||||
{
|
||||
struct netxen_port *port = netdev_priv(dev);
|
||||
struct netxen_adapter *adapter = port->adapter;
|
||||
u32 data_read, data_written, save;
|
||||
__le32 mode;
|
||||
|
||||
/*
|
||||
* first test the "Read Only" registers by writing which mode
|
||||
*/
|
||||
netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode);
|
||||
if (netxen_get_niu_enable_ge(mode)) { /* GB Mode */
|
||||
netxen_nic_read_w0(adapter,
|
||||
NETXEN_NIU_GB_MII_MGMT_STATUS(port->portnum),
|
||||
&data_read);
|
||||
|
||||
save = data_read;
|
||||
if (data_read)
|
||||
data_written = data_read & 0xDEADBEEF;
|
||||
else
|
||||
data_written = 0xDEADBEEF;
|
||||
netxen_nic_write_w0(adapter,
|
||||
NETXEN_NIU_GB_MII_MGMT_STATUS(port->
|
||||
portnum),
|
||||
data_written);
|
||||
netxen_nic_read_w0(adapter,
|
||||
NETXEN_NIU_GB_MII_MGMT_STATUS(port->portnum),
|
||||
&data_read);
|
||||
|
||||
if (data_written == data_read) {
|
||||
netxen_nic_write_w0(adapter,
|
||||
NETXEN_NIU_GB_MII_MGMT_STATUS(port->
|
||||
portnum),
|
||||
save);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* netxen_niu_gb_mii_mgmt_indicators is read only */
|
||||
netxen_nic_read_w0(adapter,
|
||||
NETXEN_NIU_GB_MII_MGMT_INDICATE(port->
|
||||
portnum),
|
||||
&data_read);
|
||||
|
||||
save = data_read;
|
||||
if (data_read)
|
||||
data_written = data_read & 0xDEADBEEF;
|
||||
else
|
||||
data_written = 0xDEADBEEF;
|
||||
netxen_nic_write_w0(adapter,
|
||||
NETXEN_NIU_GB_MII_MGMT_INDICATE(port->
|
||||
portnum),
|
||||
data_written);
|
||||
|
||||
netxen_nic_read_w0(adapter,
|
||||
NETXEN_NIU_GB_MII_MGMT_INDICATE(port->
|
||||
portnum),
|
||||
&data_read);
|
||||
|
||||
if (data_written == data_read) {
|
||||
netxen_nic_write_w0(adapter,
|
||||
NETXEN_NIU_GB_MII_MGMT_INDICATE
|
||||
(port->portnum), save);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* netxen_niu_gb_interface_status is read only */
|
||||
netxen_nic_read_w0(adapter,
|
||||
NETXEN_NIU_GB_INTERFACE_STATUS(port->
|
||||
portnum),
|
||||
&data_read);
|
||||
|
||||
save = data_read;
|
||||
if (data_read)
|
||||
data_written = data_read & 0xDEADBEEF;
|
||||
else
|
||||
data_written = 0xDEADBEEF;
|
||||
netxen_nic_write_w0(adapter,
|
||||
NETXEN_NIU_GB_INTERFACE_STATUS(port->
|
||||
portnum),
|
||||
data_written);
|
||||
|
||||
netxen_nic_read_w0(adapter,
|
||||
NETXEN_NIU_GB_INTERFACE_STATUS(port->
|
||||
portnum),
|
||||
&data_read);
|
||||
|
||||
if (data_written == data_read) {
|
||||
netxen_nic_write_w0(adapter,
|
||||
NETXEN_NIU_GB_INTERFACE_STATUS
|
||||
(port->portnum), save);
|
||||
|
||||
return 0;
|
||||
}
|
||||
} /* GB Mode */
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int netxen_nic_diag_test_count(struct net_device *dev)
|
||||
{
|
||||
return NETXEN_NIC_TEST_LEN;
|
||||
}
|
||||
|
||||
static void
|
||||
netxen_nic_diag_test(struct net_device *dev, struct ethtool_test *eth_test,
|
||||
u64 * data)
|
||||
{
|
||||
if (eth_test->flags == ETH_TEST_FL_OFFLINE) { /* offline tests */
|
||||
/* link test */
|
||||
if (!(data[4] = (u64) netxen_nic_get_link(dev)))
|
||||
eth_test->flags |= ETH_TEST_FL_FAILED;
|
||||
|
||||
if (netif_running(dev))
|
||||
dev->stop(dev);
|
||||
|
||||
/* register tests */
|
||||
if (!(data[0] = netxen_nic_reg_test(dev)))
|
||||
eth_test->flags |= ETH_TEST_FL_FAILED;
|
||||
/* other tests pass as of now */
|
||||
data[1] = data[2] = data[3] = 1;
|
||||
if (netif_running(dev))
|
||||
dev->open(dev);
|
||||
} else { /* online tests */
|
||||
/* link test */
|
||||
if (!(data[4] = (u64) netxen_nic_get_link(dev)))
|
||||
eth_test->flags |= ETH_TEST_FL_FAILED;
|
||||
|
||||
/* other tests pass by default */
|
||||
data[0] = data[1] = data[2] = data[3] = 1;
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
netxen_nic_get_strings(struct net_device *dev, u32 stringset, u8 * data)
|
||||
{
|
||||
int index;
|
||||
|
||||
switch (stringset) {
|
||||
case ETH_SS_TEST:
|
||||
memcpy(data, *netxen_nic_gstrings_test,
|
||||
NETXEN_NIC_TEST_LEN * ETH_GSTRING_LEN);
|
||||
break;
|
||||
case ETH_SS_STATS:
|
||||
for (index = 0; index < NETXEN_NIC_STATS_LEN; index++) {
|
||||
memcpy(data + index * ETH_GSTRING_LEN,
|
||||
netxen_nic_gstrings_stats[index].stat_string,
|
||||
ETH_GSTRING_LEN);
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static int netxen_nic_get_stats_count(struct net_device *dev)
|
||||
{
|
||||
return NETXEN_NIC_STATS_LEN;
|
||||
}
|
||||
|
||||
static void
|
||||
netxen_nic_get_ethtool_stats(struct net_device *dev,
|
||||
struct ethtool_stats *stats, u64 * data)
|
||||
{
|
||||
struct netxen_port *port = netdev_priv(dev);
|
||||
int index;
|
||||
|
||||
for (index = 0; index < NETXEN_NIC_STATS_LEN; index++) {
|
||||
char *p =
|
||||
(char *)port + netxen_nic_gstrings_stats[index].stat_offset;
|
||||
data[index] =
|
||||
(netxen_nic_gstrings_stats[index].sizeof_stat ==
|
||||
sizeof(u64)) ? *(u64 *) p : *(u32 *) p;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
struct ethtool_ops netxen_nic_ethtool_ops = {
|
||||
.get_settings = netxen_nic_get_settings,
|
||||
.set_settings = netxen_nic_set_settings,
|
||||
.get_drvinfo = netxen_nic_get_drvinfo,
|
||||
.get_regs_len = netxen_nic_get_regs_len,
|
||||
.get_regs = netxen_nic_get_regs,
|
||||
.get_wol = netxen_nic_get_wol,
|
||||
.get_link = netxen_nic_get_link,
|
||||
.get_eeprom_len = netxen_nic_get_eeprom_len,
|
||||
.get_eeprom = netxen_nic_get_eeprom,
|
||||
.get_ringparam = netxen_nic_get_ringparam,
|
||||
.get_pauseparam = netxen_nic_get_pauseparam,
|
||||
.set_pauseparam = netxen_nic_set_pauseparam,
|
||||
.get_tx_csum = ethtool_op_get_tx_csum,
|
||||
.set_tx_csum = ethtool_op_set_tx_csum,
|
||||
.get_sg = ethtool_op_get_sg,
|
||||
.set_sg = ethtool_op_set_sg,
|
||||
.get_tso = ethtool_op_get_tso,
|
||||
.set_tso = ethtool_op_set_tso,
|
||||
.self_test_count = netxen_nic_diag_test_count,
|
||||
.self_test = netxen_nic_diag_test,
|
||||
.get_strings = netxen_nic_get_strings,
|
||||
.get_stats_count = netxen_nic_get_stats_count,
|
||||
.get_ethtool_stats = netxen_nic_get_ethtool_stats,
|
||||
.get_perm_addr = ethtool_op_get_perm_addr,
|
||||
};
|
||||
|
|
@ -0,0 +1,618 @@
|
|||
/*
|
||||
* Copyright (C) 2003 - 2006 NetXen, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston,
|
||||
* MA 02111-1307, USA.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution
|
||||
* in the file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* info@netxen.com
|
||||
* NetXen,
|
||||
* 3965 Freedom Circle, Fourth floor,
|
||||
* Santa Clara, CA 95054
|
||||
*/
|
||||
|
||||
#ifndef __NETXEN_NIC_HDR_H_
|
||||
#define __NETXEN_NIC_HDR_H_
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/config.h>
|
||||
#include <linux/version.h>
|
||||
|
||||
#include <asm/semaphore.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <asm/irq.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/types.h>
|
||||
#include <asm/uaccess.h>
|
||||
#include <asm/string.h> /* for memset */
|
||||
|
||||
/*
|
||||
* The basic unit of access when reading/writing control registers.
|
||||
*/
|
||||
|
||||
typedef __le32 netxen_crbword_t; /* single word in CRB space */
|
||||
|
||||
enum {
|
||||
NETXEN_HW_H0_CH_HUB_ADR = 0x05,
|
||||
NETXEN_HW_H1_CH_HUB_ADR = 0x0E,
|
||||
NETXEN_HW_H2_CH_HUB_ADR = 0x03,
|
||||
NETXEN_HW_H3_CH_HUB_ADR = 0x01,
|
||||
NETXEN_HW_H4_CH_HUB_ADR = 0x06,
|
||||
NETXEN_HW_H5_CH_HUB_ADR = 0x07,
|
||||
NETXEN_HW_H6_CH_HUB_ADR = 0x08
|
||||
};
|
||||
|
||||
/* Hub 0 */
|
||||
enum {
|
||||
NETXEN_HW_MN_CRB_AGT_ADR = 0x15,
|
||||
NETXEN_HW_MS_CRB_AGT_ADR = 0x25
|
||||
};
|
||||
|
||||
/* Hub 1 */
|
||||
enum {
|
||||
NETXEN_HW_PS_CRB_AGT_ADR = 0x73,
|
||||
NETXEN_HW_SS_CRB_AGT_ADR = 0x20,
|
||||
NETXEN_HW_RPMX3_CRB_AGT_ADR = 0x0b,
|
||||
NETXEN_HW_QMS_CRB_AGT_ADR = 0x00,
|
||||
NETXEN_HW_SQGS0_CRB_AGT_ADR = 0x01,
|
||||
NETXEN_HW_SQGS1_CRB_AGT_ADR = 0x02,
|
||||
NETXEN_HW_SQGS2_CRB_AGT_ADR = 0x03,
|
||||
NETXEN_HW_SQGS3_CRB_AGT_ADR = 0x04,
|
||||
NETXEN_HW_C2C0_CRB_AGT_ADR = 0x58,
|
||||
NETXEN_HW_C2C1_CRB_AGT_ADR = 0x59,
|
||||
NETXEN_HW_C2C2_CRB_AGT_ADR = 0x5a,
|
||||
NETXEN_HW_RPMX2_CRB_AGT_ADR = 0x0a,
|
||||
NETXEN_HW_RPMX4_CRB_AGT_ADR = 0x0c,
|
||||
NETXEN_HW_RPMX7_CRB_AGT_ADR = 0x0f,
|
||||
NETXEN_HW_RPMX9_CRB_AGT_ADR = 0x12,
|
||||
NETXEN_HW_SMB_CRB_AGT_ADR = 0x18
|
||||
};
|
||||
|
||||
/* Hub 2 */
|
||||
enum {
|
||||
NETXEN_HW_NIU_CRB_AGT_ADR = 0x31,
|
||||
NETXEN_HW_I2C0_CRB_AGT_ADR = 0x19,
|
||||
NETXEN_HW_I2C1_CRB_AGT_ADR = 0x29,
|
||||
|
||||
NETXEN_HW_SN_CRB_AGT_ADR = 0x10,
|
||||
NETXEN_HW_I2Q_CRB_AGT_ADR = 0x20,
|
||||
NETXEN_HW_LPC_CRB_AGT_ADR = 0x22,
|
||||
NETXEN_HW_ROMUSB_CRB_AGT_ADR = 0x21,
|
||||
NETXEN_HW_QM_CRB_AGT_ADR = 0x66,
|
||||
NETXEN_HW_SQG0_CRB_AGT_ADR = 0x60,
|
||||
NETXEN_HW_SQG1_CRB_AGT_ADR = 0x61,
|
||||
NETXEN_HW_SQG2_CRB_AGT_ADR = 0x62,
|
||||
NETXEN_HW_SQG3_CRB_AGT_ADR = 0x63,
|
||||
NETXEN_HW_RPMX1_CRB_AGT_ADR = 0x09,
|
||||
NETXEN_HW_RPMX5_CRB_AGT_ADR = 0x0d,
|
||||
NETXEN_HW_RPMX6_CRB_AGT_ADR = 0x0e,
|
||||
NETXEN_HW_RPMX8_CRB_AGT_ADR = 0x11
|
||||
};
|
||||
|
||||
/* Hub 3 */
|
||||
enum {
|
||||
NETXEN_HW_PH_CRB_AGT_ADR = 0x1A,
|
||||
NETXEN_HW_SRE_CRB_AGT_ADR = 0x50,
|
||||
NETXEN_HW_EG_CRB_AGT_ADR = 0x51,
|
||||
NETXEN_HW_RPMX0_CRB_AGT_ADR = 0x08
|
||||
};
|
||||
|
||||
/* Hub 4 */
|
||||
enum {
|
||||
NETXEN_HW_PEGN0_CRB_AGT_ADR = 0x40,
|
||||
NETXEN_HW_PEGN1_CRB_AGT_ADR,
|
||||
NETXEN_HW_PEGN2_CRB_AGT_ADR,
|
||||
NETXEN_HW_PEGN3_CRB_AGT_ADR,
|
||||
NETXEN_HW_PEGNI_CRB_AGT_ADR,
|
||||
NETXEN_HW_PEGND_CRB_AGT_ADR,
|
||||
NETXEN_HW_PEGNC_CRB_AGT_ADR,
|
||||
NETXEN_HW_PEGR0_CRB_AGT_ADR,
|
||||
NETXEN_HW_PEGR1_CRB_AGT_ADR,
|
||||
NETXEN_HW_PEGR2_CRB_AGT_ADR,
|
||||
NETXEN_HW_PEGR3_CRB_AGT_ADR
|
||||
};
|
||||
|
||||
/* Hub 5 */
|
||||
enum {
|
||||
NETXEN_HW_PEGS0_CRB_AGT_ADR = 0x40,
|
||||
NETXEN_HW_PEGS1_CRB_AGT_ADR,
|
||||
NETXEN_HW_PEGS2_CRB_AGT_ADR,
|
||||
NETXEN_HW_PEGS3_CRB_AGT_ADR,
|
||||
NETXEN_HW_PEGSI_CRB_AGT_ADR,
|
||||
NETXEN_HW_PEGSD_CRB_AGT_ADR,
|
||||
NETXEN_HW_PEGSC_CRB_AGT_ADR
|
||||
};
|
||||
|
||||
/* Hub 6 */
|
||||
enum {
|
||||
NETXEN_HW_CAS0_CRB_AGT_ADR = 0x46,
|
||||
NETXEN_HW_CAS1_CRB_AGT_ADR = 0x47,
|
||||
NETXEN_HW_CAS2_CRB_AGT_ADR = 0x48,
|
||||
NETXEN_HW_CAS3_CRB_AGT_ADR = 0x49,
|
||||
NETXEN_HW_NCM_CRB_AGT_ADR = 0x16,
|
||||
NETXEN_HW_TMR_CRB_AGT_ADR = 0x17,
|
||||
NETXEN_HW_XDMA_CRB_AGT_ADR = 0x05,
|
||||
NETXEN_HW_OCM0_CRB_AGT_ADR = 0x06,
|
||||
NETXEN_HW_OCM1_CRB_AGT_ADR = 0x07
|
||||
};
|
||||
|
||||
/* Floaters - non existent modules */
|
||||
#define NETXEN_HW_EFC_RPMX0_CRB_AGT_ADR 0x67
|
||||
|
||||
/* This field defines PCI/X adr [25:20] of agents on the CRB */
|
||||
enum {
|
||||
NETXEN_HW_PX_MAP_CRB_PH = 0,
|
||||
NETXEN_HW_PX_MAP_CRB_PS,
|
||||
NETXEN_HW_PX_MAP_CRB_MN,
|
||||
NETXEN_HW_PX_MAP_CRB_MS,
|
||||
NETXEN_HW_PX_MAP_CRB_PGR1,
|
||||
NETXEN_HW_PX_MAP_CRB_SRE,
|
||||
NETXEN_HW_PX_MAP_CRB_NIU,
|
||||
NETXEN_HW_PX_MAP_CRB_QMN,
|
||||
NETXEN_HW_PX_MAP_CRB_SQN0,
|
||||
NETXEN_HW_PX_MAP_CRB_SQN1,
|
||||
NETXEN_HW_PX_MAP_CRB_SQN2,
|
||||
NETXEN_HW_PX_MAP_CRB_SQN3,
|
||||
NETXEN_HW_PX_MAP_CRB_QMS,
|
||||
NETXEN_HW_PX_MAP_CRB_SQS0,
|
||||
NETXEN_HW_PX_MAP_CRB_SQS1,
|
||||
NETXEN_HW_PX_MAP_CRB_SQS2,
|
||||
NETXEN_HW_PX_MAP_CRB_SQS3,
|
||||
NETXEN_HW_PX_MAP_CRB_PGN0,
|
||||
NETXEN_HW_PX_MAP_CRB_PGN1,
|
||||
NETXEN_HW_PX_MAP_CRB_PGN2,
|
||||
NETXEN_HW_PX_MAP_CRB_PGN3,
|
||||
NETXEN_HW_PX_MAP_CRB_PGND,
|
||||
NETXEN_HW_PX_MAP_CRB_PGNI,
|
||||
NETXEN_HW_PX_MAP_CRB_PGS0,
|
||||
NETXEN_HW_PX_MAP_CRB_PGS1,
|
||||
NETXEN_HW_PX_MAP_CRB_PGS2,
|
||||
NETXEN_HW_PX_MAP_CRB_PGS3,
|
||||
NETXEN_HW_PX_MAP_CRB_PGSD,
|
||||
NETXEN_HW_PX_MAP_CRB_PGSI,
|
||||
NETXEN_HW_PX_MAP_CRB_SN,
|
||||
NETXEN_HW_PX_MAP_CRB_PGR2,
|
||||
NETXEN_HW_PX_MAP_CRB_EG,
|
||||
NETXEN_HW_PX_MAP_CRB_PH2,
|
||||
NETXEN_HW_PX_MAP_CRB_PS2,
|
||||
NETXEN_HW_PX_MAP_CRB_CAM,
|
||||
NETXEN_HW_PX_MAP_CRB_CAS0,
|
||||
NETXEN_HW_PX_MAP_CRB_CAS1,
|
||||
NETXEN_HW_PX_MAP_CRB_CAS2,
|
||||
NETXEN_HW_PX_MAP_CRB_C2C0,
|
||||
NETXEN_HW_PX_MAP_CRB_C2C1,
|
||||
NETXEN_HW_PX_MAP_CRB_TIMR,
|
||||
NETXEN_HW_PX_MAP_CRB_PGR3,
|
||||
NETXEN_HW_PX_MAP_CRB_RPMX1,
|
||||
NETXEN_HW_PX_MAP_CRB_RPMX2,
|
||||
NETXEN_HW_PX_MAP_CRB_RPMX3,
|
||||
NETXEN_HW_PX_MAP_CRB_RPMX4,
|
||||
NETXEN_HW_PX_MAP_CRB_RPMX5,
|
||||
NETXEN_HW_PX_MAP_CRB_RPMX6,
|
||||
NETXEN_HW_PX_MAP_CRB_RPMX7,
|
||||
NETXEN_HW_PX_MAP_CRB_XDMA,
|
||||
NETXEN_HW_PX_MAP_CRB_I2Q,
|
||||
NETXEN_HW_PX_MAP_CRB_ROMUSB,
|
||||
NETXEN_HW_PX_MAP_CRB_CAS3,
|
||||
NETXEN_HW_PX_MAP_CRB_RPMX0,
|
||||
NETXEN_HW_PX_MAP_CRB_RPMX8,
|
||||
NETXEN_HW_PX_MAP_CRB_RPMX9,
|
||||
NETXEN_HW_PX_MAP_CRB_OCM0,
|
||||
NETXEN_HW_PX_MAP_CRB_OCM1,
|
||||
NETXEN_HW_PX_MAP_CRB_SMB,
|
||||
NETXEN_HW_PX_MAP_CRB_I2C0,
|
||||
NETXEN_HW_PX_MAP_CRB_I2C1,
|
||||
NETXEN_HW_PX_MAP_CRB_LPC,
|
||||
NETXEN_HW_PX_MAP_CRB_PGNC,
|
||||
NETXEN_HW_PX_MAP_CRB_PGR0
|
||||
};
|
||||
|
||||
/* This field defines CRB adr [31:20] of the agents */
|
||||
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_MN \
|
||||
((NETXEN_HW_H0_CH_HUB_ADR << 7) | NETXEN_HW_MN_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_PH \
|
||||
((NETXEN_HW_H0_CH_HUB_ADR << 7) | NETXEN_HW_PH_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_MS \
|
||||
((NETXEN_HW_H0_CH_HUB_ADR << 7) | NETXEN_HW_MS_CRB_AGT_ADR)
|
||||
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_PS \
|
||||
((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_PS_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_SS \
|
||||
((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SS_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3 \
|
||||
((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_RPMX3_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_QMS \
|
||||
((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_QMS_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_SQS0 \
|
||||
((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SQGS0_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_SQS1 \
|
||||
((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SQGS1_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_SQS2 \
|
||||
((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SQGS2_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_SQS3 \
|
||||
((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SQGS3_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_C2C0 \
|
||||
((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_C2C0_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_C2C1 \
|
||||
((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_C2C1_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2 \
|
||||
((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_RPMX2_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4 \
|
||||
((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_RPMX4_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7 \
|
||||
((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_RPMX7_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9 \
|
||||
((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_RPMX9_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_SMB \
|
||||
((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SMB_CRB_AGT_ADR)
|
||||
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_NIU \
|
||||
((NETXEN_HW_H2_CH_HUB_ADR << 7) | NETXEN_HW_NIU_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_I2C0 \
|
||||
((NETXEN_HW_H2_CH_HUB_ADR << 7) | NETXEN_HW_I2C0_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_I2C1 \
|
||||
((NETXEN_HW_H2_CH_HUB_ADR << 7) | NETXEN_HW_I2C1_CRB_AGT_ADR)
|
||||
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_SRE \
|
||||
((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_SRE_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_EG \
|
||||
((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_EG_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0 \
|
||||
((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_RPMX0_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_QMN \
|
||||
((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_QM_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_SQN0 \
|
||||
((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_SQG0_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_SQN1 \
|
||||
((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_SQG1_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_SQN2 \
|
||||
((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_SQG2_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_SQN3 \
|
||||
((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_SQG3_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1 \
|
||||
((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_RPMX1_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5 \
|
||||
((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_RPMX5_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6 \
|
||||
((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_RPMX6_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8 \
|
||||
((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_RPMX8_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_CAS0 \
|
||||
((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_CAS0_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_CAS1 \
|
||||
((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_CAS1_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_CAS2 \
|
||||
((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_CAS2_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_CAS3 \
|
||||
((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_CAS3_CRB_AGT_ADR)
|
||||
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_PGNI \
|
||||
((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGNI_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_PGND \
|
||||
((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGND_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_PGN0 \
|
||||
((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGN0_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_PGN1 \
|
||||
((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGN1_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_PGN2 \
|
||||
((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGN2_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_PGN3 \
|
||||
((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGN3_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_PGNC \
|
||||
((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGNC_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_PGR0 \
|
||||
((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGR0_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_PGR1 \
|
||||
((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGR1_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_PGR2 \
|
||||
((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGR2_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_PGR3 \
|
||||
((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGR3_CRB_AGT_ADR)
|
||||
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_PGSI \
|
||||
((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGSI_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_PGSD \
|
||||
((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGSD_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_PGS0 \
|
||||
((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGS0_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_PGS1 \
|
||||
((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGS1_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_PGS2 \
|
||||
((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGS2_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_PGS3 \
|
||||
((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGS3_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_PGSC \
|
||||
((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGSC_CRB_AGT_ADR)
|
||||
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_CAM \
|
||||
((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_NCM_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_TIMR \
|
||||
((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_TMR_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_XDMA \
|
||||
((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_XDMA_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_SN \
|
||||
((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_SN_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_I2Q \
|
||||
((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_I2Q_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB \
|
||||
((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_ROMUSB_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_OCM0 \
|
||||
((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_OCM0_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_OCM1 \
|
||||
((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_OCM1_CRB_AGT_ADR)
|
||||
#define NETXEN_HW_CRB_HUB_AGT_ADR_LPC \
|
||||
((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_LPC_CRB_AGT_ADR)
|
||||
|
||||
/*
|
||||
* MAX_RCV_CTX : The number of receive contexts that are available on
|
||||
* the phantom.
|
||||
*/
|
||||
#define MAX_RCV_CTX 1
|
||||
|
||||
#define NETXEN_SRE_INT_STATUS (NETXEN_CRB_SRE + 0x00034)
|
||||
#define NETXEN_SRE_PBI_ACTIVE_STATUS (NETXEN_CRB_SRE + 0x01014)
|
||||
#define NETXEN_SRE_L1RE_CTL (NETXEN_CRB_SRE + 0x03000)
|
||||
#define NETXEN_SRE_L2RE_CTL (NETXEN_CRB_SRE + 0x05000)
|
||||
#define NETXEN_SRE_BUF_CTL (NETXEN_CRB_SRE + 0x01000)
|
||||
|
||||
#define NETXEN_DMA_BASE(U) (NETXEN_CRB_PCIX_MD + 0x20000 + ((U)<<16))
|
||||
#define NETXEN_DMA_COMMAND(U) (NETXEN_DMA_BASE(U) + 0x00008)
|
||||
|
||||
#define NETXEN_I2Q_CLR_PCI_HI (NETXEN_CRB_I2Q + 0x00034)
|
||||
|
||||
#define PEG_NETWORK_BASE(N) (NETXEN_CRB_PEG_NET_0 + (((N)&3) << 20))
|
||||
#define CRB_REG_EX_PC 0x3c
|
||||
|
||||
#define ROMUSB_GLB (NETXEN_CRB_ROMUSB + 0x00000)
|
||||
#define ROMUSB_ROM (NETXEN_CRB_ROMUSB + 0x10000)
|
||||
|
||||
#define NETXEN_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004)
|
||||
#define NETXEN_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008)
|
||||
#define NETXEN_ROMUSB_GLB_PAD_GPIO_I (ROMUSB_GLB + 0x000c)
|
||||
#define NETXEN_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038)
|
||||
#define NETXEN_ROMUSB_GLB_TEST_MUX_SEL (ROMUSB_GLB + 0x0044)
|
||||
#define NETXEN_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c)
|
||||
#define NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL (ROMUSB_GLB + 0x00A8)
|
||||
|
||||
#define NETXEN_ROMUSB_GPIO(n) (ROMUSB_GLB + 0x60 + (4 * (n)))
|
||||
|
||||
#define NETXEN_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004)
|
||||
#define NETXEN_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008)
|
||||
#define NETXEN_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010)
|
||||
#define NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014)
|
||||
#define NETXEN_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018)
|
||||
|
||||
/* Lock IDs for ROM lock */
|
||||
#define ROM_LOCK_DRIVER 0x0d417340
|
||||
|
||||
#define NETXEN_PCI_CRB_WINDOWSIZE 0x00100000 /* all are 1MB windows */
|
||||
#define NETXEN_PCI_CRB_WINDOW(A) \
|
||||
(NETXEN_PCI_CRBSPACE + (A)*NETXEN_PCI_CRB_WINDOWSIZE)
|
||||
|
||||
#define NETXEN_CRB_NIU NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_NIU)
|
||||
#define NETXEN_CRB_SRE NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_SRE)
|
||||
#define NETXEN_CRB_ROMUSB \
|
||||
NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_ROMUSB)
|
||||
#define NETXEN_CRB_I2Q NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_I2Q)
|
||||
#define NETXEN_CRB_MAX NETXEN_PCI_CRB_WINDOW(64)
|
||||
|
||||
#define NETXEN_CRB_PCIX_HOST NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PH)
|
||||
#define NETXEN_CRB_PCIX_HOST2 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PH2)
|
||||
#define NETXEN_CRB_PEG_NET_0 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGN0)
|
||||
#define NETXEN_CRB_PEG_NET_1 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGN1)
|
||||
#define NETXEN_CRB_PEG_NET_2 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGN2)
|
||||
#define NETXEN_CRB_PEG_NET_3 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGN3)
|
||||
#define NETXEN_CRB_PEG_NET_D NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGND)
|
||||
#define NETXEN_CRB_PEG_NET_I NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGNI)
|
||||
#define NETXEN_CRB_DDR_NET NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_MN)
|
||||
|
||||
#define NETXEN_CRB_PCIX_MD NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PS)
|
||||
#define NETXEN_CRB_PCIE NETXEN_CRB_PCIX_MD
|
||||
|
||||
#define ISR_INT_VECTOR (NETXEN_PCIX_PS_REG(PCIX_INT_VECTOR))
|
||||
#define ISR_INT_MASK (NETXEN_PCIX_PS_REG(PCIX_INT_MASK))
|
||||
#define ISR_INT_MASK_SLOW (NETXEN_PCIX_PS_REG(PCIX_INT_MASK))
|
||||
#define ISR_INT_TARGET_STATUS (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS))
|
||||
#define ISR_INT_TARGET_MASK (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK))
|
||||
|
||||
#define NETXEN_PCI_MAPSIZE 128
|
||||
#define NETXEN_PCI_DDR_NET (0x00000000UL)
|
||||
#define NETXEN_PCI_QDR_NET (0x04000000UL)
|
||||
#define NETXEN_PCI_DIRECT_CRB (0x04400000UL)
|
||||
#define NETXEN_PCI_CAMQM_MAX (0x04ffffffUL)
|
||||
#define NETXEN_PCI_OCM0 (0x05000000UL)
|
||||
#define NETXEN_PCI_OCM0_MAX (0x050fffffUL)
|
||||
#define NETXEN_PCI_OCM1 (0x05100000UL)
|
||||
#define NETXEN_PCI_OCM1_MAX (0x051fffffUL)
|
||||
#define NETXEN_PCI_CRBSPACE (0x06000000UL)
|
||||
|
||||
#define NETXEN_CRB_CAM NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_CAM)
|
||||
|
||||
#define NETXEN_ADDR_DDR_NET (0x0000000000000000ULL)
|
||||
#define NETXEN_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
|
||||
#define NETXEN_ADDR_OCM0 (0x0000000200000000ULL)
|
||||
#define NETXEN_ADDR_OCM0_MAX (0x00000002000fffffULL)
|
||||
#define NETXEN_ADDR_OCM1 (0x0000000200400000ULL)
|
||||
#define NETXEN_ADDR_OCM1_MAX (0x00000002004fffffULL)
|
||||
#define NETXEN_ADDR_QDR_NET (0x0000000300000000ULL)
|
||||
#define NETXEN_ADDR_QDR_NET_MAX (0x00000003003fffffULL)
|
||||
|
||||
/* 200ms delay in each loop */
|
||||
#define NETXEN_NIU_PHY_WAITLEN 200000
|
||||
/* 10 seconds before we give up */
|
||||
#define NETXEN_NIU_PHY_WAITMAX 50
|
||||
#define NETXEN_NIU_MAX_GBE_PORTS 4
|
||||
|
||||
#define NETXEN_NIU_MODE (NETXEN_CRB_NIU + 0x00000)
|
||||
|
||||
#define NETXEN_NIU_XG_SINGLE_TERM (NETXEN_CRB_NIU + 0x00004)
|
||||
#define NETXEN_NIU_XG_DRIVE_HI (NETXEN_CRB_NIU + 0x00008)
|
||||
#define NETXEN_NIU_XG_DRIVE_LO (NETXEN_CRB_NIU + 0x0000c)
|
||||
#define NETXEN_NIU_XG_DTX (NETXEN_CRB_NIU + 0x00010)
|
||||
#define NETXEN_NIU_XG_DEQ (NETXEN_CRB_NIU + 0x00014)
|
||||
#define NETXEN_NIU_XG_WORD_ALIGN (NETXEN_CRB_NIU + 0x00018)
|
||||
#define NETXEN_NIU_XG_RESET (NETXEN_CRB_NIU + 0x0001c)
|
||||
#define NETXEN_NIU_XG_POWER_DOWN (NETXEN_CRB_NIU + 0x00020)
|
||||
#define NETXEN_NIU_XG_RESET_PLL (NETXEN_CRB_NIU + 0x00024)
|
||||
#define NETXEN_NIU_XG_SERDES_LOOPBACK (NETXEN_CRB_NIU + 0x00028)
|
||||
#define NETXEN_NIU_XG_DO_BYTE_ALIGN (NETXEN_CRB_NIU + 0x0002c)
|
||||
#define NETXEN_NIU_XG_TX_ENABLE (NETXEN_CRB_NIU + 0x00030)
|
||||
#define NETXEN_NIU_XG_RX_ENABLE (NETXEN_CRB_NIU + 0x00034)
|
||||
#define NETXEN_NIU_XG_STATUS (NETXEN_CRB_NIU + 0x00038)
|
||||
#define NETXEN_NIU_XG_PAUSE_THRESHOLD (NETXEN_CRB_NIU + 0x0003c)
|
||||
#define NETXEN_NIU_INT_MASK (NETXEN_CRB_NIU + 0x00040)
|
||||
#define NETXEN_NIU_ACTIVE_INT (NETXEN_CRB_NIU + 0x00044)
|
||||
#define NETXEN_NIU_MASKABLE_INT (NETXEN_CRB_NIU + 0x00048)
|
||||
|
||||
#define NETXEN_NIU_STRAP_VALUE_SAVE_HIGHER (NETXEN_CRB_NIU + 0x0004c)
|
||||
|
||||
#define NETXEN_NIU_GB_SERDES_RESET (NETXEN_CRB_NIU + 0x00050)
|
||||
#define NETXEN_NIU_GB0_GMII_MODE (NETXEN_CRB_NIU + 0x00054)
|
||||
#define NETXEN_NIU_GB0_MII_MODE (NETXEN_CRB_NIU + 0x00058)
|
||||
#define NETXEN_NIU_GB1_GMII_MODE (NETXEN_CRB_NIU + 0x0005c)
|
||||
#define NETXEN_NIU_GB1_MII_MODE (NETXEN_CRB_NIU + 0x00060)
|
||||
#define NETXEN_NIU_GB2_GMII_MODE (NETXEN_CRB_NIU + 0x00064)
|
||||
#define NETXEN_NIU_GB2_MII_MODE (NETXEN_CRB_NIU + 0x00068)
|
||||
#define NETXEN_NIU_GB3_GMII_MODE (NETXEN_CRB_NIU + 0x0006c)
|
||||
#define NETXEN_NIU_GB3_MII_MODE (NETXEN_CRB_NIU + 0x00070)
|
||||
#define NETXEN_NIU_REMOTE_LOOPBACK (NETXEN_CRB_NIU + 0x00074)
|
||||
#define NETXEN_NIU_GB0_HALF_DUPLEX (NETXEN_CRB_NIU + 0x00078)
|
||||
#define NETXEN_NIU_GB1_HALF_DUPLEX (NETXEN_CRB_NIU + 0x0007c)
|
||||
#define NETXEN_NIU_RESET_SYS_FIFOS (NETXEN_CRB_NIU + 0x00088)
|
||||
#define NETXEN_NIU_GB_CRC_DROP (NETXEN_CRB_NIU + 0x0008c)
|
||||
#define NETXEN_NIU_GB_DROP_WRONGADDR (NETXEN_CRB_NIU + 0x00090)
|
||||
#define NETXEN_NIU_TEST_MUX_CTL (NETXEN_CRB_NIU + 0x00094)
|
||||
#define NETXEN_NIU_XG_PAUSE_CTL (NETXEN_CRB_NIU + 0x00098)
|
||||
#define NETXEN_NIU_XG_PAUSE_LEVEL (NETXEN_CRB_NIU + 0x000dc)
|
||||
#define NETXEN_NIU_XG_SEL (NETXEN_CRB_NIU + 0x00128)
|
||||
|
||||
#define NETXEN_MAC_ADDR_CNTL_REG (NETXEN_CRB_NIU + 0x1000)
|
||||
|
||||
#define NETXEN_MULTICAST_ADDR_HI_0 (NETXEN_CRB_NIU + 0x1010)
|
||||
#define NETXEN_MULTICAST_ADDR_HI_1 (NETXEN_CRB_NIU + 0x1014)
|
||||
#define NETXEN_MULTICAST_ADDR_HI_2 (NETXEN_CRB_NIU + 0x1018)
|
||||
#define NETXEN_MULTICAST_ADDR_HI_3 (NETXEN_CRB_NIU + 0x101c)
|
||||
|
||||
#define NETXEN_NIU_GB_MAC_CONFIG_0(I) \
|
||||
(NETXEN_CRB_NIU + 0x30000 + (I)*0x10000)
|
||||
#define NETXEN_NIU_GB_MAC_CONFIG_1(I) \
|
||||
(NETXEN_CRB_NIU + 0x30004 + (I)*0x10000)
|
||||
#define NETXEN_NIU_GB_MAC_IPG_IFG(I) \
|
||||
(NETXEN_CRB_NIU + 0x30008 + (I)*0x10000)
|
||||
#define NETXEN_NIU_GB_HALF_DUPLEX_CTRL(I) \
|
||||
(NETXEN_CRB_NIU + 0x3000c + (I)*0x10000)
|
||||
#define NETXEN_NIU_GB_MAX_FRAME_SIZE(I) \
|
||||
(NETXEN_CRB_NIU + 0x30010 + (I)*0x10000)
|
||||
#define NETXEN_NIU_GB_TEST_REG(I) \
|
||||
(NETXEN_CRB_NIU + 0x3001c + (I)*0x10000)
|
||||
#define NETXEN_NIU_GB_MII_MGMT_CONFIG(I) \
|
||||
(NETXEN_CRB_NIU + 0x30020 + (I)*0x10000)
|
||||
#define NETXEN_NIU_GB_MII_MGMT_COMMAND(I) \
|
||||
(NETXEN_CRB_NIU + 0x30024 + (I)*0x10000)
|
||||
#define NETXEN_NIU_GB_MII_MGMT_ADDR(I) \
|
||||
(NETXEN_CRB_NIU + 0x30028 + (I)*0x10000)
|
||||
#define NETXEN_NIU_GB_MII_MGMT_CTRL(I) \
|
||||
(NETXEN_CRB_NIU + 0x3002c + (I)*0x10000)
|
||||
#define NETXEN_NIU_GB_MII_MGMT_STATUS(I) \
|
||||
(NETXEN_CRB_NIU + 0x30030 + (I)*0x10000)
|
||||
#define NETXEN_NIU_GB_MII_MGMT_INDICATE(I) \
|
||||
(NETXEN_CRB_NIU + 0x30034 + (I)*0x10000)
|
||||
#define NETXEN_NIU_GB_INTERFACE_CTRL(I) \
|
||||
(NETXEN_CRB_NIU + 0x30038 + (I)*0x10000)
|
||||
#define NETXEN_NIU_GB_INTERFACE_STATUS(I) \
|
||||
(NETXEN_CRB_NIU + 0x3003c + (I)*0x10000)
|
||||
#define NETXEN_NIU_GB_STATION_ADDR_0(I) \
|
||||
(NETXEN_CRB_NIU + 0x30040 + (I)*0x10000)
|
||||
#define NETXEN_NIU_GB_STATION_ADDR_1(I) \
|
||||
(NETXEN_CRB_NIU + 0x30044 + (I)*0x10000)
|
||||
|
||||
#define NETXEN_NIU_XGE_CONFIG_0 (NETXEN_CRB_NIU + 0x70000)
|
||||
#define NETXEN_NIU_XGE_CONFIG_1 (NETXEN_CRB_NIU + 0x70004)
|
||||
#define NETXEN_NIU_XGE_IPG (NETXEN_CRB_NIU + 0x70008)
|
||||
#define NETXEN_NIU_XGE_STATION_ADDR_0_HI (NETXEN_CRB_NIU + 0x7000c)
|
||||
#define NETXEN_NIU_XGE_STATION_ADDR_0_1 (NETXEN_CRB_NIU + 0x70010)
|
||||
#define NETXEN_NIU_XGE_STATION_ADDR_1_LO (NETXEN_CRB_NIU + 0x70014)
|
||||
#define NETXEN_NIU_XGE_STATUS (NETXEN_CRB_NIU + 0x70018)
|
||||
#define NETXEN_NIU_XGE_MAX_FRAME_SIZE (NETXEN_CRB_NIU + 0x7001c)
|
||||
#define NETXEN_NIU_XGE_PAUSE_FRAME_VALUE (NETXEN_CRB_NIU + 0x70020)
|
||||
#define NETXEN_NIU_XGE_TX_BYTE_CNT (NETXEN_CRB_NIU + 0x70024)
|
||||
#define NETXEN_NIU_XGE_TX_FRAME_CNT (NETXEN_CRB_NIU + 0x70028)
|
||||
#define NETXEN_NIU_XGE_RX_BYTE_CNT (NETXEN_CRB_NIU + 0x7002c)
|
||||
#define NETXEN_NIU_XGE_RX_FRAME_CNT (NETXEN_CRB_NIU + 0x70030)
|
||||
#define NETXEN_NIU_XGE_AGGR_ERROR_CNT (NETXEN_CRB_NIU + 0x70034)
|
||||
#define NETXEN_NIU_XGE_MULTICAST_FRAME_CNT (NETXEN_CRB_NIU + 0x70038)
|
||||
#define NETXEN_NIU_XGE_UNICAST_FRAME_CNT (NETXEN_CRB_NIU + 0x7003c)
|
||||
#define NETXEN_NIU_XGE_CRC_ERROR_CNT (NETXEN_CRB_NIU + 0x70040)
|
||||
#define NETXEN_NIU_XGE_OVERSIZE_FRAME_ERR (NETXEN_CRB_NIU + 0x70044)
|
||||
#define NETXEN_NIU_XGE_UNDERSIZE_FRAME_ERR (NETXEN_CRB_NIU + 0x70048)
|
||||
#define NETXEN_NIU_XGE_LOCAL_ERROR_CNT (NETXEN_CRB_NIU + 0x7004c)
|
||||
#define NETXEN_NIU_XGE_REMOTE_ERROR_CNT (NETXEN_CRB_NIU + 0x70050)
|
||||
#define NETXEN_NIU_XGE_CONTROL_CHAR_CNT (NETXEN_CRB_NIU + 0x70054)
|
||||
#define NETXEN_NIU_XGE_PAUSE_FRAME_CNT (NETXEN_CRB_NIU + 0x70058)
|
||||
|
||||
/* XG Link status */
|
||||
#define XG_LINK_UP 0x10
|
||||
#define XG_LINK_DOWN 0x20
|
||||
|
||||
#define NETXEN_CAM_RAM_BASE (NETXEN_CRB_CAM + 0x02000)
|
||||
#define NETXEN_CAM_RAM(reg) (NETXEN_CAM_RAM_BASE + (reg))
|
||||
#define NETXEN_FW_VERSION_MAJOR (NETXEN_CAM_RAM(0x150))
|
||||
#define NETXEN_FW_VERSION_MINOR (NETXEN_CAM_RAM(0x154))
|
||||
#define NETXEN_FW_VERSION_SUB (NETXEN_CAM_RAM(0x158))
|
||||
#define NETXEN_ROM_LOCK_ID (NETXEN_CAM_RAM(0x100))
|
||||
|
||||
#define PCIX_PS_OP_ADDR_LO (0x10000) /* Used for PS PCI Memory access */
|
||||
#define PCIX_PS_OP_ADDR_HI (0x10004) /* via CRB (PS side only) */
|
||||
|
||||
#define PCIX_INT_VECTOR (0x10100)
|
||||
#define PCIX_INT_MASK (0x10104)
|
||||
|
||||
#define PCIX_MN_WINDOW (0x10200)
|
||||
#define PCIX_MS_WINDOW (0x10204)
|
||||
#define PCIX_SN_WINDOW (0x10208)
|
||||
#define PCIX_CRB_WINDOW (0x10210)
|
||||
|
||||
#define PCIX_TARGET_STATUS (0x10118)
|
||||
#define PCIX_TARGET_MASK (0x10128)
|
||||
|
||||
#define PCIX_MSI_F0 (0x13000)
|
||||
|
||||
#define PCIX_PS_MEM_SPACE (0x90000)
|
||||
|
||||
#define NETXEN_PCIX_PH_REG(reg) (NETXEN_CRB_PCIE + (reg))
|
||||
#define NETXEN_PCIX_PS_REG(reg) (NETXEN_CRB_PCIX_MD + (reg))
|
||||
|
||||
#define NETXEN_PCIE_REG(reg) (NETXEN_CRB_PCIE + (reg))
|
||||
|
||||
#define PCIE_MAX_DMA_XFER_SIZE (0x1404c)
|
||||
|
||||
#define PCIE_DCR 0x00d8
|
||||
|
||||
#define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */
|
||||
#define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */
|
||||
|
||||
#define PCIE_TGT_SPLIT_CHICKEN (0x12080)
|
||||
|
||||
#define PCIE_MAX_MASTER_SPLIT (0x14048)
|
||||
|
||||
#endif /* __NETXEN_NIC_HDR_H_ */
|
||||
|
|
@ -0,0 +1,936 @@
|
|||
/*
|
||||
* Copyright (C) 2003 - 2006 NetXen, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston,
|
||||
* MA 02111-1307, USA.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution
|
||||
* in the file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* info@netxen.com
|
||||
* NetXen,
|
||||
* 3965 Freedom Circle, Fourth floor,
|
||||
* Santa Clara, CA 95054
|
||||
*
|
||||
*
|
||||
* Source file for NIC routines to access the Phantom hardware
|
||||
*
|
||||
*/
|
||||
|
||||
#include "netxen_nic.h"
|
||||
#include "netxen_nic_hw.h"
|
||||
#include "netxen_nic_phan_reg.h"
|
||||
|
||||
/* PCI Windowing for DDR regions. */
|
||||
|
||||
#define ADDR_IN_RANGE(addr, low, high) \
|
||||
(((addr) <= (high)) && ((addr) >= (low)))
|
||||
|
||||
#define NETXEN_FLASH_BASE (BOOTLD_START)
|
||||
#define NETXEN_PHANTOM_MEM_BASE (NETXEN_FLASH_BASE)
|
||||
#define NETXEN_MAX_MTU 8000
|
||||
#define NETXEN_MIN_MTU 64
|
||||
#define NETXEN_ETH_FCS_SIZE 4
|
||||
#define NETXEN_ENET_HEADER_SIZE 14
|
||||
#define NETXEN_WINDOW_ONE 0x2000000 /* CRB Window: bit 25 of CRB address */
|
||||
#define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4)
|
||||
#define NETXEN_NIU_HDRSIZE (0x1 << 6)
|
||||
#define NETXEN_NIU_TLRSIZE (0x1 << 5)
|
||||
|
||||
unsigned long netxen_nic_pci_set_window(void __iomem * pci_base,
|
||||
unsigned long long addr);
|
||||
void netxen_free_hw_resources(struct netxen_adapter *adapter);
|
||||
|
||||
int netxen_nic_set_mac(struct net_device *netdev, void *p)
|
||||
{
|
||||
struct netxen_port *port = netdev_priv(netdev);
|
||||
struct netxen_adapter *adapter = port->adapter;
|
||||
struct sockaddr *addr = p;
|
||||
|
||||
if (netif_running(netdev))
|
||||
return -EBUSY;
|
||||
|
||||
if (!is_valid_ether_addr(addr->sa_data))
|
||||
return -EADDRNOTAVAIL;
|
||||
|
||||
DPRINTK(INFO, "valid ether addr\n");
|
||||
memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
|
||||
|
||||
if (adapter->ops->macaddr_set)
|
||||
adapter->ops->macaddr_set(port, addr->sa_data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* netxen_nic_set_multi - Multicast
|
||||
*/
|
||||
void netxen_nic_set_multi(struct net_device *netdev)
|
||||
{
|
||||
struct netxen_port *port = netdev_priv(netdev);
|
||||
struct netxen_adapter *adapter = port->adapter;
|
||||
struct dev_mc_list *mc_ptr;
|
||||
__le32 netxen_mac_addr_cntl_data = 0;
|
||||
|
||||
mc_ptr = netdev->mc_list;
|
||||
if (netdev->flags & IFF_PROMISC) {
|
||||
if (adapter->ops->set_promisc)
|
||||
adapter->ops->set_promisc(adapter,
|
||||
port->portnum,
|
||||
NETXEN_NIU_PROMISC_MODE);
|
||||
} else {
|
||||
if (adapter->ops->unset_promisc)
|
||||
adapter->ops->unset_promisc(adapter,
|
||||
port->portnum,
|
||||
NETXEN_NIU_NON_PROMISC_MODE);
|
||||
}
|
||||
if (adapter->ahw.board_type == NETXEN_NIC_XGBE) {
|
||||
netxen_nic_mcr_set_mode_select(netxen_mac_addr_cntl_data, 0x03);
|
||||
netxen_nic_mcr_set_id_pool0(netxen_mac_addr_cntl_data, 0x00);
|
||||
netxen_nic_mcr_set_id_pool1(netxen_mac_addr_cntl_data, 0x00);
|
||||
netxen_nic_mcr_set_id_pool2(netxen_mac_addr_cntl_data, 0x00);
|
||||
netxen_nic_mcr_set_id_pool3(netxen_mac_addr_cntl_data, 0x00);
|
||||
netxen_nic_mcr_set_enable_xtnd0(netxen_mac_addr_cntl_data);
|
||||
netxen_nic_mcr_set_enable_xtnd1(netxen_mac_addr_cntl_data);
|
||||
netxen_nic_mcr_set_enable_xtnd2(netxen_mac_addr_cntl_data);
|
||||
netxen_nic_mcr_set_enable_xtnd3(netxen_mac_addr_cntl_data);
|
||||
} else {
|
||||
netxen_nic_mcr_set_mode_select(netxen_mac_addr_cntl_data, 0x00);
|
||||
netxen_nic_mcr_set_id_pool0(netxen_mac_addr_cntl_data, 0x00);
|
||||
netxen_nic_mcr_set_id_pool1(netxen_mac_addr_cntl_data, 0x01);
|
||||
netxen_nic_mcr_set_id_pool2(netxen_mac_addr_cntl_data, 0x02);
|
||||
netxen_nic_mcr_set_id_pool3(netxen_mac_addr_cntl_data, 0x03);
|
||||
}
|
||||
writel(netxen_mac_addr_cntl_data,
|
||||
NETXEN_CRB_NORMALIZE(adapter, NETXEN_MAC_ADDR_CNTL_REG));
|
||||
if (adapter->ahw.board_type == NETXEN_NIC_XGBE) {
|
||||
writel(netxen_mac_addr_cntl_data,
|
||||
NETXEN_CRB_NORMALIZE(adapter,
|
||||
NETXEN_MULTICAST_ADDR_HI_0));
|
||||
} else {
|
||||
writel(netxen_mac_addr_cntl_data,
|
||||
NETXEN_CRB_NORMALIZE(adapter,
|
||||
NETXEN_MULTICAST_ADDR_HI_1));
|
||||
}
|
||||
netxen_mac_addr_cntl_data = 0;
|
||||
writel(netxen_mac_addr_cntl_data,
|
||||
NETXEN_CRB_NORMALIZE(adapter, NETXEN_NIU_GB_DROP_WRONGADDR));
|
||||
}
|
||||
|
||||
/*
|
||||
* netxen_nic_change_mtu - Change the Maximum Transfer Unit
|
||||
* @returns 0 on success, negative on failure
|
||||
*/
|
||||
int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
|
||||
{
|
||||
struct netxen_port *port = netdev_priv(netdev);
|
||||
struct netxen_adapter *adapter = port->adapter;
|
||||
int eff_mtu = mtu + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE;
|
||||
|
||||
if ((eff_mtu > NETXEN_MAX_MTU) || (eff_mtu < NETXEN_MIN_MTU)) {
|
||||
printk(KERN_ERR "%s: %s %d is not supported.\n",
|
||||
netxen_nic_driver_name, netdev->name, mtu);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (adapter->ops->set_mtu)
|
||||
adapter->ops->set_mtu(port, mtu);
|
||||
netdev->mtu = mtu;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* check if the firmware has been downloaded and ready to run and
|
||||
* setup the address for the descriptors in the adapter
|
||||
*/
|
||||
int netxen_nic_hw_resources(struct netxen_adapter *adapter)
|
||||
{
|
||||
struct netxen_hardware_context *hw = &adapter->ahw;
|
||||
int i;
|
||||
u32 state = 0;
|
||||
void *addr;
|
||||
int loops = 0, err = 0;
|
||||
int ctx, ring;
|
||||
u32 card_cmdring = 0;
|
||||
struct netxen_rcv_desc_crb *rcv_desc_crb = NULL;
|
||||
struct netxen_recv_context *recv_ctx;
|
||||
struct netxen_rcv_desc_ctx *rcv_desc;
|
||||
struct cmd_desc_type0 *pcmd;
|
||||
|
||||
DPRINTK(INFO, "pci_base: %lx\n", adapter->ahw.pci_base);
|
||||
DPRINTK(INFO, "crb_base: %lx %lx", NETXEN_PCI_CRBSPACE,
|
||||
adapter->ahw.pci_base + NETXEN_PCI_CRBSPACE);
|
||||
DPRINTK(INFO, "cam base: %lx %lx", NETXEN_CRB_CAM,
|
||||
adapter->ahw.pci_base + NETXEN_CRB_CAM);
|
||||
DPRINTK(INFO, "cam RAM: %lx %lx", NETXEN_CAM_RAM_BASE,
|
||||
adapter->ahw.pci_base + NETXEN_CAM_RAM_BASE);
|
||||
DPRINTK(INFO, "NIC base:%lx %lx\n", NIC_CRB_BASE_PORT1,
|
||||
adapter->ahw.pci_base + NIC_CRB_BASE_PORT1);
|
||||
|
||||
/* Window 1 call */
|
||||
card_cmdring = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_CMDRING));
|
||||
|
||||
DPRINTK(INFO, "Command Peg sends 0x%x for cmdring base\n",
|
||||
card_cmdring);
|
||||
|
||||
for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
|
||||
DPRINTK(INFO, "Command Peg ready..waiting for rcv peg\n");
|
||||
loops = 0;
|
||||
state = 0;
|
||||
/* Window 1 call */
|
||||
state = readl(NETXEN_CRB_NORMALIZE(adapter,
|
||||
recv_crb_registers[ctx].
|
||||
crb_rcvpeg_state));
|
||||
while (state != PHAN_PEG_RCV_INITIALIZED && loops < 20) {
|
||||
udelay(100);
|
||||
/* Window 1 call */
|
||||
state = readl(NETXEN_CRB_NORMALIZE(adapter,
|
||||
recv_crb_registers
|
||||
[ctx].
|
||||
crb_rcvpeg_state));
|
||||
loops++;
|
||||
}
|
||||
if (loops >= 20) {
|
||||
printk(KERN_ERR "Rcv Peg initialization not complete:"
|
||||
"%x.\n", state);
|
||||
err = -EIO;
|
||||
return err;
|
||||
}
|
||||
}
|
||||
DPRINTK(INFO, "Recieve Peg ready too. starting stuff\n");
|
||||
|
||||
addr = pci_alloc_consistent(adapter->ahw.pdev,
|
||||
sizeof(struct cmd_desc_type0) *
|
||||
adapter->max_tx_desc_count,
|
||||
&hw->cmd_desc_phys_addr);
|
||||
if (addr == NULL) {
|
||||
DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
|
||||
err = -ENOMEM;
|
||||
return err;
|
||||
}
|
||||
|
||||
/* we need to prelink all of the cmd descriptors */
|
||||
pcmd = (struct cmd_desc_type0 *)addr;
|
||||
for (i = 1; i < adapter->max_tx_desc_count; i++) {
|
||||
pcmd->netxen_next =
|
||||
(card_cmdring + i * sizeof(struct cmd_desc_type0));
|
||||
pcmd++;
|
||||
}
|
||||
/* fill in last link (point to first) */
|
||||
pcmd->netxen_next = card_cmdring;
|
||||
|
||||
hw->cmd_desc_head = (struct cmd_desc_type0 *)addr;
|
||||
|
||||
for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
|
||||
recv_ctx = &adapter->recv_ctx[ctx];
|
||||
|
||||
for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
|
||||
rcv_desc = &recv_ctx->rcv_desc[ring];
|
||||
addr = pci_alloc_consistent(adapter->ahw.pdev,
|
||||
RCV_DESC_RINGSIZE,
|
||||
&rcv_desc->phys_addr);
|
||||
if (addr == NULL) {
|
||||
DPRINTK(ERR, "bad return from "
|
||||
"pci_alloc_consistent\n");
|
||||
netxen_free_hw_resources(adapter);
|
||||
err = -ENOMEM;
|
||||
return err;
|
||||
}
|
||||
rcv_desc->desc_head = (struct rcv_desc *)addr;
|
||||
}
|
||||
|
||||
addr = pci_alloc_consistent(adapter->ahw.pdev,
|
||||
STATUS_DESC_RINGSIZE,
|
||||
&recv_ctx->
|
||||
rcv_status_desc_phys_addr);
|
||||
if (addr == NULL) {
|
||||
DPRINTK(ERR, "bad return from"
|
||||
" pci_alloc_consistent\n");
|
||||
netxen_free_hw_resources(adapter);
|
||||
err = -ENOMEM;
|
||||
return err;
|
||||
}
|
||||
recv_ctx->rcv_status_desc_head = (struct status_desc *)addr;
|
||||
for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
|
||||
rcv_desc = &recv_ctx->rcv_desc[ring];
|
||||
rcv_desc_crb =
|
||||
&recv_crb_registers[ctx].rcv_desc_crb[ring];
|
||||
DPRINTK(INFO, "ring #%d crb global ring reg 0x%x\n",
|
||||
ring, rcv_desc_crb->crb_globalrcv_ring);
|
||||
/* Window = 1 */
|
||||
writel(rcv_desc->phys_addr,
|
||||
NETXEN_CRB_NORMALIZE(adapter,
|
||||
rcv_desc_crb->
|
||||
crb_globalrcv_ring));
|
||||
DPRINTK(INFO, "GLOBAL_RCV_RING ctx %d, addr 0x%x"
|
||||
" val 0x%x,"
|
||||
" virt %p\n", ctx,
|
||||
rcv_desc_crb->crb_globalrcv_ring,
|
||||
rcv_desc->phys_addr, rcv_desc->desc_head);
|
||||
}
|
||||
|
||||
/* Window = 1 */
|
||||
writel(recv_ctx->rcv_status_desc_phys_addr,
|
||||
NETXEN_CRB_NORMALIZE(adapter,
|
||||
recv_crb_registers[ctx].
|
||||
crb_rcvstatus_ring));
|
||||
DPRINTK(INFO, "RCVSTATUS_RING, ctx %d, addr 0x%x,"
|
||||
" val 0x%x,virt%p\n",
|
||||
ctx,
|
||||
recv_crb_registers[ctx].crb_rcvstatus_ring,
|
||||
recv_ctx->rcv_status_desc_phys_addr,
|
||||
recv_ctx->rcv_status_desc_head);
|
||||
}
|
||||
/* Window = 1 */
|
||||
writel(hw->cmd_desc_phys_addr,
|
||||
NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_CMD_ADDR_LO));
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
void netxen_free_hw_resources(struct netxen_adapter *adapter)
|
||||
{
|
||||
struct netxen_recv_context *recv_ctx;
|
||||
struct netxen_rcv_desc_ctx *rcv_desc;
|
||||
int ctx, ring;
|
||||
|
||||
if (adapter->ahw.cmd_desc_head != NULL) {
|
||||
pci_free_consistent(adapter->ahw.pdev,
|
||||
sizeof(struct cmd_desc_type0) *
|
||||
adapter->max_tx_desc_count,
|
||||
adapter->ahw.cmd_desc_head,
|
||||
adapter->ahw.cmd_desc_phys_addr);
|
||||
adapter->ahw.cmd_desc_head = NULL;
|
||||
}
|
||||
|
||||
for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
|
||||
recv_ctx = &adapter->recv_ctx[ctx];
|
||||
for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
|
||||
rcv_desc = &recv_ctx->rcv_desc[ring];
|
||||
|
||||
if (rcv_desc->desc_head != NULL) {
|
||||
pci_free_consistent(adapter->ahw.pdev,
|
||||
RCV_DESC_RINGSIZE,
|
||||
rcv_desc->desc_head,
|
||||
rcv_desc->phys_addr);
|
||||
rcv_desc->desc_head = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
if (recv_ctx->rcv_status_desc_head != NULL) {
|
||||
pci_free_consistent(adapter->ahw.pdev,
|
||||
STATUS_DESC_RINGSIZE,
|
||||
recv_ctx->rcv_status_desc_head,
|
||||
recv_ctx->
|
||||
rcv_status_desc_phys_addr);
|
||||
recv_ctx->rcv_status_desc_head = NULL;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void netxen_tso_check(struct netxen_adapter *adapter,
|
||||
struct cmd_desc_type0 *desc, struct sk_buff *skb)
|
||||
{
|
||||
if (desc->mss) {
|
||||
desc->total_hdr_length = sizeof(struct ethhdr) +
|
||||
((skb->nh.iph)->ihl * sizeof(u32)) +
|
||||
((skb->h.th)->doff * sizeof(u32));
|
||||
desc->opcode = TX_TCP_LSO;
|
||||
} else if (skb->ip_summed == CHECKSUM_HW) {
|
||||
if (skb->nh.iph->protocol == IPPROTO_TCP) {
|
||||
desc->opcode = TX_TCP_PKT;
|
||||
} else if (skb->nh.iph->protocol == IPPROTO_UDP) {
|
||||
desc->opcode = TX_UDP_PKT;
|
||||
} else {
|
||||
return;
|
||||
}
|
||||
}
|
||||
CMD_DESC_TCP_HDR_OFFSET_WRT(desc, skb->h.raw - skb->data);
|
||||
desc->length_tcp_hdr = cpu_to_le32(desc->length_tcp_hdr);
|
||||
desc->ip_hdr_offset = skb->nh.raw - skb->data;
|
||||
adapter->stats.xmitcsummed++;
|
||||
}
|
||||
|
||||
int netxen_is_flash_supported(struct netxen_adapter *adapter)
|
||||
{
|
||||
const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 };
|
||||
int addr, val01, val02, i, j;
|
||||
|
||||
/* if the flash size less than 4Mb, make huge war cry and die */
|
||||
for (j = 1; j < 4; j++) {
|
||||
addr = j * 0x100000;
|
||||
for (i = 0; i < (sizeof(locs) / sizeof(locs[0])); i++) {
|
||||
if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0
|
||||
&& netxen_rom_fast_read(adapter, (addr + locs[i]),
|
||||
&val02) == 0) {
|
||||
if (val01 == val02)
|
||||
return -1;
|
||||
} else
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
|
||||
int size, u32 * buf)
|
||||
{
|
||||
int i, addr;
|
||||
u32 *ptr32;
|
||||
|
||||
addr = base;
|
||||
ptr32 = buf;
|
||||
for (i = 0; i < size / sizeof(u32); i++) {
|
||||
if (netxen_rom_fast_read(adapter, addr, ptr32) == -1)
|
||||
return -1;
|
||||
ptr32++;
|
||||
addr += sizeof(u32);
|
||||
}
|
||||
if ((char *)buf + size > (char *)ptr32) {
|
||||
u32 local;
|
||||
|
||||
if (netxen_rom_fast_read(adapter, addr, &local) == -1)
|
||||
return -1;
|
||||
memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 mac[])
|
||||
{
|
||||
u32 *pmac = (u32 *) & mac[0];
|
||||
|
||||
if (netxen_get_flash_block(adapter,
|
||||
USER_START +
|
||||
offsetof(struct netxen_new_user_info,
|
||||
mac_addr),
|
||||
FLASH_NUM_PORTS * sizeof(u64), pmac) == -1) {
|
||||
return -1;
|
||||
}
|
||||
if (*mac == ~0ULL) {
|
||||
if (netxen_get_flash_block(adapter,
|
||||
USER_START_OLD +
|
||||
offsetof(struct netxen_user_old_info,
|
||||
mac_addr),
|
||||
FLASH_NUM_PORTS * sizeof(u64),
|
||||
pmac) == -1)
|
||||
return -1;
|
||||
if (*mac == ~0ULL)
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Changes the CRB window to the specified window.
|
||||
*/
|
||||
void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw)
|
||||
{
|
||||
void __iomem *offset;
|
||||
u32 tmp;
|
||||
int count = 0;
|
||||
|
||||
if (adapter->curr_window == wndw)
|
||||
return;
|
||||
|
||||
/*
|
||||
* Move the CRB window.
|
||||
* We need to write to the "direct access" region of PCI
|
||||
* to avoid a race condition where the window register has
|
||||
* not been successfully written across CRB before the target
|
||||
* register address is received by PCI. The direct region bypasses
|
||||
* the CRB bus.
|
||||
*/
|
||||
offset = adapter->ahw.pci_base + NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW);
|
||||
|
||||
if (wndw & 0x1)
|
||||
wndw = NETXEN_WINDOW_ONE;
|
||||
|
||||
writel(wndw, offset);
|
||||
|
||||
/* MUST make sure window is set before we forge on... */
|
||||
while ((tmp = readl(offset)) != wndw) {
|
||||
printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
|
||||
"registered properly: 0x%08x.\n",
|
||||
netxen_nic_driver_name, __FUNCTION__, tmp);
|
||||
mdelay(1);
|
||||
if (count >= 10)
|
||||
break;
|
||||
count++;
|
||||
}
|
||||
|
||||
adapter->curr_window = wndw;
|
||||
}
|
||||
|
||||
void netxen_load_firmware(struct netxen_adapter *adapter)
|
||||
{
|
||||
int i;
|
||||
long data, size = 0;
|
||||
long flashaddr = NETXEN_FLASH_BASE, memaddr = NETXEN_PHANTOM_MEM_BASE;
|
||||
u64 off;
|
||||
void __iomem *addr;
|
||||
|
||||
size = NETXEN_FIRMWARE_LEN;
|
||||
writel(1, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0) {
|
||||
DPRINTK(ERR,
|
||||
"Error in netxen_rom_fast_read(). Will skip"
|
||||
"loading flash image\n");
|
||||
return;
|
||||
}
|
||||
off = netxen_nic_pci_set_window(adapter->ahw.pci_base, memaddr);
|
||||
addr = (adapter->ahw.pci_base + off);
|
||||
writel(data, addr);
|
||||
flashaddr += 4;
|
||||
memaddr += 4;
|
||||
}
|
||||
udelay(100);
|
||||
/* make sure Casper is powered on */
|
||||
writel(0x3fff,
|
||||
NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL));
|
||||
writel(0, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
|
||||
|
||||
udelay(100);
|
||||
}
|
||||
|
||||
int
|
||||
netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
|
||||
int len)
|
||||
{
|
||||
void __iomem *addr;
|
||||
|
||||
if (ADDR_IN_WINDOW1(off)) {
|
||||
addr = NETXEN_CRB_NORMALIZE(adapter, off);
|
||||
} else { /* Window 0 */
|
||||
addr = adapter->ahw.pci_base + off;
|
||||
netxen_nic_pci_change_crbwindow(adapter, 0);
|
||||
}
|
||||
|
||||
DPRINTK(INFO, "writing to base %lx offset %llx addr %p"
|
||||
" data %llx len %d\n",
|
||||
adapter->ahw.pci_base, off, addr,
|
||||
*(unsigned long long *)data, len);
|
||||
switch (len) {
|
||||
case 1:
|
||||
writeb(*(u8 *) data, addr);
|
||||
break;
|
||||
case 2:
|
||||
writew(*(u16 *) data, addr);
|
||||
break;
|
||||
case 4:
|
||||
writel(*(u32 *) data, addr);
|
||||
break;
|
||||
case 8:
|
||||
writeq(*(u64 *) data, addr);
|
||||
break;
|
||||
default:
|
||||
DPRINTK(INFO,
|
||||
"writing data %lx to offset %llx, num words=%d\n",
|
||||
*(unsigned long *)data, off, (len >> 3));
|
||||
|
||||
netxen_nic_hw_block_write64((u64 __iomem *) data, addr,
|
||||
(len >> 3));
|
||||
break;
|
||||
}
|
||||
if (!ADDR_IN_WINDOW1(off))
|
||||
netxen_nic_pci_change_crbwindow(adapter, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
|
||||
int len)
|
||||
{
|
||||
void __iomem *addr;
|
||||
|
||||
if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
|
||||
addr = NETXEN_CRB_NORMALIZE(adapter, off);
|
||||
} else { /* Window 0 */
|
||||
addr = adapter->ahw.pci_base + off;
|
||||
netxen_nic_pci_change_crbwindow(adapter, 0);
|
||||
}
|
||||
|
||||
DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
|
||||
adapter->ahw.pci_base, off, addr);
|
||||
switch (len) {
|
||||
case 1:
|
||||
*(u8 *) data = readb(addr);
|
||||
break;
|
||||
case 2:
|
||||
*(u16 *) data = readw(addr);
|
||||
break;
|
||||
case 4:
|
||||
*(u32 *) data = readl(addr);
|
||||
break;
|
||||
case 8:
|
||||
*(u64 *) data = readq(addr);
|
||||
break;
|
||||
default:
|
||||
netxen_nic_hw_block_read64((u64 __iomem *) data, addr,
|
||||
(len >> 3));
|
||||
break;
|
||||
}
|
||||
DPRINTK(INFO, "read %lx\n", *(unsigned long *)data);
|
||||
|
||||
if (!ADDR_IN_WINDOW1(off))
|
||||
netxen_nic_pci_change_crbwindow(adapter, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
|
||||
{ /* Only for window 1 */
|
||||
void __iomem *addr;
|
||||
|
||||
addr = NETXEN_CRB_NORMALIZE(adapter, off);
|
||||
DPRINTK(INFO, "writing to base %lx offset %llx addr %p data %x\n",
|
||||
adapter->ahw.pci_base, off, addr, val);
|
||||
writel(val, addr);
|
||||
|
||||
}
|
||||
|
||||
int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
|
||||
{ /* Only for window 1 */
|
||||
void __iomem *addr;
|
||||
int val;
|
||||
|
||||
addr = NETXEN_CRB_NORMALIZE(adapter, off);
|
||||
DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
|
||||
adapter->ahw.pci_base, off, addr);
|
||||
val = readl(addr);
|
||||
writel(val, addr);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
/* Change the window to 0, write and change back to window 1. */
|
||||
void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
|
||||
{
|
||||
void __iomem *addr;
|
||||
|
||||
netxen_nic_pci_change_crbwindow(adapter, 0);
|
||||
addr = (void __iomem *)(adapter->ahw.pci_base + index);
|
||||
writel(value, addr);
|
||||
netxen_nic_pci_change_crbwindow(adapter, 1);
|
||||
}
|
||||
|
||||
/* Change the window to 0, read and change back to window 1. */
|
||||
void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value)
|
||||
{
|
||||
void __iomem *addr;
|
||||
|
||||
addr = (void __iomem *)(adapter->ahw.pci_base + index);
|
||||
|
||||
netxen_nic_pci_change_crbwindow(adapter, 0);
|
||||
*value = readl(addr);
|
||||
netxen_nic_pci_change_crbwindow(adapter, 1);
|
||||
}
|
||||
|
||||
int netxen_pci_set_window_warning_count = 0;
|
||||
|
||||
unsigned long
|
||||
netxen_nic_pci_set_window(void __iomem * pci_base, unsigned long long addr)
|
||||
{
|
||||
static int ddr_mn_window = -1;
|
||||
static int qdr_sn_window = -1;
|
||||
int window;
|
||||
|
||||
if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
|
||||
/* DDR network side */
|
||||
addr -= NETXEN_ADDR_DDR_NET;
|
||||
window = (addr >> 25) & 0x3ff;
|
||||
if (ddr_mn_window != window) {
|
||||
ddr_mn_window = window;
|
||||
writel(window, pci_base +
|
||||
NETXEN_PCIX_PH_REG(PCIX_MN_WINDOW));
|
||||
/* MUST make sure window is set before we forge on... */
|
||||
readl(pci_base + NETXEN_PCIX_PH_REG(PCIX_MN_WINDOW));
|
||||
}
|
||||
addr -= (window * 0x2000000);
|
||||
addr += NETXEN_PCI_DDR_NET;
|
||||
} else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
|
||||
addr -= NETXEN_ADDR_OCM0;
|
||||
addr += NETXEN_PCI_OCM0;
|
||||
} else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
|
||||
addr -= NETXEN_ADDR_OCM1;
|
||||
addr += NETXEN_PCI_OCM1;
|
||||
} else
|
||||
if (ADDR_IN_RANGE
|
||||
(addr, NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX)) {
|
||||
/* QDR network side */
|
||||
addr -= NETXEN_ADDR_QDR_NET;
|
||||
window = (addr >> 22) & 0x3f;
|
||||
if (qdr_sn_window != window) {
|
||||
qdr_sn_window = window;
|
||||
writel((window << 22), pci_base +
|
||||
NETXEN_PCIX_PH_REG(PCIX_SN_WINDOW));
|
||||
/* MUST make sure window is set before we forge on... */
|
||||
readl(pci_base + NETXEN_PCIX_PH_REG(PCIX_SN_WINDOW));
|
||||
}
|
||||
addr -= (window * 0x400000);
|
||||
addr += NETXEN_PCI_QDR_NET;
|
||||
} else {
|
||||
/*
|
||||
* peg gdb frequently accesses memory that doesn't exist,
|
||||
* this limits the chit chat so debugging isn't slowed down.
|
||||
*/
|
||||
if ((netxen_pci_set_window_warning_count++ < 8)
|
||||
|| (netxen_pci_set_window_warning_count % 64 == 0))
|
||||
printk("%s: Warning:netxen_nic_pci_set_window()"
|
||||
" Unknown address range!\n",
|
||||
netxen_nic_driver_name);
|
||||
|
||||
}
|
||||
return addr;
|
||||
}
|
||||
|
||||
int netxen_nic_get_board_info(struct netxen_adapter *adapter)
|
||||
{
|
||||
int rv = 0;
|
||||
int addr = BRDCFG_START;
|
||||
struct netxen_board_info *boardinfo;
|
||||
int index;
|
||||
u32 *ptr32;
|
||||
|
||||
boardinfo = &adapter->ahw.boardcfg;
|
||||
ptr32 = (u32 *) boardinfo;
|
||||
|
||||
for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32);
|
||||
index++) {
|
||||
if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
|
||||
return -EIO;
|
||||
}
|
||||
ptr32++;
|
||||
addr += sizeof(u32);
|
||||
}
|
||||
if (boardinfo->magic != NETXEN_BDINFO_MAGIC) {
|
||||
printk("%s: ERROR reading %s board config."
|
||||
" Read %x, expected %x\n", netxen_nic_driver_name,
|
||||
netxen_nic_driver_name,
|
||||
boardinfo->magic, NETXEN_BDINFO_MAGIC);
|
||||
rv = -1;
|
||||
}
|
||||
if (boardinfo->header_version != NETXEN_BDINFO_VERSION) {
|
||||
printk("%s: Unknown board config version."
|
||||
" Read %x, expected %x\n", netxen_nic_driver_name,
|
||||
boardinfo->header_version, NETXEN_BDINFO_VERSION);
|
||||
rv = -1;
|
||||
}
|
||||
|
||||
DPRINTK(INFO, "Discovered board type:0x%x ", boardinfo->board_type);
|
||||
switch ((netxen_brdtype_t) boardinfo->board_type) {
|
||||
case NETXEN_BRDTYPE_P2_SB35_4G:
|
||||
adapter->ahw.board_type = NETXEN_NIC_GBE;
|
||||
break;
|
||||
case NETXEN_BRDTYPE_P2_SB31_10G:
|
||||
case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
|
||||
case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
|
||||
case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
|
||||
adapter->ahw.board_type = NETXEN_NIC_XGBE;
|
||||
break;
|
||||
case NETXEN_BRDTYPE_P1_BD:
|
||||
case NETXEN_BRDTYPE_P1_SB:
|
||||
case NETXEN_BRDTYPE_P1_SMAX:
|
||||
case NETXEN_BRDTYPE_P1_SOCK:
|
||||
adapter->ahw.board_type = NETXEN_NIC_GBE;
|
||||
break;
|
||||
default:
|
||||
printk("%s: Unknown(%x)\n", netxen_nic_driver_name,
|
||||
boardinfo->board_type);
|
||||
break;
|
||||
}
|
||||
|
||||
return rv;
|
||||
}
|
||||
|
||||
/* NIU access sections */
|
||||
|
||||
int netxen_nic_set_mtu_gb(struct netxen_port *port, int new_mtu)
|
||||
{
|
||||
struct netxen_adapter *adapter = port->adapter;
|
||||
netxen_nic_write_w0(adapter,
|
||||
NETXEN_NIU_GB_MAX_FRAME_SIZE(port->portnum),
|
||||
new_mtu);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int netxen_nic_set_mtu_xgb(struct netxen_port *port, int new_mtu)
|
||||
{
|
||||
struct netxen_adapter *adapter = port->adapter;
|
||||
new_mtu += NETXEN_NIU_HDRSIZE + NETXEN_NIU_TLRSIZE;
|
||||
netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void netxen_nic_init_niu_gb(struct netxen_adapter *adapter)
|
||||
{
|
||||
int portno;
|
||||
for (portno = 0; portno < NETXEN_NIU_MAX_GBE_PORTS; portno++)
|
||||
netxen_niu_gbe_init_port(adapter, portno);
|
||||
}
|
||||
|
||||
void netxen_nic_stop_all_ports(struct netxen_adapter *adapter)
|
||||
{
|
||||
int port_nr;
|
||||
struct netxen_port *port;
|
||||
|
||||
for (port_nr = 0; port_nr < adapter->ahw.max_ports; port_nr++) {
|
||||
port = adapter->port[port_nr];
|
||||
if (adapter->ops->stop_port)
|
||||
adapter->ops->stop_port(adapter, port->portnum);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
netxen_crb_writelit_adapter(struct netxen_adapter *adapter, unsigned long off,
|
||||
int data)
|
||||
{
|
||||
void __iomem *addr;
|
||||
|
||||
if (ADDR_IN_WINDOW1(off)) {
|
||||
writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
|
||||
} else {
|
||||
netxen_nic_pci_change_crbwindow(adapter, 0);
|
||||
addr = (void __iomem *)(adapter->ahw.pci_base + off);
|
||||
writel(data, addr);
|
||||
netxen_nic_pci_change_crbwindow(adapter, 1);
|
||||
}
|
||||
}
|
||||
|
||||
void netxen_nic_set_link_parameters(struct netxen_port *port)
|
||||
{
|
||||
struct netxen_adapter *adapter = port->adapter;
|
||||
__le32 status;
|
||||
u16 autoneg;
|
||||
__le32 mode;
|
||||
|
||||
netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode);
|
||||
if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */
|
||||
if (adapter->ops->phy_read
|
||||
&& adapter->ops->
|
||||
phy_read(adapter, port->portnum,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
|
||||
&status) == 0) {
|
||||
if (netxen_get_phy_link(status)) {
|
||||
switch (netxen_get_phy_speed(status)) {
|
||||
case 0:
|
||||
port->link_speed = SPEED_10;
|
||||
break;
|
||||
case 1:
|
||||
port->link_speed = SPEED_100;
|
||||
break;
|
||||
case 2:
|
||||
port->link_speed = SPEED_1000;
|
||||
break;
|
||||
default:
|
||||
port->link_speed = -1;
|
||||
break;
|
||||
}
|
||||
switch (netxen_get_phy_duplex(status)) {
|
||||
case 0:
|
||||
port->link_duplex = DUPLEX_HALF;
|
||||
break;
|
||||
case 1:
|
||||
port->link_duplex = DUPLEX_FULL;
|
||||
break;
|
||||
default:
|
||||
port->link_duplex = -1;
|
||||
break;
|
||||
}
|
||||
if (adapter->ops->phy_read
|
||||
&& adapter->ops->
|
||||
phy_read(adapter, port->portnum,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
|
||||
(__le32 *) & autoneg) != 0)
|
||||
port->link_autoneg = autoneg;
|
||||
} else
|
||||
goto link_down;
|
||||
} else {
|
||||
link_down:
|
||||
port->link_speed = -1;
|
||||
port->link_duplex = -1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void netxen_nic_flash_print(struct netxen_adapter *adapter)
|
||||
{
|
||||
int valid = 1;
|
||||
u32 fw_major = 0;
|
||||
u32 fw_minor = 0;
|
||||
u32 fw_build = 0;
|
||||
|
||||
struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
|
||||
if (board_info->magic != NETXEN_BDINFO_MAGIC) {
|
||||
printk
|
||||
("NetXen Unknown board config, Read 0x%x expected as 0x%x\n",
|
||||
board_info->magic, NETXEN_BDINFO_MAGIC);
|
||||
valid = 0;
|
||||
}
|
||||
if (board_info->header_version != NETXEN_BDINFO_VERSION) {
|
||||
printk("NetXen Unknown board config version."
|
||||
" Read %x, expected %x\n",
|
||||
board_info->header_version, NETXEN_BDINFO_VERSION);
|
||||
valid = 0;
|
||||
}
|
||||
if (valid) {
|
||||
printk("NetXen %s Board #%d, Chip id 0x%x\n",
|
||||
board_info->board_type == 0x0b ? "XGB" : "GBE",
|
||||
board_info->board_num, board_info->chip_id);
|
||||
fw_major = readl(NETXEN_CRB_NORMALIZE(adapter,
|
||||
NETXEN_FW_VERSION_MAJOR));
|
||||
fw_minor = readl(NETXEN_CRB_NORMALIZE(adapter,
|
||||
NETXEN_FW_VERSION_MINOR));
|
||||
fw_build =
|
||||
readl(NETXEN_CRB_NORMALIZE(adapter, NETXEN_FW_VERSION_SUB));
|
||||
|
||||
printk("NetXen Firmware version %d.%d.%d\n", fw_major, fw_minor,
|
||||
fw_build);
|
||||
}
|
||||
if (fw_major != _NETXEN_NIC_LINUX_MAJOR) {
|
||||
printk(KERN_ERR "The mismatch in driver version and firmware "
|
||||
"version major number\n"
|
||||
"Driver version major number = %d \t"
|
||||
"Firmware version major number = %d \n",
|
||||
_NETXEN_NIC_LINUX_MAJOR, fw_major);
|
||||
adapter->driver_mismatch = 1;
|
||||
}
|
||||
if (fw_minor != _NETXEN_NIC_LINUX_MINOR) {
|
||||
printk(KERN_ERR "The mismatch in driver version and firmware "
|
||||
"version minor number\n"
|
||||
"Driver version minor number = %d \t"
|
||||
"Firmware version minor number = %d \n",
|
||||
_NETXEN_NIC_LINUX_MINOR, fw_minor);
|
||||
adapter->driver_mismatch = 1;
|
||||
}
|
||||
if (adapter->driver_mismatch)
|
||||
printk(KERN_INFO "Use the driver with version no %d.%d.xxx\n",
|
||||
fw_major, fw_minor);
|
||||
}
|
||||
|
||||
int netxen_crb_read_val(struct netxen_adapter *adapter, unsigned long off)
|
||||
{
|
||||
int data;
|
||||
netxen_nic_hw_read_wx(adapter, off, &data, 4);
|
||||
return data;
|
||||
}
|
||||
|
|
@ -0,0 +1,480 @@
|
|||
/*
|
||||
* Copyright (C) 2003 - 2006 NetXen, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston,
|
||||
* MA 02111-1307, USA.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution
|
||||
* in the file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* info@netxen.com
|
||||
* NetXen,
|
||||
* 3965 Freedom Circle, Fourth floor,
|
||||
* Santa Clara, CA 95054
|
||||
*
|
||||
*
|
||||
* Structures, enums, and macros for the MAC
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __NETXEN_NIC_HW_H_
|
||||
#define __NETXEN_NIC_HW_H_
|
||||
|
||||
#include "netxen_nic_hdr.h"
|
||||
|
||||
/* Hardware memory size of 128 meg */
|
||||
#define NETXEN_MEMADDR_MAX (128 * 1024 * 1024)
|
||||
|
||||
#ifndef readq
|
||||
static inline u64 readq(void __iomem * addr)
|
||||
{
|
||||
return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef writeq
|
||||
static inline void writeq(u64 val, void __iomem * addr)
|
||||
{
|
||||
writel(((u32) (val)), (addr));
|
||||
writel(((u32) (val >> 32)), (addr + 4));
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline void netxen_nic_hw_block_write64(u64 __iomem * data_ptr,
|
||||
u64 __iomem * addr,
|
||||
int num_words)
|
||||
{
|
||||
int num;
|
||||
for (num = 0; num < num_words; num++) {
|
||||
writeq(readq((void __iomem *)data_ptr), addr);
|
||||
addr++;
|
||||
data_ptr++;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void netxen_nic_hw_block_read64(u64 __iomem * data_ptr,
|
||||
u64 __iomem * addr, int num_words)
|
||||
{
|
||||
int num;
|
||||
for (num = 0; num < num_words; num++) {
|
||||
writeq(readq((void __iomem *)addr), data_ptr);
|
||||
addr++;
|
||||
data_ptr++;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
struct netxen_adapter;
|
||||
|
||||
#define NETXEN_PCI_MAPSIZE_BYTES (NETXEN_PCI_MAPSIZE << 20)
|
||||
|
||||
#define NETXEN_NIC_LOCKED_READ_REG(X, Y) \
|
||||
addr = (adapter->ahw.pci_base + X); \
|
||||
*(u32 *)Y = readl((void __iomem*) addr);
|
||||
|
||||
struct netxen_port;
|
||||
void netxen_nic_set_link_parameters(struct netxen_port *port);
|
||||
void netxen_nic_flash_print(struct netxen_adapter *adapter);
|
||||
int netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off,
|
||||
void *data, int len);
|
||||
void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
|
||||
unsigned long off, int data);
|
||||
int netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off,
|
||||
void *data, int len);
|
||||
|
||||
typedef u8 netxen_ethernet_macaddr_t[6];
|
||||
|
||||
/* Nibble or Byte mode for phy interface (GbE mode only) */
|
||||
typedef enum {
|
||||
NETXEN_NIU_10_100_MB = 0,
|
||||
NETXEN_NIU_1000_MB
|
||||
} netxen_niu_gbe_ifmode_t;
|
||||
|
||||
#define _netxen_crb_get_bit(var, bit) ((var >> bit) & 0x1)
|
||||
|
||||
/*
|
||||
* NIU GB MAC Config Register 0 (applies to GB0, GB1, GB2, GB3)
|
||||
*
|
||||
* Bit 0 : enable_tx => 1:enable frame xmit, 0:disable
|
||||
* Bit 1 : tx_synced => R/O: xmit enable synched to xmit stream
|
||||
* Bit 2 : enable_rx => 1:enable frame recv, 0:disable
|
||||
* Bit 3 : rx_synced => R/O: recv enable synched to recv stream
|
||||
* Bit 4 : tx_flowctl => 1:enable pause frame generation, 0:disable
|
||||
* Bit 5 : rx_flowctl => 1:act on recv'd pause frames, 0:ignore
|
||||
* Bit 8 : loopback => 1:loop MAC xmits to MAC recvs, 0:normal
|
||||
* Bit 16: tx_reset_pb => 1:reset frame xmit protocol blk, 0:no-op
|
||||
* Bit 17: rx_reset_pb => 1:reset frame recv protocol blk, 0:no-op
|
||||
* Bit 18: tx_reset_mac => 1:reset data/ctl multiplexer blk, 0:no-op
|
||||
* Bit 19: rx_reset_mac => 1:reset ctl frames & timers blk, 0:no-op
|
||||
* Bit 31: soft_reset => 1:reset the MAC and the SERDES, 0:no-op
|
||||
*/
|
||||
|
||||
#define netxen_gb_enable_tx(config_word) \
|
||||
set_bit(0, (unsigned long*)(&config_word))
|
||||
#define netxen_gb_enable_rx(config_word) \
|
||||
set_bit(2, (unsigned long*)(&config_word))
|
||||
#define netxen_gb_tx_flowctl(config_word) \
|
||||
set_bit(4, (unsigned long*)(&config_word))
|
||||
#define netxen_gb_rx_flowctl(config_word) \
|
||||
set_bit(5, (unsigned long*)(&config_word))
|
||||
#define netxen_gb_tx_reset_pb(config_word) \
|
||||
set_bit(16, (unsigned long*)(&config_word))
|
||||
#define netxen_gb_rx_reset_pb(config_word) \
|
||||
set_bit(17, (unsigned long*)(&config_word))
|
||||
#define netxen_gb_tx_reset_mac(config_word) \
|
||||
set_bit(18, (unsigned long*)(&config_word))
|
||||
#define netxen_gb_rx_reset_mac(config_word) \
|
||||
set_bit(19, (unsigned long*)(&config_word))
|
||||
#define netxen_gb_soft_reset(config_word) \
|
||||
set_bit(31, (unsigned long*)(&config_word))
|
||||
|
||||
#define netxen_gb_unset_tx_flowctl(config_word) \
|
||||
clear_bit(4, (unsigned long *)(&config_word))
|
||||
#define netxen_gb_unset_rx_flowctl(config_word) \
|
||||
clear_bit(5, (unsigned long*)(&config_word))
|
||||
|
||||
#define netxen_gb_get_tx_synced(config_word) \
|
||||
_netxen_crb_get_bit((config_word), 1)
|
||||
#define netxen_gb_get_rx_synced(config_word) \
|
||||
_netxen_crb_get_bit((config_word), 3)
|
||||
#define netxen_gb_get_tx_flowctl(config_word) \
|
||||
_netxen_crb_get_bit((config_word), 4)
|
||||
#define netxen_gb_get_rx_flowctl(config_word) \
|
||||
_netxen_crb_get_bit((config_word), 5)
|
||||
#define netxen_gb_get_soft_reset(config_word) \
|
||||
_netxen_crb_get_bit((config_word), 31)
|
||||
|
||||
/*
|
||||
* NIU GB MAC Config Register 1 (applies to GB0, GB1, GB2, GB3)
|
||||
*
|
||||
* Bit 0 : duplex => 1:full duplex mode, 0:half duplex
|
||||
* Bit 1 : crc_enable => 1:append CRC to xmit frames, 0:dont append
|
||||
* Bit 2 : padshort => 1:pad short frames and add CRC, 0:dont pad
|
||||
* Bit 4 : checklength => 1:check framelen with actual,0:dont check
|
||||
* Bit 5 : hugeframes => 1:allow oversize xmit frames, 0:dont allow
|
||||
* Bits 8-9 : intfmode => 01:nibble (10/100), 10:byte (1000)
|
||||
* Bits 12-15 : preamblelen => preamble field length in bytes, default 7
|
||||
*/
|
||||
|
||||
#define netxen_gb_set_duplex(config_word) \
|
||||
set_bit(0, (unsigned long*)&config_word)
|
||||
#define netxen_gb_set_crc_enable(config_word) \
|
||||
set_bit(1, (unsigned long*)&config_word)
|
||||
#define netxen_gb_set_padshort(config_word) \
|
||||
set_bit(2, (unsigned long*)&config_word)
|
||||
#define netxen_gb_set_checklength(config_word) \
|
||||
set_bit(4, (unsigned long*)&config_word)
|
||||
#define netxen_gb_set_hugeframes(config_word) \
|
||||
set_bit(5, (unsigned long*)&config_word)
|
||||
#define netxen_gb_set_preamblelen(config_word, val) \
|
||||
((config_word) |= ((val) << 12) & 0xF000)
|
||||
#define netxen_gb_set_intfmode(config_word, val) \
|
||||
((config_word) |= ((val) << 8) & 0x300)
|
||||
|
||||
#define netxen_gb_get_stationaddress_low(config_word) ((config_word) >> 16)
|
||||
|
||||
#define netxen_gb_set_mii_mgmt_clockselect(config_word, val) \
|
||||
((config_word) |= ((val) & 0x07))
|
||||
#define netxen_gb_mii_mgmt_reset(config_word) \
|
||||
set_bit(31, (unsigned long*)&config_word)
|
||||
#define netxen_gb_mii_mgmt_unset(config_word) \
|
||||
clear_bit(31, (unsigned long*)&config_word)
|
||||
|
||||
/*
|
||||
* NIU GB MII Mgmt Command Register (applies to GB0, GB1, GB2, GB3)
|
||||
* Bit 0 : read_cycle => 1:perform single read cycle, 0:no-op
|
||||
* Bit 1 : scan_cycle => 1:perform continuous read cycles, 0:no-op
|
||||
*/
|
||||
|
||||
#define netxen_gb_mii_mgmt_set_read_cycle(config_word) \
|
||||
set_bit(0, (unsigned long*)&config_word)
|
||||
#define netxen_gb_mii_mgmt_reg_addr(config_word, val) \
|
||||
((config_word) |= ((val) & 0x1F))
|
||||
#define netxen_gb_mii_mgmt_phy_addr(config_word, val) \
|
||||
((config_word) |= (((val) & 0x1F) << 8))
|
||||
|
||||
/*
|
||||
* NIU GB MII Mgmt Indicators Register (applies to GB0, GB1, GB2, GB3)
|
||||
* Read-only register.
|
||||
* Bit 0 : busy => 1:performing an MII mgmt cycle, 0:idle
|
||||
* Bit 1 : scanning => 1:scan operation in progress, 0:idle
|
||||
* Bit 2 : notvalid => :mgmt result data not yet valid, 0:idle
|
||||
*/
|
||||
#define netxen_get_gb_mii_mgmt_busy(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 0)
|
||||
#define netxen_get_gb_mii_mgmt_scanning(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 1)
|
||||
#define netxen_get_gb_mii_mgmt_notvalid(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 2)
|
||||
|
||||
/*
|
||||
* PHY-Specific MII control/status registers.
|
||||
*/
|
||||
typedef enum {
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_CONTROL = 0,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_STATUS = 1,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_0 = 2,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_1 = 3,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG = 4,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART = 5,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG_MORE = 6,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_NEXTPAGE_XMIT = 7,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART_NEXTPAGE = 8,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_CONTROL = 9,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_STATUS = 10,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_EXTENDED_STATUS = 15,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL = 16,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS = 17,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE = 18,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS = 19,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE = 20,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_RECV_ERROR_COUNT = 21,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_LED_CONTROL = 24,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_LED_OVERRIDE = 25,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE_YET = 26,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS_MORE = 27
|
||||
} netxen_niu_phy_register_t;
|
||||
|
||||
/*
|
||||
* PHY-Specific Status Register (reg 17).
|
||||
*
|
||||
* Bit 0 : jabber => 1:jabber detected, 0:not
|
||||
* Bit 1 : polarity => 1:polarity reversed, 0:normal
|
||||
* Bit 2 : recvpause => 1:receive pause enabled, 0:disabled
|
||||
* Bit 3 : xmitpause => 1:transmit pause enabled, 0:disabled
|
||||
* Bit 4 : energydetect => 1:sleep, 0:active
|
||||
* Bit 5 : downshift => 1:downshift, 0:no downshift
|
||||
* Bit 6 : crossover => 1:MDIX (crossover), 0:MDI (no crossover)
|
||||
* Bits 7-9 : cablelen => not valid in 10Mb/s mode
|
||||
* 0:<50m, 1:50-80m, 2:80-110m, 3:110-140m, 4:>140m
|
||||
* Bit 10 : link => 1:link up, 0:link down
|
||||
* Bit 11 : resolved => 1:speed and duplex resolved, 0:not yet
|
||||
* Bit 12 : pagercvd => 1:page received, 0:page not received
|
||||
* Bit 13 : duplex => 1:full duplex, 0:half duplex
|
||||
* Bits 14-15 : speed => 0:10Mb/s, 1:100Mb/s, 2:1000Mb/s, 3:rsvd
|
||||
*/
|
||||
|
||||
#define netxen_get_phy_cablelen(config_word) (((config_word) >> 7) & 0x07)
|
||||
#define netxen_get_phy_speed(config_word) (((config_word) >> 14) & 0x03)
|
||||
|
||||
#define netxen_set_phy_speed(config_word, val) \
|
||||
((config_word) |= ((val & 0x03) << 14))
|
||||
#define netxen_set_phy_duplex(config_word) \
|
||||
set_bit(13, (unsigned long*)&config_word)
|
||||
#define netxen_clear_phy_duplex(config_word) \
|
||||
clear_bit(13, (unsigned long*)&config_word)
|
||||
|
||||
#define netxen_get_phy_jabber(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 0)
|
||||
#define netxen_get_phy_polarity(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 1)
|
||||
#define netxen_get_phy_recvpause(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 2)
|
||||
#define netxen_get_phy_xmitpause(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 3)
|
||||
#define netxen_get_phy_energydetect(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 4)
|
||||
#define netxen_get_phy_downshift(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 5)
|
||||
#define netxen_get_phy_crossover(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 6)
|
||||
#define netxen_get_phy_link(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 10)
|
||||
#define netxen_get_phy_resolved(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 11)
|
||||
#define netxen_get_phy_pagercvd(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 12)
|
||||
#define netxen_get_phy_duplex(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 13)
|
||||
|
||||
/*
|
||||
* Interrupt Register definition
|
||||
* This definition applies to registers 18 and 19 (int enable and int status).
|
||||
* Bit 0 : jabber
|
||||
* Bit 1 : polarity_changed
|
||||
* Bit 4 : energy_detect
|
||||
* Bit 5 : downshift
|
||||
* Bit 6 : mdi_xover_changed
|
||||
* Bit 7 : fifo_over_underflow
|
||||
* Bit 8 : false_carrier
|
||||
* Bit 9 : symbol_error
|
||||
* Bit 10: link_status_changed
|
||||
* Bit 11: autoneg_completed
|
||||
* Bit 12: page_received
|
||||
* Bit 13: duplex_changed
|
||||
* Bit 14: speed_changed
|
||||
* Bit 15: autoneg_error
|
||||
*/
|
||||
|
||||
#define netxen_get_phy_int_jabber(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 0)
|
||||
#define netxen_get_phy_int_polarity_changed(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 1)
|
||||
#define netxen_get_phy_int_energy_detect(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 4)
|
||||
#define netxen_get_phy_int_downshift(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 5)
|
||||
#define netxen_get_phy_int_mdi_xover_changed(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 6)
|
||||
#define netxen_get_phy_int_fifo_over_underflow(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 7)
|
||||
#define netxen_get_phy_int_false_carrier(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 8)
|
||||
#define netxen_get_phy_int_symbol_error(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 9)
|
||||
#define netxen_get_phy_int_link_status_changed(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 10)
|
||||
#define netxen_get_phy_int_autoneg_completed(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 11)
|
||||
#define netxen_get_phy_int_page_received(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 12)
|
||||
#define netxen_get_phy_int_duplex_changed(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 13)
|
||||
#define netxen_get_phy_int_speed_changed(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 14)
|
||||
#define netxen_get_phy_int_autoneg_error(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 15)
|
||||
|
||||
#define netxen_set_phy_int_link_status_changed(config_word) \
|
||||
set_bit(10, (unsigned long*)&config_word)
|
||||
#define netxen_set_phy_int_autoneg_completed(config_word) \
|
||||
set_bit(11, (unsigned long*)&config_word)
|
||||
#define netxen_set_phy_int_speed_changed(config_word) \
|
||||
set_bit(14, (unsigned long*)&config_word)
|
||||
|
||||
/*
|
||||
* NIU Mode Register.
|
||||
* Bit 0 : enable FibreChannel
|
||||
* Bit 1 : enable 10/100/1000 Ethernet
|
||||
* Bit 2 : enable 10Gb Ethernet
|
||||
*/
|
||||
|
||||
#define netxen_get_niu_enable_ge(config_word) \
|
||||
_netxen_crb_get_bit(config_word, 1)
|
||||
|
||||
/* Promiscous mode options (GbE mode only) */
|
||||
typedef enum {
|
||||
NETXEN_NIU_PROMISC_MODE = 0,
|
||||
NETXEN_NIU_NON_PROMISC_MODE
|
||||
} netxen_niu_prom_mode_t;
|
||||
|
||||
/*
|
||||
* NIU GB Drop CRC Register
|
||||
*
|
||||
* Bit 0 : drop_gb0 => 1:drop pkts with bad CRCs, 0:pass them on
|
||||
* Bit 1 : drop_gb1 => 1:drop pkts with bad CRCs, 0:pass them on
|
||||
* Bit 2 : drop_gb2 => 1:drop pkts with bad CRCs, 0:pass them on
|
||||
* Bit 3 : drop_gb3 => 1:drop pkts with bad CRCs, 0:pass them on
|
||||
*/
|
||||
|
||||
#define netxen_set_gb_drop_gb0(config_word) \
|
||||
set_bit(0, (unsigned long*)&config_word)
|
||||
#define netxen_set_gb_drop_gb1(config_word) \
|
||||
set_bit(1, (unsigned long*)&config_word)
|
||||
#define netxen_set_gb_drop_gb2(config_word) \
|
||||
set_bit(2, (unsigned long*)&config_word)
|
||||
#define netxen_set_gb_drop_gb3(config_word) \
|
||||
set_bit(3, (unsigned long*)&config_word)
|
||||
|
||||
#define netxen_clear_gb_drop_gb0(config_word) \
|
||||
clear_bit(0, (unsigned long*)&config_word)
|
||||
#define netxen_clear_gb_drop_gb1(config_word) \
|
||||
clear_bit(1, (unsigned long*)&config_word)
|
||||
#define netxen_clear_gb_drop_gb2(config_word) \
|
||||
clear_bit(2, (unsigned long*)&config_word)
|
||||
#define netxen_clear_gb_drop_gb3(config_word) \
|
||||
clear_bit(3, (unsigned long*)&config_word)
|
||||
|
||||
/*
|
||||
* NIU XG MAC Config Register
|
||||
*
|
||||
* Bit 0 : tx_enable => 1:enable frame xmit, 0:disable
|
||||
* Bit 2 : rx_enable => 1:enable frame recv, 0:disable
|
||||
* Bit 4 : soft_reset => 1:reset the MAC , 0:no-op
|
||||
* Bit 27: xaui_framer_reset
|
||||
* Bit 28: xaui_rx_reset
|
||||
* Bit 29: xaui_tx_reset
|
||||
* Bit 30: xg_ingress_afifo_reset
|
||||
* Bit 31: xg_egress_afifo_reset
|
||||
*/
|
||||
|
||||
#define netxen_xg_soft_reset(config_word) \
|
||||
set_bit(4, (unsigned long*)&config_word)
|
||||
|
||||
/*
|
||||
* MAC Control Register
|
||||
*
|
||||
* Bit 0-1 : id_pool0
|
||||
* Bit 2 : enable_xtnd0
|
||||
* Bit 4-5 : id_pool1
|
||||
* Bit 6 : enable_xtnd1
|
||||
* Bit 8-9 : id_pool2
|
||||
* Bit 10 : enable_xtnd2
|
||||
* Bit 12-13 : id_pool3
|
||||
* Bit 14 : enable_xtnd3
|
||||
* Bit 24-25 : mode_select
|
||||
* Bit 28-31 : enable_pool
|
||||
*/
|
||||
|
||||
#define netxen_nic_mcr_set_id_pool0(config, val) \
|
||||
((config) |= ((val) &0x03))
|
||||
#define netxen_nic_mcr_set_enable_xtnd0(config) \
|
||||
(set_bit(3, (unsigned long *)&(config)))
|
||||
#define netxen_nic_mcr_set_id_pool1(config, val) \
|
||||
((config) |= (((val) & 0x03) << 4))
|
||||
#define netxen_nic_mcr_set_enable_xtnd1(config) \
|
||||
(set_bit(6, (unsigned long *)&(config)))
|
||||
#define netxen_nic_mcr_set_id_pool2(config, val) \
|
||||
((config) |= (((val) & 0x03) << 8))
|
||||
#define netxen_nic_mcr_set_enable_xtnd2(config) \
|
||||
(set_bit(10, (unsigned long *)&(config)))
|
||||
#define netxen_nic_mcr_set_id_pool3(config, val) \
|
||||
((config) |= (((val) & 0x03) << 12))
|
||||
#define netxen_nic_mcr_set_enable_xtnd3(config) \
|
||||
(set_bit(14, (unsigned long *)&(config)))
|
||||
#define netxen_nic_mcr_set_mode_select(config, val) \
|
||||
((config) |= (((val) & 0x03) << 24))
|
||||
#define netxen_nic_mcr_set_enable_pool(config, val) \
|
||||
((config) |= (((val) & 0x0f) << 28))
|
||||
|
||||
/* Set promiscuous mode for a GbE interface */
|
||||
int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter, int port,
|
||||
netxen_niu_prom_mode_t mode);
|
||||
int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter,
|
||||
int port, netxen_niu_prom_mode_t mode);
|
||||
|
||||
/* get/set the MAC address for a given MAC */
|
||||
int netxen_niu_macaddr_get(struct netxen_adapter *adapter, int port,
|
||||
netxen_ethernet_macaddr_t * addr);
|
||||
int netxen_niu_macaddr_set(struct netxen_port *port,
|
||||
netxen_ethernet_macaddr_t addr);
|
||||
|
||||
/* XG versons */
|
||||
int netxen_niu_xg_macaddr_get(struct netxen_adapter *adapter, int port,
|
||||
netxen_ethernet_macaddr_t * addr);
|
||||
int netxen_niu_xg_macaddr_set(struct netxen_port *port,
|
||||
netxen_ethernet_macaddr_t addr);
|
||||
|
||||
/* Generic enable for GbE ports. Will detect the speed of the link. */
|
||||
int netxen_niu_gbe_init_port(struct netxen_adapter *adapter, int port);
|
||||
|
||||
/* Disable a GbE interface */
|
||||
int netxen_niu_disable_gbe_port(struct netxen_adapter *adapter, int port);
|
||||
|
||||
int netxen_niu_disable_xg_port(struct netxen_adapter *adapter, int port);
|
||||
|
||||
#endif /* __NETXEN_NIC_HW_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,75 @@
|
|||
/*
|
||||
* Copyright (C) 2003 - 2006 NetXen, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston,
|
||||
* MA 02111-1307, USA.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution
|
||||
* in the file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* info@netxen.com
|
||||
* NetXen,
|
||||
* 3965 Freedom Circle, Fourth floor,
|
||||
* Santa Clara, CA 95054
|
||||
*/
|
||||
|
||||
#ifndef __NETXEN_NIC_IOCTL_H__
|
||||
#define __NETXEN_NIC_IOCTL_H__
|
||||
|
||||
#include <linux/sockios.h>
|
||||
|
||||
#define NETXEN_CMD_START SIOCDEVPRIVATE
|
||||
#define NETXEN_NIC_CMD (NETXEN_CMD_START + 1)
|
||||
#define NETXEN_NIC_NAME (NETXEN_CMD_START + 2)
|
||||
|
||||
typedef enum {
|
||||
netxen_nic_cmd_none = 0,
|
||||
netxen_nic_cmd_pci_read,
|
||||
netxen_nic_cmd_pci_write,
|
||||
netxen_nic_cmd_pci_mem_read,
|
||||
netxen_nic_cmd_pci_mem_write,
|
||||
netxen_nic_cmd_pci_config_read,
|
||||
netxen_nic_cmd_pci_config_write,
|
||||
netxen_nic_cmd_get_stats,
|
||||
netxen_nic_cmd_clear_stats,
|
||||
netxen_nic_cmd_get_version
|
||||
} netxen_nic_ioctl_cmd_t;
|
||||
|
||||
struct netxen_nic_ioctl_data {
|
||||
u32 cmd;
|
||||
u32 unused1;
|
||||
u64 off;
|
||||
u32 size;
|
||||
u32 rv;
|
||||
char u[64];
|
||||
void *ptr;
|
||||
};
|
||||
|
||||
struct netxen_statistics {
|
||||
u64 rx_packets;
|
||||
u64 tx_packets;
|
||||
u64 rx_bytes;
|
||||
u64 rx_errors;
|
||||
u64 tx_bytes;
|
||||
u64 tx_errors;
|
||||
u64 rx_crc_errors;
|
||||
u64 rx_short_length_error;
|
||||
u64 rx_long_length_error;
|
||||
u64 rx_mac_errors;
|
||||
};
|
||||
|
||||
#endif /* __NETXEN_NIC_IOCTL_H_ */
|
||||
|
|
@ -0,0 +1,221 @@
|
|||
/*
|
||||
* Copyright (C) 2003 - 2006 NetXen, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston,
|
||||
* MA 02111-1307, USA.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution
|
||||
* in the file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* info@netxen.com
|
||||
* NetXen,
|
||||
* 3965 Freedom Circle, Fourth floor,
|
||||
* Santa Clara, CA 95054
|
||||
*/
|
||||
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include "netxen_nic.h"
|
||||
#include "netxen_nic_hw.h"
|
||||
#include "netxen_nic_phan_reg.h"
|
||||
|
||||
/*
|
||||
* netxen_nic_get_stats - Get System Network Statistics
|
||||
* @netdev: network interface device structure
|
||||
*/
|
||||
struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev)
|
||||
{
|
||||
struct netxen_port *port = netdev_priv(netdev);
|
||||
struct net_device_stats *stats = &port->net_stats;
|
||||
|
||||
memset(stats, 0, sizeof(*stats));
|
||||
|
||||
/* total packets received */
|
||||
stats->rx_packets = port->stats.no_rcv;
|
||||
/* total packets transmitted */
|
||||
stats->tx_packets = port->stats.xmitedframes + port->stats.xmitfinished;
|
||||
/* total bytes received */
|
||||
stats->rx_bytes = port->stats.rxbytes;
|
||||
/* total bytes transmitted */
|
||||
stats->tx_bytes = port->stats.txbytes;
|
||||
/* bad packets received */
|
||||
stats->rx_errors = port->stats.rcvdbadskb;
|
||||
/* packet transmit problems */
|
||||
stats->tx_errors = port->stats.nocmddescriptor;
|
||||
/* no space in linux buffers */
|
||||
stats->rx_dropped = port->stats.updropped;
|
||||
/* no space available in linux */
|
||||
stats->tx_dropped = port->stats.txdropped;
|
||||
|
||||
return stats;
|
||||
}
|
||||
|
||||
void netxen_indicate_link_status(struct netxen_adapter *adapter, u32 portno,
|
||||
u32 link)
|
||||
{
|
||||
struct netxen_port *pport = adapter->port[portno];
|
||||
struct net_device *netdev = pport->netdev;
|
||||
|
||||
if (link)
|
||||
netif_carrier_on(netdev);
|
||||
else
|
||||
netif_carrier_off(netdev);
|
||||
}
|
||||
|
||||
void netxen_handle_port_int(struct netxen_adapter *adapter, u32 portno,
|
||||
u32 enable)
|
||||
{
|
||||
__le32 int_src;
|
||||
struct netxen_port *port;
|
||||
|
||||
/* This should clear the interrupt source */
|
||||
if (adapter->ops->phy_read)
|
||||
adapter->ops->phy_read(adapter, portno,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS,
|
||||
&int_src);
|
||||
if (int_src == 0) {
|
||||
DPRINTK(INFO, "No phy interrupts for port #%d\n", portno);
|
||||
return;
|
||||
}
|
||||
if (adapter->ops->disable_phy_interrupts)
|
||||
adapter->ops->disable_phy_interrupts(adapter, portno);
|
||||
|
||||
port = adapter->port[portno];
|
||||
|
||||
if (netxen_get_phy_int_jabber(int_src))
|
||||
DPRINTK(INFO, "NetXen: %s Jabber interrupt \n",
|
||||
port->netdev->name);
|
||||
|
||||
if (netxen_get_phy_int_polarity_changed(int_src))
|
||||
DPRINTK(INFO, "NetXen: %s POLARITY CHANGED int \n",
|
||||
port->netdev->name);
|
||||
|
||||
if (netxen_get_phy_int_energy_detect(int_src))
|
||||
DPRINTK(INFO, "NetXen: %s ENERGY DETECT INT \n",
|
||||
port->netdev->name);
|
||||
|
||||
if (netxen_get_phy_int_downshift(int_src))
|
||||
DPRINTK(INFO, "NetXen: %s DOWNSHIFT INT \n",
|
||||
port->netdev->name);
|
||||
/* write it down later.. */
|
||||
if ((netxen_get_phy_int_speed_changed(int_src))
|
||||
|| (netxen_get_phy_int_link_status_changed(int_src))) {
|
||||
__le32 status;
|
||||
|
||||
DPRINTK(INFO, "NetXen: %s SPEED CHANGED OR"
|
||||
" LINK STATUS CHANGED \n", port->netdev->name);
|
||||
|
||||
if (adapter->ops->phy_read
|
||||
&& adapter->ops->phy_read(adapter, portno,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
|
||||
&status) == 0) {
|
||||
if (netxen_get_phy_int_link_status_changed(int_src)) {
|
||||
if (netxen_get_phy_link(status)) {
|
||||
netxen_niu_gbe_init_port(adapter,
|
||||
portno);
|
||||
printk("%s: %s Link UP\n",
|
||||
netxen_nic_driver_name,
|
||||
port->netdev->name);
|
||||
|
||||
} else {
|
||||
printk("%s: %s Link DOWN\n",
|
||||
netxen_nic_driver_name,
|
||||
port->netdev->name);
|
||||
}
|
||||
netxen_indicate_link_status(adapter, portno,
|
||||
netxen_get_phy_link
|
||||
(status));
|
||||
}
|
||||
}
|
||||
}
|
||||
if (adapter->ops->enable_phy_interrupts)
|
||||
adapter->ops->enable_phy_interrupts(adapter, portno);
|
||||
}
|
||||
|
||||
void netxen_nic_isr_other(struct netxen_adapter *adapter)
|
||||
{
|
||||
u32 enable, portno;
|
||||
u32 i2qhi;
|
||||
|
||||
/*
|
||||
* bit 3 is for i2qInt, if high its enabled
|
||||
* check for phy interrupts
|
||||
* read vector and check for bit 45 for phy
|
||||
* clear int by writing the same value into ISR_INT_VECTOR REG
|
||||
*/
|
||||
|
||||
DPRINTK(INFO, "I2Q is the source of INT \n");
|
||||
|
||||
/* verify the offset */
|
||||
i2qhi = readl(NETXEN_CRB_NORMALIZE(adapter, NETXEN_I2Q_CLR_PCI_HI));
|
||||
|
||||
DPRINTK(INFO, "isr NETXEN_I2Q_CLR_PCI_HI = 0x%x \n", i2qhi);
|
||||
|
||||
if (i2qhi & 0x4000) {
|
||||
for (portno = 0; portno < NETXEN_NIU_MAX_GBE_PORTS; portno++) {
|
||||
DPRINTK(INFO, "External PHY interrupt ON PORT %d\n",
|
||||
portno);
|
||||
|
||||
enable = 1;
|
||||
netxen_handle_port_int(adapter, portno, enable);
|
||||
}
|
||||
|
||||
/* Clear the interrupt on I2Q */
|
||||
writel((u32) i2qhi,
|
||||
NETXEN_CRB_NORMALIZE(adapter, NETXEN_I2Q_CLR_PCI_HI));
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
void netxen_nic_gbe_handle_phy_intr(struct netxen_adapter *adapter)
|
||||
{
|
||||
u32 val;
|
||||
val = readl(NETXEN_CRB_NORMALIZE(adapter, ISR_INT_VECTOR));
|
||||
if (val & 0x4) {
|
||||
adapter->stats.otherints++;
|
||||
netxen_nic_isr_other(adapter);
|
||||
}
|
||||
}
|
||||
|
||||
void netxen_nic_xgbe_handle_phy_intr(struct netxen_adapter *adapter)
|
||||
{
|
||||
struct net_device *netdev = adapter->port[0]->netdev;
|
||||
u32 val;
|
||||
|
||||
/* WINDOW = 1 */
|
||||
val = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_XG_STATE));
|
||||
|
||||
if (adapter->ahw.xg_linkup == 1 && val != XG_LINK_UP) {
|
||||
printk(KERN_INFO "%s: %s NIC Link is down\n",
|
||||
netxen_nic_driver_name, netdev->name);
|
||||
adapter->ahw.xg_linkup = 0;
|
||||
/* read twice to clear sticky bits */
|
||||
/* WINDOW = 0 */
|
||||
netxen_nic_read_w0(adapter, NETXEN_NIU_XG_STATUS, &val);
|
||||
netxen_nic_read_w0(adapter, NETXEN_NIU_XG_STATUS, &val);
|
||||
|
||||
if ((val & 0xffb) != 0xffb) {
|
||||
printk(KERN_INFO "%s ISR: Sync/Align BAD: 0x%08x\n",
|
||||
netxen_nic_driver_name, val);
|
||||
}
|
||||
} else if (adapter->ahw.xg_linkup == 0 && val == XG_LINK_UP) {
|
||||
printk(KERN_INFO "%s: %s NIC Link is up\n",
|
||||
netxen_nic_driver_name, netdev->name);
|
||||
adapter->ahw.xg_linkup = 1;
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,800 @@
|
|||
/*
|
||||
* Copyright (C) 2003 - 2006 NetXen, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston,
|
||||
* MA 02111-1307, USA.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution
|
||||
* in the file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* info@netxen.com
|
||||
* NetXen,
|
||||
* 3965 Freedom Circle, Fourth floor,
|
||||
* Santa Clara, CA 95054
|
||||
*
|
||||
*
|
||||
* Provides access to the Network Interface Unit h/w block.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "netxen_nic.h"
|
||||
#include <linux/delay.h>
|
||||
|
||||
/*
|
||||
* netxen_niu_gbe_phy_read - read a register from the GbE PHY via
|
||||
* mii management interface.
|
||||
*
|
||||
* Note: The MII management interface goes through port 0.
|
||||
* Individual phys are addressed as follows:
|
||||
* @param phy [15:8] phy id
|
||||
* @param reg [7:0] register number
|
||||
*
|
||||
* @returns 0 on success
|
||||
* -1 on error
|
||||
*
|
||||
*/
|
||||
int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long phy,
|
||||
long reg, __le32 * readval)
|
||||
{
|
||||
long timeout = 0;
|
||||
long result = 0;
|
||||
long restore = 0;
|
||||
__le32 address;
|
||||
__le32 command;
|
||||
__le32 status;
|
||||
__le32 mii_cfg;
|
||||
__le32 mac_cfg0;
|
||||
|
||||
/* MII mgmt all goes through port 0 MAC interface, so it cannot be in reset */
|
||||
if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0),
|
||||
&mac_cfg0, 4))
|
||||
return -EIO;
|
||||
if (netxen_gb_get_soft_reset(mac_cfg0)) {
|
||||
__le32 temp;
|
||||
temp = 0;
|
||||
netxen_gb_tx_reset_pb(temp);
|
||||
netxen_gb_rx_reset_pb(temp);
|
||||
netxen_gb_tx_reset_mac(temp);
|
||||
netxen_gb_rx_reset_mac(temp);
|
||||
if (netxen_nic_hw_write_wx(adapter,
|
||||
NETXEN_NIU_GB_MAC_CONFIG_0(0),
|
||||
&temp, 4))
|
||||
return -EIO;
|
||||
restore = 1;
|
||||
}
|
||||
|
||||
/* reset MII management interface */
|
||||
mii_cfg = 0;
|
||||
netxen_gb_set_mii_mgmt_clockselect(mii_cfg, 7);
|
||||
netxen_gb_mii_mgmt_reset(mii_cfg);
|
||||
if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_CONFIG(0),
|
||||
&mii_cfg, 4))
|
||||
return -EIO;
|
||||
netxen_gb_mii_mgmt_unset(mii_cfg);
|
||||
if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_CONFIG(0),
|
||||
&mii_cfg, 4))
|
||||
return -EIO;
|
||||
|
||||
address = 0;
|
||||
netxen_gb_mii_mgmt_reg_addr(address, reg);
|
||||
netxen_gb_mii_mgmt_phy_addr(address, phy);
|
||||
if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0),
|
||||
&address, 4))
|
||||
return -EIO;
|
||||
command = 0; /* turn off any prior activity */
|
||||
if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0),
|
||||
&command, 4))
|
||||
return -EIO;
|
||||
/* send read command */
|
||||
netxen_gb_mii_mgmt_set_read_cycle(command);
|
||||
if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0),
|
||||
&command, 4))
|
||||
return -EIO;
|
||||
|
||||
status = 0;
|
||||
do {
|
||||
if (netxen_nic_hw_read_wx(adapter,
|
||||
NETXEN_NIU_GB_MII_MGMT_INDICATE(0),
|
||||
&status, 4))
|
||||
return -EIO;
|
||||
timeout++;
|
||||
} while ((netxen_get_gb_mii_mgmt_busy(status)
|
||||
|| netxen_get_gb_mii_mgmt_notvalid(status))
|
||||
&& (timeout++ < NETXEN_NIU_PHY_WAITMAX));
|
||||
|
||||
if (timeout < NETXEN_NIU_PHY_WAITMAX) {
|
||||
if (netxen_nic_hw_read_wx(adapter,
|
||||
NETXEN_NIU_GB_MII_MGMT_STATUS(0),
|
||||
readval, 4))
|
||||
return -EIO;
|
||||
result = 0;
|
||||
} else
|
||||
result = -1;
|
||||
|
||||
if (restore)
|
||||
if (netxen_nic_hw_write_wx(adapter,
|
||||
NETXEN_NIU_GB_MAC_CONFIG_0(0),
|
||||
&mac_cfg0, 4))
|
||||
return -EIO;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/*
|
||||
* netxen_niu_gbe_phy_write - write a register to the GbE PHY via
|
||||
* mii management interface.
|
||||
*
|
||||
* Note: The MII management interface goes through port 0.
|
||||
* Individual phys are addressed as follows:
|
||||
* @param phy [15:8] phy id
|
||||
* @param reg [7:0] register number
|
||||
*
|
||||
* @returns 0 on success
|
||||
* -1 on error
|
||||
*
|
||||
*/
|
||||
int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
|
||||
long phy, long reg, __le32 val)
|
||||
{
|
||||
long timeout = 0;
|
||||
long result = 0;
|
||||
long restore = 0;
|
||||
__le32 address;
|
||||
__le32 command;
|
||||
__le32 status;
|
||||
__le32 mac_cfg0;
|
||||
|
||||
/* MII mgmt all goes through port 0 MAC interface, so it cannot be in reset */
|
||||
if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0),
|
||||
&mac_cfg0, 4))
|
||||
return -EIO;
|
||||
if (netxen_gb_get_soft_reset(mac_cfg0)) {
|
||||
__le32 temp;
|
||||
temp = 0;
|
||||
netxen_gb_tx_reset_pb(temp);
|
||||
netxen_gb_rx_reset_pb(temp);
|
||||
netxen_gb_tx_reset_mac(temp);
|
||||
netxen_gb_rx_reset_mac(temp);
|
||||
|
||||
if (netxen_nic_hw_write_wx(adapter,
|
||||
NETXEN_NIU_GB_MAC_CONFIG_0(0),
|
||||
&temp, 4))
|
||||
return -EIO;
|
||||
restore = 1;
|
||||
}
|
||||
|
||||
command = 0; /* turn off any prior activity */
|
||||
if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0),
|
||||
&command, 4))
|
||||
return -EIO;
|
||||
|
||||
address = 0;
|
||||
netxen_gb_mii_mgmt_reg_addr(address, reg);
|
||||
netxen_gb_mii_mgmt_phy_addr(address, phy);
|
||||
if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0),
|
||||
&address, 4))
|
||||
return -EIO;
|
||||
|
||||
if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_CTRL(0),
|
||||
&val, 4))
|
||||
return -EIO;
|
||||
|
||||
status = 0;
|
||||
do {
|
||||
if (netxen_nic_hw_read_wx(adapter,
|
||||
NETXEN_NIU_GB_MII_MGMT_INDICATE(0),
|
||||
&status, 4))
|
||||
return -EIO;
|
||||
timeout++;
|
||||
} while ((netxen_get_gb_mii_mgmt_busy(status))
|
||||
&& (timeout++ < NETXEN_NIU_PHY_WAITMAX));
|
||||
|
||||
if (timeout < NETXEN_NIU_PHY_WAITMAX)
|
||||
result = 0;
|
||||
else
|
||||
result = -EIO;
|
||||
|
||||
/* restore the state of port 0 MAC in case we tampered with it */
|
||||
if (restore)
|
||||
if (netxen_nic_hw_write_wx(adapter,
|
||||
NETXEN_NIU_GB_MAC_CONFIG_0(0),
|
||||
&mac_cfg0, 4))
|
||||
return -EIO;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter,
|
||||
int port)
|
||||
{
|
||||
netxen_crb_writelit_adapter(adapter, NETXEN_NIU_INT_MASK, 0x3f);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter,
|
||||
int port)
|
||||
{
|
||||
int result = 0;
|
||||
__le32 enable = 0;
|
||||
netxen_set_phy_int_link_status_changed(enable);
|
||||
netxen_set_phy_int_autoneg_completed(enable);
|
||||
netxen_set_phy_int_speed_changed(enable);
|
||||
|
||||
if (0 !=
|
||||
netxen_niu_gbe_phy_write(adapter, port,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE,
|
||||
enable))
|
||||
result = -EIO;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter,
|
||||
int port)
|
||||
{
|
||||
netxen_crb_writelit_adapter(adapter, NETXEN_NIU_INT_MASK, 0x7f);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter,
|
||||
int port)
|
||||
{
|
||||
int result = 0;
|
||||
if (0 !=
|
||||
netxen_niu_gbe_phy_write(adapter, port,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE, 0))
|
||||
result = -EIO;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
int netxen_niu_xgbe_clear_phy_interrupts(struct netxen_adapter *adapter,
|
||||
int port)
|
||||
{
|
||||
netxen_crb_writelit_adapter(adapter, NETXEN_NIU_ACTIVE_INT, -1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int netxen_niu_gbe_clear_phy_interrupts(struct netxen_adapter *adapter,
|
||||
int port)
|
||||
{
|
||||
int result = 0;
|
||||
if (0 !=
|
||||
netxen_niu_gbe_phy_write(adapter, port,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS,
|
||||
-EIO))
|
||||
result = -EIO;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/*
|
||||
* netxen_niu_gbe_set_mii_mode- Set 10/100 Mbit Mode for GbE MAC
|
||||
*
|
||||
*/
|
||||
void netxen_niu_gbe_set_mii_mode(struct netxen_adapter *adapter,
|
||||
int port, long enable)
|
||||
{
|
||||
netxen_crb_writelit_adapter(adapter, NETXEN_NIU_MODE, 0x2);
|
||||
netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
|
||||
0x80000000);
|
||||
netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
|
||||
0x0000f0025);
|
||||
netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_1(port),
|
||||
0xf1ff);
|
||||
netxen_crb_writelit_adapter(adapter,
|
||||
NETXEN_NIU_GB0_GMII_MODE + (port << 3), 0);
|
||||
netxen_crb_writelit_adapter(adapter,
|
||||
NETXEN_NIU_GB0_MII_MODE + (port << 3), 1);
|
||||
netxen_crb_writelit_adapter(adapter,
|
||||
(NETXEN_NIU_GB0_HALF_DUPLEX + port * 4), 0);
|
||||
netxen_crb_writelit_adapter(adapter,
|
||||
NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 0x7);
|
||||
|
||||
if (enable) {
|
||||
/*
|
||||
* Do NOT enable flow control until a suitable solution for
|
||||
* shutting down pause frames is found.
|
||||
*/
|
||||
netxen_crb_writelit_adapter(adapter,
|
||||
NETXEN_NIU_GB_MAC_CONFIG_0(port),
|
||||
0x5);
|
||||
}
|
||||
|
||||
if (netxen_niu_gbe_enable_phy_interrupts(adapter, port))
|
||||
printk(KERN_ERR PFX "ERROR enabling PHY interrupts\n");
|
||||
if (netxen_niu_gbe_clear_phy_interrupts(adapter, port))
|
||||
printk(KERN_ERR PFX "ERROR clearing PHY interrupts\n");
|
||||
}
|
||||
|
||||
/*
|
||||
* netxen_niu_gbe_set_gmii_mode- Set GbE Mode for GbE MAC
|
||||
*/
|
||||
void netxen_niu_gbe_set_gmii_mode(struct netxen_adapter *adapter,
|
||||
int port, long enable)
|
||||
{
|
||||
netxen_crb_writelit_adapter(adapter, NETXEN_NIU_MODE, 0x2);
|
||||
netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
|
||||
0x80000000);
|
||||
netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
|
||||
0x0000f0025);
|
||||
netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_1(port),
|
||||
0xf2ff);
|
||||
netxen_crb_writelit_adapter(adapter,
|
||||
NETXEN_NIU_GB0_MII_MODE + (port << 3), 0);
|
||||
netxen_crb_writelit_adapter(adapter,
|
||||
NETXEN_NIU_GB0_GMII_MODE + (port << 3), 1);
|
||||
netxen_crb_writelit_adapter(adapter,
|
||||
(NETXEN_NIU_GB0_HALF_DUPLEX + port * 4), 0);
|
||||
netxen_crb_writelit_adapter(adapter,
|
||||
NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 0x7);
|
||||
|
||||
if (enable) {
|
||||
/*
|
||||
* Do NOT enable flow control until a suitable solution for
|
||||
* shutting down pause frames is found.
|
||||
*/
|
||||
netxen_crb_writelit_adapter(adapter,
|
||||
NETXEN_NIU_GB_MAC_CONFIG_0(port),
|
||||
0x5);
|
||||
}
|
||||
|
||||
if (netxen_niu_gbe_enable_phy_interrupts(adapter, port))
|
||||
printk(KERN_ERR PFX "ERROR enabling PHY interrupts\n");
|
||||
if (netxen_niu_gbe_clear_phy_interrupts(adapter, port))
|
||||
printk(KERN_ERR PFX "ERROR clearing PHY interrupts\n");
|
||||
}
|
||||
|
||||
int netxen_niu_gbe_init_port(struct netxen_adapter *adapter, int port)
|
||||
{
|
||||
int result = 0;
|
||||
__le32 status;
|
||||
if (adapter->ops->disable_phy_interrupts)
|
||||
adapter->ops->disable_phy_interrupts(adapter, port);
|
||||
mdelay(2);
|
||||
|
||||
if (0 ==
|
||||
netxen_niu_gbe_phy_read(adapter, port,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
|
||||
(__le32 *) & status)) {
|
||||
if (netxen_get_phy_link(status)) {
|
||||
if (netxen_get_phy_speed(status) == 2) {
|
||||
netxen_niu_gbe_set_gmii_mode(adapter, port, 1);
|
||||
} else if ((netxen_get_phy_speed(status) == 1)
|
||||
|| (netxen_get_phy_speed(status) == 0)) {
|
||||
netxen_niu_gbe_set_mii_mode(adapter, port, 1);
|
||||
} else {
|
||||
result = -1;
|
||||
}
|
||||
|
||||
} else {
|
||||
/* We don't have link. Cable must be unconnected. */
|
||||
/* Enable phy interrupts so we take action when plugged in */
|
||||
netxen_crb_writelit_adapter(adapter,
|
||||
NETXEN_NIU_GB_MAC_CONFIG_0
|
||||
(port), 0x80000000);
|
||||
netxen_crb_writelit_adapter(adapter,
|
||||
NETXEN_NIU_GB_MAC_CONFIG_0
|
||||
(port), 0x0000f0025);
|
||||
if (netxen_niu_gbe_clear_phy_interrupts(adapter, port))
|
||||
printk(KERN_ERR PFX
|
||||
"ERROR clearing PHY interrupts\n");
|
||||
if (netxen_niu_gbe_enable_phy_interrupts(adapter, port))
|
||||
printk(KERN_ERR PFX
|
||||
"ERROR enabling PHY interrupts\n");
|
||||
if (netxen_niu_gbe_clear_phy_interrupts(adapter, port))
|
||||
printk(KERN_ERR PFX
|
||||
"ERROR clearing PHY interrupts\n");
|
||||
result = -1;
|
||||
}
|
||||
} else {
|
||||
result = -EIO;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
/*
|
||||
* netxen_niu_gbe_handle_phy_interrupt - Handles GbE PHY interrupts
|
||||
* @param enable 0 means don't enable the port
|
||||
* 1 means enable (or re-enable) the port
|
||||
*/
|
||||
int netxen_niu_gbe_handle_phy_interrupt(struct netxen_adapter *adapter,
|
||||
int port, long enable)
|
||||
{
|
||||
int result = 0;
|
||||
__le32 int_src;
|
||||
|
||||
printk(KERN_INFO PFX "NETXEN: Handling PHY interrupt on port %d"
|
||||
" (device enable = %d)\n", (int)port, (int)enable);
|
||||
|
||||
/* The read of the PHY INT status will clear the pending interrupt status */
|
||||
if (netxen_niu_gbe_phy_read(adapter, port,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS,
|
||||
&int_src) != 0)
|
||||
result = -EINVAL;
|
||||
else {
|
||||
printk(KERN_INFO PFX "PHY Interrupt source = 0x%x \n", int_src);
|
||||
if (netxen_get_phy_int_jabber(int_src))
|
||||
printk(KERN_INFO PFX "jabber Interrupt ");
|
||||
if (netxen_get_phy_int_polarity_changed(int_src))
|
||||
printk(KERN_INFO PFX "polarity changed ");
|
||||
if (netxen_get_phy_int_energy_detect(int_src))
|
||||
printk(KERN_INFO PFX "energy detect \n");
|
||||
if (netxen_get_phy_int_downshift(int_src))
|
||||
printk(KERN_INFO PFX "downshift \n");
|
||||
if (netxen_get_phy_int_mdi_xover_changed(int_src))
|
||||
printk(KERN_INFO PFX "mdi_xover_changed ");
|
||||
if (netxen_get_phy_int_fifo_over_underflow(int_src))
|
||||
printk(KERN_INFO PFX "fifo_over_underflow ");
|
||||
if (netxen_get_phy_int_false_carrier(int_src))
|
||||
printk(KERN_INFO PFX "false_carrier ");
|
||||
if (netxen_get_phy_int_symbol_error(int_src))
|
||||
printk(KERN_INFO PFX "symbol_error ");
|
||||
if (netxen_get_phy_int_autoneg_completed(int_src))
|
||||
printk(KERN_INFO PFX "autoneg_completed ");
|
||||
if (netxen_get_phy_int_page_received(int_src))
|
||||
printk(KERN_INFO PFX "page_received ");
|
||||
if (netxen_get_phy_int_duplex_changed(int_src))
|
||||
printk(KERN_INFO PFX "duplex_changed ");
|
||||
if (netxen_get_phy_int_autoneg_error(int_src))
|
||||
printk(KERN_INFO PFX "autoneg_error ");
|
||||
if ((netxen_get_phy_int_speed_changed(int_src))
|
||||
|| (netxen_get_phy_int_link_status_changed(int_src))) {
|
||||
__le32 status;
|
||||
|
||||
printk(KERN_INFO PFX
|
||||
"speed_changed or link status changed");
|
||||
if (netxen_niu_gbe_phy_read
|
||||
(adapter, port,
|
||||
NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
|
||||
&status) == 0) {
|
||||
if (netxen_get_phy_speed(status) == 2) {
|
||||
printk
|
||||
(KERN_INFO PFX "Link speed changed"
|
||||
" to 1000 Mbps\n");
|
||||
netxen_niu_gbe_set_gmii_mode(adapter,
|
||||
port,
|
||||
enable);
|
||||
} else if (netxen_get_phy_speed(status) == 1) {
|
||||
printk
|
||||
(KERN_INFO PFX "Link speed changed"
|
||||
" to 100 Mbps\n");
|
||||
netxen_niu_gbe_set_mii_mode(adapter,
|
||||
port,
|
||||
enable);
|
||||
} else if (netxen_get_phy_speed(status) == 0) {
|
||||
printk
|
||||
(KERN_INFO PFX "Link speed changed"
|
||||
" to 10 Mbps\n");
|
||||
netxen_niu_gbe_set_mii_mode(adapter,
|
||||
port,
|
||||
enable);
|
||||
} else {
|
||||
printk(KERN_ERR PFX "ERROR reading"
|
||||
"PHY status. Illegal speed.\n");
|
||||
result = -1;
|
||||
}
|
||||
} else {
|
||||
printk(KERN_ERR PFX
|
||||
"ERROR reading PHY status.\n");
|
||||
result = -1;
|
||||
}
|
||||
|
||||
}
|
||||
printk(KERN_INFO "\n");
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
/*
|
||||
* Return the current station MAC address.
|
||||
* Note that the passed-in value must already be in network byte order.
|
||||
*/
|
||||
int netxen_niu_macaddr_get(struct netxen_adapter *adapter,
|
||||
int phy, netxen_ethernet_macaddr_t * addr)
|
||||
{
|
||||
u64 result = 0;
|
||||
__le32 stationhigh;
|
||||
__le32 stationlow;
|
||||
|
||||
if (addr == NULL)
|
||||
return -EINVAL;
|
||||
if ((phy < 0) || (phy > 3))
|
||||
return -EINVAL;
|
||||
|
||||
if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_STATION_ADDR_0(phy),
|
||||
&stationhigh, 4))
|
||||
return -EIO;
|
||||
if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_STATION_ADDR_1(phy),
|
||||
&stationlow, 4))
|
||||
return -EIO;
|
||||
|
||||
result = (u64) netxen_gb_get_stationaddress_low(stationlow);
|
||||
result |= (u64) stationhigh << 16;
|
||||
memcpy(*addr, &result, sizeof(netxen_ethernet_macaddr_t));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set the station MAC address.
|
||||
* Note that the passed-in value must already be in network byte order.
|
||||
*/
|
||||
int netxen_niu_macaddr_set(struct netxen_port *port,
|
||||
netxen_ethernet_macaddr_t addr)
|
||||
{
|
||||
__le32 temp = 0;
|
||||
struct netxen_adapter *adapter = port->adapter;
|
||||
int phy = port->portnum;
|
||||
|
||||
memcpy(&temp, addr, 2);
|
||||
temp <<= 16;
|
||||
if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_STATION_ADDR_1(phy),
|
||||
&temp, 4))
|
||||
return -EIO;
|
||||
|
||||
temp = 0;
|
||||
|
||||
memcpy(&temp, ((u8 *) addr) + 2, sizeof(__le32));
|
||||
if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_STATION_ADDR_0(phy),
|
||||
&temp, 4))
|
||||
return -2;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Enable a GbE interface */
|
||||
int netxen_niu_enable_gbe_port(struct netxen_adapter *adapter,
|
||||
int port, netxen_niu_gbe_ifmode_t mode)
|
||||
{
|
||||
__le32 mac_cfg0;
|
||||
__le32 mac_cfg1;
|
||||
__le32 mii_cfg;
|
||||
|
||||
if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
|
||||
return -EINVAL;
|
||||
|
||||
mac_cfg0 = 0;
|
||||
netxen_gb_soft_reset(mac_cfg0);
|
||||
if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
|
||||
&mac_cfg0, 4))
|
||||
return -EIO;
|
||||
mac_cfg0 = 0;
|
||||
netxen_gb_enable_tx(mac_cfg0);
|
||||
netxen_gb_enable_rx(mac_cfg0);
|
||||
netxen_gb_unset_rx_flowctl(mac_cfg0);
|
||||
netxen_gb_tx_reset_pb(mac_cfg0);
|
||||
netxen_gb_rx_reset_pb(mac_cfg0);
|
||||
netxen_gb_tx_reset_mac(mac_cfg0);
|
||||
netxen_gb_rx_reset_mac(mac_cfg0);
|
||||
|
||||
if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
|
||||
&mac_cfg0, 4))
|
||||
return -EIO;
|
||||
mac_cfg1 = 0;
|
||||
netxen_gb_set_preamblelen(mac_cfg1, 0xf);
|
||||
netxen_gb_set_duplex(mac_cfg1);
|
||||
netxen_gb_set_crc_enable(mac_cfg1);
|
||||
netxen_gb_set_padshort(mac_cfg1);
|
||||
netxen_gb_set_checklength(mac_cfg1);
|
||||
netxen_gb_set_hugeframes(mac_cfg1);
|
||||
|
||||
if (mode == NETXEN_NIU_10_100_MB) {
|
||||
netxen_gb_set_intfmode(mac_cfg1, 1);
|
||||
if (netxen_nic_hw_write_wx(adapter,
|
||||
NETXEN_NIU_GB_MAC_CONFIG_1(port),
|
||||
&mac_cfg1, 4))
|
||||
return -EIO;
|
||||
|
||||
/* set mii mode */
|
||||
netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB0_GMII_MODE +
|
||||
(port << 3), 0);
|
||||
netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB0_MII_MODE +
|
||||
(port << 3), 1);
|
||||
|
||||
} else if (mode == NETXEN_NIU_1000_MB) {
|
||||
netxen_gb_set_intfmode(mac_cfg1, 2);
|
||||
if (netxen_nic_hw_write_wx(adapter,
|
||||
NETXEN_NIU_GB_MAC_CONFIG_1(port),
|
||||
&mac_cfg1, 4))
|
||||
return -EIO;
|
||||
/* set gmii mode */
|
||||
netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB0_MII_MODE +
|
||||
(port << 3), 0);
|
||||
netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB0_GMII_MODE +
|
||||
(port << 3), 1);
|
||||
}
|
||||
mii_cfg = 0;
|
||||
netxen_gb_set_mii_mgmt_clockselect(mii_cfg, 7);
|
||||
if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_CONFIG(port),
|
||||
&mii_cfg, 4))
|
||||
return -EIO;
|
||||
mac_cfg0 = 0;
|
||||
netxen_gb_enable_tx(mac_cfg0);
|
||||
netxen_gb_enable_rx(mac_cfg0);
|
||||
netxen_gb_unset_rx_flowctl(mac_cfg0);
|
||||
netxen_gb_unset_tx_flowctl(mac_cfg0);
|
||||
|
||||
if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
|
||||
&mac_cfg0, 4))
|
||||
return -EIO;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Disable a GbE interface */
|
||||
int netxen_niu_disable_gbe_port(struct netxen_adapter *adapter, int port)
|
||||
{
|
||||
__le32 mac_cfg0;
|
||||
|
||||
if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
|
||||
return -EINVAL;
|
||||
|
||||
mac_cfg0 = 0;
|
||||
netxen_gb_soft_reset(mac_cfg0);
|
||||
if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
|
||||
&mac_cfg0, 4))
|
||||
return -EIO;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Disable an XG interface */
|
||||
int netxen_niu_disable_xg_port(struct netxen_adapter *adapter, int port)
|
||||
{
|
||||
__le32 mac_cfg;
|
||||
|
||||
if (port != 0)
|
||||
return -EINVAL;
|
||||
|
||||
mac_cfg = 0;
|
||||
netxen_xg_soft_reset(mac_cfg);
|
||||
if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_XGE_CONFIG_0,
|
||||
&mac_cfg, 4))
|
||||
return -EIO;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Set promiscuous mode for a GbE interface */
|
||||
int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter, int port,
|
||||
netxen_niu_prom_mode_t mode)
|
||||
{
|
||||
__le32 reg;
|
||||
|
||||
if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
|
||||
return -EINVAL;
|
||||
|
||||
/* save previous contents */
|
||||
if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_DROP_WRONGADDR,
|
||||
®, 4))
|
||||
return -EIO;
|
||||
if (mode == NETXEN_NIU_PROMISC_MODE) {
|
||||
switch (port) {
|
||||
case 0:
|
||||
netxen_clear_gb_drop_gb0(reg);
|
||||
break;
|
||||
case 1:
|
||||
netxen_clear_gb_drop_gb1(reg);
|
||||
break;
|
||||
case 2:
|
||||
netxen_clear_gb_drop_gb2(reg);
|
||||
break;
|
||||
case 3:
|
||||
netxen_clear_gb_drop_gb3(reg);
|
||||
break;
|
||||
default:
|
||||
return -EIO;
|
||||
}
|
||||
} else {
|
||||
switch (port) {
|
||||
case 0:
|
||||
netxen_set_gb_drop_gb0(reg);
|
||||
break;
|
||||
case 1:
|
||||
netxen_set_gb_drop_gb1(reg);
|
||||
break;
|
||||
case 2:
|
||||
netxen_set_gb_drop_gb2(reg);
|
||||
break;
|
||||
case 3:
|
||||
netxen_set_gb_drop_gb3(reg);
|
||||
break;
|
||||
default:
|
||||
return -EIO;
|
||||
}
|
||||
}
|
||||
if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_DROP_WRONGADDR,
|
||||
®, 4))
|
||||
return -EIO;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set the MAC address for an XG port
|
||||
* Note that the passed-in value must already be in network byte order.
|
||||
*/
|
||||
int netxen_niu_xg_macaddr_set(struct netxen_port *port,
|
||||
netxen_ethernet_macaddr_t addr)
|
||||
{
|
||||
__le32 temp = 0;
|
||||
struct netxen_adapter *adapter = port->adapter;
|
||||
|
||||
memcpy(&temp, addr, 2);
|
||||
temp = cpu_to_le32(temp);
|
||||
temp <<= 16;
|
||||
if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_1,
|
||||
&temp, 4))
|
||||
return -EIO;
|
||||
|
||||
temp = 0;
|
||||
|
||||
memcpy(&temp, ((u8 *) addr) + 2, sizeof(__le32));
|
||||
temp = cpu_to_le32(temp);
|
||||
if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_HI,
|
||||
&temp, 4))
|
||||
return -EIO;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Return the current station MAC address.
|
||||
* Note that the passed-in value must already be in network byte order.
|
||||
*/
|
||||
int netxen_niu_xg_macaddr_get(struct netxen_adapter *adapter, int phy,
|
||||
netxen_ethernet_macaddr_t * addr)
|
||||
{
|
||||
__le32 stationhigh;
|
||||
__le32 stationlow;
|
||||
u64 result;
|
||||
|
||||
if (addr == NULL)
|
||||
return -EINVAL;
|
||||
if (phy != 0)
|
||||
return -EINVAL;
|
||||
|
||||
if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_HI,
|
||||
&stationhigh, 4))
|
||||
return -EIO;
|
||||
if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_1,
|
||||
&stationlow, 4))
|
||||
return -EIO;
|
||||
|
||||
result = ((u64) stationlow) >> 16;
|
||||
result |= (u64) stationhigh << 16;
|
||||
memcpy(*addr, &result, sizeof(netxen_ethernet_macaddr_t));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter,
|
||||
int port, netxen_niu_prom_mode_t mode)
|
||||
{
|
||||
__le32 reg;
|
||||
|
||||
if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
|
||||
return -EINVAL;
|
||||
|
||||
if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_XGE_CONFIG_1, ®, 4))
|
||||
return -EIO;
|
||||
if (mode == NETXEN_NIU_PROMISC_MODE)
|
||||
reg = (reg | 0x2000UL);
|
||||
else
|
||||
reg = (reg & ~0x2000UL);
|
||||
|
||||
netxen_crb_writelit_adapter(adapter, NETXEN_NIU_XGE_CONFIG_1, reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,195 @@
|
|||
/*
|
||||
* Copyright (C) 2003 - 2006 NetXen, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston,
|
||||
* MA 02111-1307, USA.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution
|
||||
* in the file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* info@netxen.com
|
||||
* NetXen,
|
||||
* 3965 Freedom Circle, Fourth floor,
|
||||
* Santa Clara, CA 95054
|
||||
*/
|
||||
|
||||
#ifndef __NIC_PHAN_REG_H_
|
||||
#define __NIC_PHAN_REG_H_
|
||||
|
||||
/*
|
||||
* CRB Registers or queue message done only at initialization time.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The following 2 are the base adresses for the CRB registers and their
|
||||
* offsets will be added to get addresses for the index addresses.
|
||||
*/
|
||||
#define NIC_CRB_BASE_PORT1 NETXEN_CAM_RAM(0x200)
|
||||
#define NIC_CRB_BASE_PORT2 NETXEN_CAM_RAM(0x250)
|
||||
|
||||
#define NETXEN_NIC_REG(X) (NIC_CRB_BASE_PORT1+(X))
|
||||
|
||||
/*
|
||||
* CrbPortPhanCntrHi/Lo is used to pass the address of HostPhantomIndex address
|
||||
* which can be read by the Phantom host to get producer/consumer indexes from
|
||||
* Phantom/Casper. If it is not HOST_SHARED_MEMORY, then the following
|
||||
* registers will be used for the addresses of the ring's shared memory
|
||||
* on the Phantom.
|
||||
*/
|
||||
|
||||
#define CRB_PHAN_CNTRL_LO_OFFSET NETXEN_NIC_REG(0x00)
|
||||
#define CRB_PHAN_CNTRL_HI_OFFSET NETXEN_NIC_REG(0x04)
|
||||
|
||||
/* point to the indexes */
|
||||
#define CRB_CMD_PRODUCER_OFFSET NETXEN_NIC_REG(0x08)
|
||||
#define CRB_CMD_CONSUMER_OFFSET NETXEN_NIC_REG(0x0c)
|
||||
|
||||
/* address of command descriptors in the host memory */
|
||||
#define CRB_HOST_CMD_ADDR_HI NETXEN_NIC_REG(0x30)
|
||||
#define CRB_HOST_CMD_ADDR_LO NETXEN_NIC_REG(0x34)
|
||||
|
||||
/* The following 4 CRB registers are for doing performance coal */
|
||||
#define CRB_CMD_INTR_LOOP NETXEN_NIC_REG(0x38)
|
||||
#define CRB_CMD_DMA_LOOP NETXEN_NIC_REG(0x3c)
|
||||
#define CRB_RCV_INTR_LOOP NETXEN_NIC_REG(0x40)
|
||||
#define CRB_RCV_DMA_LOOP NETXEN_NIC_REG(0x44)
|
||||
|
||||
/* Needed by the host to find out the state of Phantom's initialization */
|
||||
#define CRB_ENABLE_TX_INTR NETXEN_NIC_REG(0x4c)
|
||||
#define CRB_CMDPEG_STATE NETXEN_NIC_REG(0x50)
|
||||
#define CRB_CMDPEG_CMDRING NETXEN_NIC_REG(0x54)
|
||||
|
||||
/* Interrupt coalescing parameters */
|
||||
#define CRB_GLOBAL_INT_COAL NETXEN_NIC_REG(0x80)
|
||||
#define CRB_INT_COAL_MODE NETXEN_NIC_REG(0x84)
|
||||
#define CRB_MAX_RCV_BUFS NETXEN_NIC_REG(0x88)
|
||||
#define CRB_TX_INT_THRESHOLD NETXEN_NIC_REG(0x8c)
|
||||
#define CRB_RX_PKT_TIMER NETXEN_NIC_REG(0x90)
|
||||
#define CRB_TX_PKT_TIMER NETXEN_NIC_REG(0x94)
|
||||
#define CRB_RX_PKT_CNT NETXEN_NIC_REG(0x98)
|
||||
#define CRB_RX_TMR_CNT NETXEN_NIC_REG(0x9c)
|
||||
|
||||
/* Register for communicating XG link status */
|
||||
#define CRB_XG_STATE NETXEN_NIC_REG(0xa0)
|
||||
|
||||
/* Debug registers for controlling NIC pkt gen agent */
|
||||
#define CRB_AGENT_GO NETXEN_NIC_REG(0xb0)
|
||||
#define CRB_AGENT_TX_SIZE NETXEN_NIC_REG(0xb4)
|
||||
#define CRB_AGENT_TX_TYPE NETXEN_NIC_REG(0xb8)
|
||||
#define CRB_AGENT_TX_ADDR NETXEN_NIC_REG(0xbc)
|
||||
#define CRB_AGENT_TX_MSS NETXEN_NIC_REG(0xc0)
|
||||
|
||||
/* Debug registers for observing NIC performance */
|
||||
#define CRB_TX_STATE NETXEN_NIC_REG(0xd0)
|
||||
#define CRB_TX_COUNT NETXEN_NIC_REG(0xd4)
|
||||
#define CRB_RX_STATE NETXEN_NIC_REG(0xd8)
|
||||
|
||||
/* CRB registers per Rcv Descriptor ring */
|
||||
struct netxen_rcv_desc_crb {
|
||||
u32 crb_rcv_producer_offset __attribute__ ((aligned(512)));
|
||||
u32 crb_rcv_consumer_offset;
|
||||
u32 crb_globalrcv_ring;
|
||||
};
|
||||
|
||||
/*
|
||||
* CRB registers used by the receive peg logic. One instance of these
|
||||
* needs to be instantiated per instance of the receive peg.
|
||||
*/
|
||||
|
||||
struct netxen_recv_crb {
|
||||
struct netxen_rcv_desc_crb rcv_desc_crb[NUM_RCV_DESC_RINGS];
|
||||
u32 crb_rcvstatus_ring;
|
||||
u32 crb_rcv_status_producer;
|
||||
u32 crb_rcv_status_consumer;
|
||||
u32 crb_rcvpeg_state;
|
||||
};
|
||||
|
||||
#if defined(DEFINE_GLOBAL_RECV_CRB)
|
||||
struct netxen_recv_crb recv_crb_registers[] = {
|
||||
/*
|
||||
* Instance 0.
|
||||
*/
|
||||
{
|
||||
/* rcv_desc_crb: */
|
||||
{
|
||||
{
|
||||
/* crb_rcv_producer_offset: */
|
||||
NETXEN_NIC_REG(0x18),
|
||||
/* crb_rcv_consumer_offset: */
|
||||
NETXEN_NIC_REG(0x1c),
|
||||
/* crb_gloablrcv_ring: */
|
||||
NETXEN_NIC_REG(0x20),
|
||||
},
|
||||
/* Jumbo frames */
|
||||
{
|
||||
/* crb_rcv_producer_offset: */
|
||||
NETXEN_NIC_REG(0x100),
|
||||
/* crb_rcv_consumer_offset: */
|
||||
NETXEN_NIC_REG(0x104),
|
||||
/* crb_gloablrcv_ring: */
|
||||
NETXEN_NIC_REG(0x108),
|
||||
}
|
||||
},
|
||||
/* crb_rcvstatus_ring: */
|
||||
NETXEN_NIC_REG(0x24),
|
||||
/* crb_rcv_status_producer: */
|
||||
NETXEN_NIC_REG(0x28),
|
||||
/* crb_rcv_status_consumer: */
|
||||
NETXEN_NIC_REG(0x2c),
|
||||
/* crb_rcvpeg_state: */
|
||||
NETXEN_NIC_REG(0x48),
|
||||
|
||||
},
|
||||
/*
|
||||
* Instance 1,
|
||||
*/
|
||||
{
|
||||
/* rcv_desc_crb: */
|
||||
{
|
||||
{
|
||||
/* crb_rcv_producer_offset: */
|
||||
NETXEN_NIC_REG(0x80),
|
||||
/* crb_rcv_consumer_offset: */
|
||||
NETXEN_NIC_REG(0x84),
|
||||
/* crb_globalrcv_ring: */
|
||||
NETXEN_NIC_REG(0x88),
|
||||
},
|
||||
/* Jumbo frames */
|
||||
{
|
||||
/* crb_rcv_producer_offset: */
|
||||
NETXEN_NIC_REG(0x10C),
|
||||
/* crb_rcv_consumer_offset: */
|
||||
NETXEN_NIC_REG(0x110),
|
||||
/* crb_globalrcv_ring: */
|
||||
NETXEN_NIC_REG(0x114),
|
||||
}
|
||||
},
|
||||
/* crb_rcvstatus_ring: */
|
||||
NETXEN_NIC_REG(0x8c),
|
||||
/* crb_rcv_status_producer: */
|
||||
NETXEN_NIC_REG(0x90),
|
||||
/* crb_rcv_status_consumer: */
|
||||
NETXEN_NIC_REG(0x94),
|
||||
/* crb_rcvpeg_state: */
|
||||
NETXEN_NIC_REG(0x98),
|
||||
},
|
||||
};
|
||||
#else
|
||||
extern struct netxen_recv_crb recv_crb_registers[];
|
||||
#endif /* DEFINE_GLOBAL_RECEIVE_CRB */
|
||||
|
||||
#endif /* __NIC_PHAN_REG_H_ */
|
||||
Loading…
Reference in New Issue