arm64: tegra: Device tree changes for v4.12-rc1
This adds a bunch of features for Tegra186, such as PMC, ethernet, I2C, SDHCI and GPIO. It also enables various features on the P2771 devkit. A small fix is made to the compatible string list for the flow controller on Tegra132 and the IOMMU is enabled for host1x on Tegra210. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAljmyEETHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zof6+D/4q3/aatnXbrQ+nYvcXdSYq+ISOaCEA Ll23ePKJvTiPGE1+rIy64NyljAdiSFhul6PCFumCaX39J7QoOgY5AE3DvOgx/xEh RhAqRxlq04rYqTqlNovwgbV0XI8TDYAnuelGrRp6f6gC8J2EqReFIWG9P+11MYcD Zim6Xzyl42v0u//3oy/JOhE0iEK1/Mv35Wv8VTxHFsh+TMhhm2M+vAFDgFeVv6q0 863ooxrw935FbAR6LRm6cIiyF1EknQ5z7LgDnJVHFke/nAggcItldkgRqijA4C8c ctJTvigOIZmhoCfF6Jh5fAuPCqhxsvZAoC5h8kWKmqw7tDS4Aysaf8cZDo034yrO y6HC632iqP3UvNj5WMTExBC4FFwHx6wp/ESdYsxih00F0/hOPsObeorUiQ2DJkjc 0XMWKEXuBWzyRYYFSY1zgs9rq0nmqlX/TL6+Lrz1FPzgMWXFvt9B2cCnssDGa7U6 uzKezAbU8eTg5muawYnStttJROdxbHBaDbRNVkvbtYUV2mYfmfAqVD5RjrssYerD cLoIU0jgjZa0wk1D0JUX6quT0rvRpmGo013G6Luk01D1jG2udTkNXIexyBtndJmr ZEuzfRLAAdDo7OpirgcWxpja4m/17Dp/LnLg1tzksHk3UxnrFD83Hrtpgif+ci8x +t8oScJqGFhgiQ== =yRy3 -----END PGP SIGNATURE----- Merge tag 'tegra-for-4.12-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt64 arm64: tegra: Device tree changes for v4.12-rc1 This adds a bunch of features for Tegra186, such as PMC, ethernet, I2C, SDHCI and GPIO. It also enables various features on the P2771 devkit. A small fix is made to the compatible string list for the flow controller on Tegra132 and the IOMMU is enabled for host1x on Tegra210. * tag 'tegra-for-4.12-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Update the Tegra132 flowctrl compatible string arm64: tegra: Add GPU node for Tegra186 arm64: tegra: Enable IOMMU for host1x on Tegra210 arm64: tegra: Enable VIC on Tegra210 arm64: tegra: Add GPIO expanders on P2771 arm64: tegra: Add power monitors on P2771 arm64: tegra: Add GPIO keys on P2771 arm64: tegra: Enable current monitors on P3310 arm64: tegra: Enable SD/MMC slot on P2771 arm64: tegra: Enable SDHCI controllers on P3110 arm64: tegra: Add initial power tree for P3310 arm64: tegra: Enable ethernet on P3310 arm64: tegra: Enable I2C controllers on P3310 arm64: tegra: Invert the PMC interrupt on P3310 arm64: tegra: Add ethernet support for Tegra186 arm64: tegra: Add PMC controller on Tegra186 Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
3d3949df4e
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@ -224,7 +224,7 @@
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};
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flow-controller@60007000 {
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compatible = "nvidia,tegra124-flowctrl";
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compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl";
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reg = <0x0 0x60007000 0x0 0x1000>;
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};
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@ -1,8 +1,99 @@
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/dts-v1/;
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#include <dt-bindings/input/linux-event-codes.h>
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#include "tegra186-p3310.dtsi"
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/ {
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model = "NVIDIA Tegra186 P2771-0000 Development Board";
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compatible = "nvidia,p2771-0000", "nvidia,tegra186";
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i2c@3160000 {
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power-monitor@42 {
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compatible = "ti,ina3221";
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reg = <0x42>;
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};
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power-monitor@43 {
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compatible = "ti,ina3221";
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reg = <0x43>;
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};
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exp1: gpio@74 {
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compatible = "ti,tca9539";
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reg = <0x74>;
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interrupt-parent = <&gpio>;
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interrupts = <TEGRA_MAIN_GPIO(Y, 0) GPIO_ACTIVE_LOW>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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exp2: gpio@77 {
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compatible = "ti,tca9539";
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reg = <0x77>;
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interrupt-parent = <&gpio>;
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interrupts = <TEGRA_MAIN_GPIO(Y, 6) GPIO_ACTIVE_LOW>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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};
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/* SDMMC1 (SD/MMC) */
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sdhci@3400000 {
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status = "okay";
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vmmc-supply = <&vdd_sd>;
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};
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gpio-keys {
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compatible = "gpio-keys";
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power {
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label = "Power";
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gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 0)
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GPIO_ACTIVE_LOW>;
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linux,input-type = <EV_KEY>;
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linux,code = <KEY_POWER>;
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debounce-interval = <10>;
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wakeup-source;
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};
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volume-up {
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label = "Volume Up";
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gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 1)
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GPIO_ACTIVE_LOW>;
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linux,input-type = <EV_KEY>;
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linux,code = <KEY_VOLUMEUP>;
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debounce-interval = <10>;
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};
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volume-down {
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label = "Volume Down";
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gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 2)
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GPIO_ACTIVE_LOW>;
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linux,input-type = <EV_KEY>;
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linux,code = <KEY_VOLUMEDOWN>;
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debounce-interval = <10>;
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};
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};
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regulators {
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vdd_sd: regulator@100 {
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compatible = "regulator-fixed";
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reg = <100>;
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regulator-name = "SD_CARD_SW_PWR";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio TEGRA_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>;
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enable-active-high;
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vin-supply = <&vdd_3v3_sys>;
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};
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};
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};
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@ -1,11 +1,23 @@
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#include "tegra186.dtsi"
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#include <dt-bindings/mfd/max77620.h>
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/ {
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model = "NVIDIA Tegra186 P3310 Processor Module";
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compatible = "nvidia,p3310", "nvidia,tegra186";
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aliases {
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sdhci0 = "/sdhci@3460000";
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sdhci1 = "/sdhci@3400000";
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serial0 = &uarta;
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i2c0 = "/bpmp/i2c";
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i2c1 = "/i2c@3160000";
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i2c2 = "/i2c@c240000";
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i2c3 = "/i2c@3180000";
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i2c4 = "/i2c@3190000";
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i2c5 = "/i2c@31c0000";
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i2c6 = "/i2c@c250000";
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i2c7 = "/i2c@31e0000";
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};
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chosen {
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@ -18,14 +30,99 @@
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reg = <0x0 0x80000000 0x2 0x00000000>;
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};
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ethernet@2490000 {
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status = "okay";
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phy-reset-gpios = <&gpio TEGRA_MAIN_GPIO(M, 4) GPIO_ACTIVE_LOW>;
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phy-handle = <&phy>;
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phy-mode = "rgmii";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy: phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0x0>;
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interrupt-parent = <&gpio>;
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interrupts = <TEGRA_MAIN_GPIO(M, 5) IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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};
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serial@3100000 {
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status = "okay";
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};
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i2c@3160000 {
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status = "okay";
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power-monitor@40 {
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compatible = "ti,ina3221";
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reg = <0x40>;
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};
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power-monitor@41 {
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compatible = "ti,ina3221";
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reg = <0x41>;
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};
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};
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i2c@3180000 {
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status = "okay";
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};
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i2c@3190000 {
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status = "okay";
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};
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i2c@31c0000 {
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status = "okay";
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};
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i2c@31e0000 {
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status = "okay";
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};
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/* SDMMC1 (SD/MMC) */
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sdhci@3400000 {
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cd-gpios = <&gpio TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio TEGRA_MAIN_GPIO(P, 4) GPIO_ACTIVE_LOW>;
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vqmmc-supply = <&vddio_sdmmc1>;
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};
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/* SDMMC3 (SDIO) */
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sdhci@3440000 {
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status = "okay";
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};
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/* SDMMC4 (eMMC) */
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sdhci@3460000 {
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status = "okay";
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bus-width = <8>;
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non-removable;
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vqmmc-supply = <&vdd_1v8_ap>;
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vmmc-supply = <&vdd_3v3_sys>;
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};
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hsp@3c00000 {
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status = "okay";
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};
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i2c@c240000 {
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status = "okay";
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};
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i2c@c250000 {
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status = "okay";
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};
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pmc@c360000 {
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nvidia,invert-interrupt;
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};
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cpus {
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cpu@0 {
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enable-method = "psci";
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@ -53,7 +150,192 @@
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};
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bpmp {
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status = "okay";
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i2c {
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status = "okay";
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pmic: pmic@3c {
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compatible = "maxim,max77620";
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reg = <0x3c>;
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interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <2>;
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interrupt-controller;
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#gpio-cells = <2>;
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gpio-controller;
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pinctrl-names = "default";
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pinctrl-0 = <&max77620_default>;
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max77620_default: pinmux {
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gpio0 {
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pins = "gpio0";
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function = "gpio";
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};
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gpio1 {
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pins = "gpio1";
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function = "fps-out";
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maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
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};
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gpio2 {
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pins = "gpio2";
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function = "fps-out";
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maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
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};
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gpio3 {
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pins = "gpio3";
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function = "fps-out";
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maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
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};
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gpio4 {
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pins = "gpio4";
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function = "32k-out1";
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drive-push-pull = <1>;
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};
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gpio5 {
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pins = "gpio5";
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function = "gpio";
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drive-push-pull = <0>;
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};
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gpio6 {
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pins = "gpio6";
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function = "gpio";
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drive-push-pull = <1>;
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};
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gpio7 {
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pins = "gpio7";
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function = "gpio";
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drive-push-pull = <0>;
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};
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};
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fps {
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fps0 {
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maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
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maxim,shutdown-fps-time-period-us = <640>;
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};
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fps1 {
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maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
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maxim,shutdown-fps-time-period-us = <640>;
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};
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fps2 {
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maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
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maxim,shutdown-fps-time-period-us = <640>;
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};
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};
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regulators {
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in-sd0-supply = <&vdd_5v0_sys>;
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in-sd1-supply = <&vdd_5v0_sys>;
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in-sd2-supply = <&vdd_5v0_sys>;
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in-sd3-supply = <&vdd_5v0_sys>;
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in-ldo0-1-supply = <&vdd_5v0_sys>;
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in-ldo2-supply = <&vdd_5v0_sys>;
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in-ldo3-5-supply = <&vdd_5v0_sys>;
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in-ldo4-6-supply = <&vdd_1v8>;
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in-ldo7-8-supply = <&avdd_dsi_csi>;
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sd0 {
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regulator-name = "VDD_DDR_1V1_PMIC";
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1100000>;
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regulator-always-on;
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regulator-boot-on;
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};
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avdd_dsi_csi: sd1 {
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regulator-name = "AVDD_DSI_CSI_1V2";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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/* XXX */
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regulator-always-on;
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regulator-boot-on;
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};
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vdd_1v8: sd2 {
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regulator-name = "VDD_1V8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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/* XXX */
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regulator-always-on;
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regulator-boot-on;
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};
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vdd_3v3_sys: sd3 {
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regulator-name = "VDD_3V3_SYS";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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/* XXX */
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regulator-always-on;
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regulator-boot-on;
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};
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ldo0 {
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regulator-name = "VDD_1V8_AP_PLL";
|
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regulator-min-microvolt = <1800000>;
|
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regulator-max-microvolt = <1800000>;
|
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/* XXX */
|
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regulator-always-on;
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regulator-boot-on;
|
||||
};
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ldo2 {
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regulator-name = "VDDIO_3V3_AOHV";
|
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regulator-min-microvolt = <3300000>;
|
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regulator-max-microvolt = <3300000>;
|
||||
/* XXX */
|
||||
regulator-always-on;
|
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regulator-boot-on;
|
||||
};
|
||||
|
||||
vddio_sdmmc1: ldo3 {
|
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regulator-name = "VDDIO_SDMMC1_AP";
|
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regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
ldo4 {
|
||||
regulator-name = "VDD_RTC";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
};
|
||||
|
||||
vddio_sdmmc3: ldo5 {
|
||||
regulator-name = "VDDIO_SDMMC3_AP";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
};
|
||||
|
||||
avdd_1v05: ldo7 {
|
||||
regulator-name = "VDD_HDMI_1V05";
|
||||
regulator-min-microvolt = <1050000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
/* XXX */
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_pex: ldo8 {
|
||||
regulator-name = "VDD_PEX_1V05";
|
||||
regulator-min-microvolt = <1050000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
/* XXX */
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
|
|
@ -61,4 +343,39 @@
|
|||
status = "okay";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vdd_5v0_sys: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
|
||||
regulator-name = "VDD_5V0_SYS";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_1v8_ap: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
|
||||
regulator-name = "VDD_1V8_AP";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
/* XXX */
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
vin-supply = <&vdd_1v8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
#include <dt-bindings/gpio/tegra186-gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/mailbox/tegra186-hsp.h>
|
||||
#include <dt-bindings/power/tegra186-powergate.h>
|
||||
#include <dt-bindings/reset/tegra186-reset.h>
|
||||
|
||||
/ {
|
||||
|
|
@ -27,6 +28,37 @@
|
|||
gpio-controller;
|
||||
};
|
||||
|
||||
ethernet@2490000 {
|
||||
compatible = "nvidia,tegra186-eqos",
|
||||
"snps,dwc-qos-ethernet-4.10";
|
||||
reg = <0x0 0x02490000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
|
||||
<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
|
||||
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
|
||||
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
|
||||
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
|
||||
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
|
||||
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
|
||||
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
|
||||
<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
|
||||
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
|
||||
clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
|
||||
<&bpmp TEGRA186_CLK_EQOS_AXI>,
|
||||
<&bpmp TEGRA186_CLK_EQOS_RX>,
|
||||
<&bpmp TEGRA186_CLK_EQOS_TX>,
|
||||
<&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
|
||||
clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
|
||||
resets = <&bpmp TEGRA186_RESET_EQOS>;
|
||||
reset-names = "eqos";
|
||||
status = "disabled";
|
||||
|
||||
snps,write-requests = <1>;
|
||||
snps,read-requests = <3>;
|
||||
snps,burst-map = <0x7>;
|
||||
snps,txpbl = <32>;
|
||||
snps,rxpbl = <8>;
|
||||
};
|
||||
|
||||
uarta: serial@3100000 {
|
||||
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x0 0x03100000 0x0 0x40>;
|
||||
|
|
@ -307,6 +339,33 @@
|
|||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pmc@c360000 {
|
||||
compatible = "nvidia,tegra186-pmc";
|
||||
reg = <0 0x0c360000 0 0x10000>,
|
||||
<0 0x0c370000 0 0x10000>,
|
||||
<0 0x0c380000 0 0x10000>,
|
||||
<0 0x0c390000 0 0x10000>;
|
||||
reg-names = "pmc", "wake", "aotag", "scratch";
|
||||
};
|
||||
|
||||
gpu@17000000 {
|
||||
compatible = "nvidia,gp10b";
|
||||
reg = <0x0 0x17000000 0x0 0x1000000>,
|
||||
<0x0 0x18000000 0x0 0x1000000>;
|
||||
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "stall", "nonstall";
|
||||
|
||||
clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
|
||||
<&bpmp TEGRA186_CLK_GPU>;
|
||||
clock-names = "gpu", "pwr";
|
||||
resets = <&bpmp TEGRA186_RESET_GPU>;
|
||||
reset-names = "gpu";
|
||||
status = "disabled";
|
||||
|
||||
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
|
||||
};
|
||||
|
||||
sysram@30000000 {
|
||||
compatible = "nvidia,tegra186-sysram", "mmio-sram";
|
||||
reg = <0x0 0x30000000 0x0 0x50000>;
|
||||
|
|
|
|||
|
|
@ -89,6 +89,8 @@
|
|||
|
||||
ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
|
||||
|
||||
iommus = <&mc TEGRA_SWGROUP_HC>;
|
||||
|
||||
dpaux1: dpaux@54040000 {
|
||||
compatible = "nvidia,tegra210-dpaux";
|
||||
reg = <0x0 0x54040000 0x0 0x00040000>;
|
||||
|
|
@ -185,7 +187,14 @@
|
|||
vic@54340000 {
|
||||
compatible = "nvidia,tegra210-vic";
|
||||
reg = <0x0 0x54340000 0x0 0x00040000>;
|
||||
status = "disabled";
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_VIC03>;
|
||||
clock-names = "vic";
|
||||
resets = <&tegra_car 178>;
|
||||
reset-names = "vic";
|
||||
|
||||
iommus = <&mc TEGRA_SWGROUP_VIC>;
|
||||
power-domains = <&pd_vic>;
|
||||
};
|
||||
|
||||
nvjpg@54380000 {
|
||||
|
|
@ -755,6 +764,14 @@
|
|||
resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_vic: vic {
|
||||
clocks = <&tegra_car TEGRA210_CLK_VIC03>;
|
||||
clock-names = "vic";
|
||||
resets = <&tegra_car 178>;
|
||||
reset-names = "vic";
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue