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sound updates for 5.17-rc1 

It's a relatively calm development cycle, but still lots of updates in
 the driver side like Intel SOF.  Below are some highlights:
 
 * ALSA / ASoC core:
 - A new kselftest for ALSA control API
 - PCM NO_REWINDS support
 - Potential race fixes around control removals
 - Unify x86 SG-buffer memory allocation code
 - Cleanups and race fixes for ASoC DPCM locking
 
 * ASoC:
 - Refinements and cleanups around the delay() APIs
 - Wider use of dev_err_probe().
 - Continuing cleanups and improvements to the SOF code
 - Support for pin switches in simple-card derived cards
 - Support for AMD Renoir ACP, Asahi Kasei Microdevices AKM4375, Intel
   systems using NAU8825 and MAX98390, Mediatek MT8915, nVidia Tegra20
   S/PDIF, Qualcomm systems using ALC5682I-VS and Texas Instruments
   TLV320ADC3xxx
 
 * HD-audio / USB-audio:
 - Fix deadlock at HD-audio codec unbinding
 - Fixes for Tegra194 HD-audio, new HDA support for CS35L41 codec
 - Quirks for Lenovo and HP machines, Gigabyte mobo, Bose device
 
 * Misc:
 - Fix virmidi drain behavior
 
 Note that the merge of CS35L41 codec support is still half-baked, and
 at least one ACPI change is missing.  Although this won't hinder the
 kernel build itself, we're going to catch up before RC1.
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Merge tag 'sound-5.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound

Pull sound updates from Takashi Iwai:
 "It's a relatively calm development cycle, but still lots of updates in
  the driver side like Intel SOF. Below are some highlights:

  ALSA / ASoC core:
   - A new kselftest for ALSA control API
   - PCM NO_REWINDS support
   - Potential race fixes around control removals
   - Unify x86 SG-buffer memory allocation code
   - Cleanups and race fixes for ASoC DPCM locking

  ASoC:
   - Refinements and cleanups around the delay() APIs
   - Wider use of dev_err_probe().
   - Continuing cleanups and improvements to the SOF code
   - Support for pin switches in simple-card derived cards
   - Support for AMD Renoir ACP, Asahi Kasei Microdevices AKM4375, Intel
     systems using NAU8825 and MAX98390, Mediatek MT8915, nVidia Tegra20
     S/PDIF, Qualcomm systems using ALC5682I-VS and Texas Instruments
     TLV320ADC3xxx

  HD-audio / USB-audio:
   - Fix deadlock at HD-audio codec unbinding
   - Fixes for Tegra194 HD-audio, new HDA support for CS35L41 codec
   - Quirks for Lenovo and HP machines, Gigabyte mobo, Bose device

  Misc:
   - Fix virmidi drain behavior

  Note that the merge of CS35L41 codec support is still half-baked, and
  at least one ACPI change is missing. Although this won't hinder the
  kernel build itself, we're going to catch up before RC1"

* tag 'sound-5.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (415 commits)
  ALSA: hda: intel-dsp-config: reorder the config table
  ALSA: hda: intel-dsp-config: add JasperLake support
  ALSA: hda: cs35l41: fix double free on error in probe()
  ALSA: hda: Fix dependencies of CS35L41 on SPI/I2C buses
  ALSA: hda: Fix dependency on ASoC cs35l41 codec
  ASoC: cs35l41: Add support for hibernate memory retention mode
  ASoC: cs35l41: Update handling of test key registers
  ALSA: intel_hdmi: Check for error num after setting mask
  ASoC: wcd9335: Keep a RX port value for each SLIM RX mux
  ASoC: amd: acp: acp-mach: Change default RT1019 amp dev id
  ALSA: virmidi: Remove duplicated code
  ALSA: seq: virmidi: Add a drain operation
  ASoC: topology: Fix typo
  ASoC: fsl_asrc: refine the check of available clock divider
  ASoC: Intel: bytcr_rt5640: Add support for external GPIO jack-detect
  ASoC: Intel: bytcr_rt5640: Support retrieving the codec IRQ from the AMCR0F28 ACPI dev
  ASoC: rt5640: Add support for boards with an external jack-detect GPIO
  ASoC: rt5640: Allow snd_soc_component_set_jack() to override the codec IRQ
  ASoC: rt5640: Change jack_work to a delayed_work
  ASoC: rt5640: Fix possible NULL pointer deref on resume
  ...
This commit is contained in:
Linus Torvalds 2022-01-14 14:55:38 +01:00
parent e1a7aa25ff 081c73701e
commit 3ceff4ea07
414 changed files with 17577 additions and 5696 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

57
Documentation/devicetree/bindings/sound/ak4375.yaml Normal file
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@ -0,0 +1,57 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/ak4375.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: AK4375 DAC and headphones amplifier Device Tree Bindings
maintainers:
- Vincent Knecht <vincent.knecht@mailoo.org>
properties:
compatible:
const: asahi-kasei,ak4375
reg:
maxItems: 1
'#sound-dai-cells':
const: 0
avdd-supply:
description: regulator phandle for the AVDD power supply.
tvdd-supply:
description: regulator phandle for the TVDD power supply.
pdn-gpios:
description: optional GPIO to set the PDN pin.
required:
- compatible
- reg
- '#sound-dai-cells'
- avdd-supply
- tvdd-supply
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
headphones: audio-codec@10 {
compatible = "asahi-kasei,ak4375";
reg = <0x10>;
avdd-supply = <&reg_headphones_avdd>;
tvdd-supply = <&pm8916_l6>;
pdn-gpios = <&msmgpio 114 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&headphones_pdn_default>;
#sound-dai-cells = <0>;
};
};

5
Documentation/devicetree/bindings/sound/amlogic,aiu.yaml
View File

@ -9,6 +9,9 @@ title: Amlogic AIU audio output controller
maintainers:
- Jerome Brunet <jbrunet@baylibre.com>
allOf:
- $ref: name-prefix.yaml#
properties:
$nodename:
pattern: "^audio-controller@.*"
@ -65,6 +68,8 @@ properties:
resets:
maxItems: 1
sound-name-prefix: true
required:
- "#sound-dai-cells"
- compatible

5
Documentation/devicetree/bindings/sound/amlogic,g12a-toacodec.yaml
View File

@ -9,6 +9,9 @@ title: Amlogic G12a Internal DAC Control Glue
maintainers:
- Jerome Brunet <jbrunet@baylibre.com>
allOf:
- $ref: name-prefix.yaml#
properties:
$nodename:
pattern: "^audio-controller@.*"
@ -31,6 +34,8 @@ properties:
resets:
maxItems: 1
sound-name-prefix: true
required:
- "#sound-dai-cells"
- compatible

5
Documentation/devicetree/bindings/sound/amlogic,t9015.yaml
View File

@ -9,6 +9,9 @@ title: Amlogic T9015 Internal Audio DAC
maintainers:
- Jerome Brunet <jbrunet@baylibre.com>
allOf:
- $ref: name-prefix.yaml#
properties:
$nodename:
pattern: "^audio-controller@.*"
@ -38,6 +41,8 @@ properties:
description:
Analogue power supply.
sound-name-prefix: true
required:
- "#sound-dai-cells"
- compatible

9
Documentation/devicetree/bindings/sound/audio-graph-port.yaml
View File

@ -42,10 +42,15 @@ patternProperties:
$ref: /schemas/types.yaml#/definitions/flag
frame-master:
description: Indicates dai-link frame master.
$ref: /schemas/types.yaml#/definitions/phandle
oneOf:
- $ref: /schemas/types.yaml#/definitions/flag
- $ref: /schemas/types.yaml#/definitions/phandle
bitclock-master:
description: Indicates dai-link bit clock master
$ref: /schemas/types.yaml#/definitions/phandle
oneOf:
- $ref: /schemas/types.yaml#/definitions/flag
- $ref: /schemas/types.yaml#/definitions/phandle
dai-format:
description: audio format.
items:

225
Documentation/devicetree/bindings/sound/cirrus,cs42l42.yaml Normal file
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@ -0,0 +1,225 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/cirrus,cs42l42.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cirrus Logic CS42L42 audio CODEC
maintainers:
- patches@opensource.cirrus.com
description:
The CS42L42 is a low-power audio codec designed for portable applications.
It provides a high-dynamic range, stereo DAC for audio playback and a mono
high-dynamic-range ADC for audio capture. There is an integrated headset
detection block.
properties:
compatible:
enum:
- cirrus,cs42l42
reg:
description:
The I2C address of the CS42L42.
maxItems: 1
VP-supply:
description:
VP power supply.
VCP-supply:
description:
Charge pump power supply.
VD_FILT-supply:
description:
FILT+ power supply.
VL-supply:
description:
Logic power supply.
VA-supply:
description:
Analog power supply.
reset-gpios:
description:
This pin will be asserted and then deasserted to reset the
CS42L42 before communication starts.
maxItems: 1
interrupts:
description:
Interrupt for CS42L42 IRQ line.
maxItems: 1
cirrus,ts-inv:
description: |
Sets the behaviour of the jack plug detect switch.
0 - (Default) Shorted to tip when unplugged, open when plugged.
This is "inverted tip sense (ITS)" in the datasheet.
1 - Open when unplugged, shorted to tip when plugged.
This is "normal tip sense (TS)" in the datasheet.
The CS42L42_TS_INV_* defines are available for this.
$ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0
maximum: 1
cirrus,ts-dbnc-rise:
description: |
Debounce the rising edge of TIP_SENSE_PLUG. With no
debounce, the tip sense pin might be noisy on a plug event.
0 - 0ms
1 - 125ms
2 - 250ms
3 - 500ms
4 - 750ms
5 - 1s (Default)
6 - 1.25s
7 - 1.5s
The CS42L42_TS_DBNCE_* defines are available for this.
$ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0
maximum: 7
cirrus,ts-dbnc-fall:
description: |
Debounce the falling edge of TIP_SENSE_UNPLUG. With no
debounce, the tip sense pin might be noisy on an unplug event.
0 - 0ms
1 - 125ms
2 - 250ms
3 - 500ms
4 - 750ms
5 - 1s (Default)
6 - 1.25s
7 - 1.5s
The CS42L42_TS_DBNCE_* defines are available for this.
$ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0
maximum: 7
cirrus,btn-det-init-dbnce:
description: |
This sets how long to wait after enabling button detection
interrupts before servicing button interrupts, to allow the
HS bias time to settle. Value is in milliseconds.
There may be erroneous button interrupts if this debounce time
is too short.
0ms - 200ms,
Default = 100ms
$ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0
maximum: 200
cirrus,btn-det-event-dbnce:
description: |
This sets how long to wait after receiving a button press
interrupt before processing it. Allows time for the button
press to make a clean connection with the bias resistors.
Value is in milliseconds.
0ms - 20ms,
Default = 10ms
$ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0
maximum: 20
cirrus,bias-lvls:
description: |
For a level-detect headset button scheme, each button will bias
the mic pin to a certain voltage. To determine which button was
pressed, the voltage is compared to sequential, decreasing
voltages, until the compared voltage < bias voltage.
For different hardware setups, a designer might want to tweak this.
This is an array of descending values for the comparator voltage,
given as percent of the HSBIAS voltage.
Array of 4 values, each 0-63
< x1 x2 x3 x4 >
Default = < 15 8 4 1 >
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 4
maxItems: 4
items:
minimum: 0
maximum: 63
cirrus,hs-bias-ramp-rate:
description: |
If present this sets the rate that the HS bias should rise and fall.
The actual rise and fall times depend on external hardware (the
datasheet gives several rise and fall time examples).
0 - Fast rise time; slow, load-dependent fall time
1 - Fast
2 - Slow (default)
3 - Slowest
The CS42L42_HSBIAS_RAMP_* defines are available for this.
$ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0
maximum: 3
cirrus,hs-bias-sense-disable:
description: |
If present the HSBIAS sense is disabled. Configures HSBIAS output
current sense through the external 2.21-k resistor. HSBIAS_SENSE
is a hardware feature to reduce the potential pop noise when the
headset plug is removed slowly. But on some platforms ESD voltage
will affect it causing plug detection to fail, especially with CTIA
headset type. For different hardware setups, a designer might want
to tweak default behavior.
type: boolean
required:
- compatible
- reg
- VP-supply
- VCP-supply
- VD_FILT-supply
- VL-supply
- VA-supply
additionalProperties: false
examples:
- |
#include <dt-bindings/sound/cs42l42.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
cs42l42: cs42l42@48 {
compatible = "cirrus,cs42l42";
reg = <0x48>;
VA-supply = <&dummy_vreg>;
VP-supply = <&dummy_vreg>;
VCP-supply = <&dummy_vreg>;
VD_FILT-supply = <&dummy_vreg>;
VL-supply = <&dummy_vreg>;
reset-gpios = <&axi_gpio_0 1 0>;
interrupt-parent = <&gpio0>;
interrupts = <55 8>;
cirrus,ts-inv = <CS42L42_TS_INV_DIS>;
cirrus,ts-dbnc-rise = <CS42L42_TS_DBNCE_1000>;
cirrus,ts-dbnc-fall = <CS42L42_TS_DBNCE_0>;
cirrus,btn-det-init-dbnce = <100>;
cirrus,btn-det-event-dbnce = <10>;
cirrus,bias-lvls = <0x0F 0x08 0x04 0x01>;
cirrus,hs-bias-ramp-rate = <CS42L42_HSBIAS_RAMP_SLOW>;
};
};

115
Documentation/devicetree/bindings/sound/cs42l42.txt
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@ -1,115 +0,0 @@
CS42L42 audio CODEC
Required properties:
- compatible : "cirrus,cs42l42"
- reg : the I2C address of the device for I2C.
- VP-supply, VCP-supply, VD_FILT-supply, VL-supply, VA-supply :
power supplies for the device, as covered in
Documentation/devicetree/bindings/regulator/regulator.txt.
Optional properties:
- reset-gpios : a GPIO spec for the reset pin. If specified, it will be
deasserted before communication to the codec starts.
- interrupts : IRQ line info CS42L42.
(See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
for further information relating to interrupt properties)
- cirrus,ts-inv : Boolean property. Sets the behaviour of the jack plug
detect switch.
0 = (Default) Shorted to tip when unplugged, open when plugged.
This is "inverted tip sense (ITS)" in the datasheet.
1 = Open when unplugged, shorted to tip when plugged.
This is "normal tip sense (TS)" in the datasheet.
- cirrus,ts-dbnc-rise : Debounce the rising edge of TIP_SENSE_PLUG. With no
debounce, the tip sense pin might be noisy on a plug event.
0 - 0ms,
1 - 125ms,
2 - 250ms,
3 - 500ms,
4 - 750ms,
5 - (Default) 1s,
6 - 1.25s,
7 - 1.5s,
- cirrus,ts-dbnc-fall : Debounce the falling edge of TIP_SENSE_UNPLUG.
With no debounce, the tip sense pin might be noisy on an unplug event.
0 - 0ms,
1 - 125ms,
2 - 250ms,
3 - 500ms,
4 - 750ms,
5 - (Default) 1s,
6 - 1.25s,
7 - 1.5s,
- cirrus,btn-det-init-dbnce : This sets how long the driver sleeps after
enabling button detection interrupts. After auto-detection and before
servicing button interrupts, the HS bias needs time to settle. If you
don't wait, there is possibility for erroneous button interrupt.
0ms - 200ms,
Default = 100ms
- cirrus,btn-det-event-dbnce : This sets how long the driver delays after
receiving a button press interrupt. With level detect interrupts, you want
to wait a small amount of time to make sure the button press is making a
clean connection with the bias resistors.
0ms - 20ms,
Default = 10ms
- cirrus,bias-lvls : For a level-detect headset button scheme, each button
will bias the mic pin to a certain voltage. To determine which button was
pressed, the driver will compare this biased voltage to sequential,
decreasing voltages and will stop when a comparator is tripped,
indicating a comparator voltage < bias voltage. This value represents a
percentage of the internally generated HS bias voltage. For different
hardware setups, a designer might want to tweak this. This is an array of
descending values for the comparator voltage.
Array of 4 values
Each 0-63
< x1 x2 x3 x4 >
Default = < 15 8 4 1>
- cirrus,hs-bias-sense-disable: This is boolean property. If present the
HSBIAS sense is disabled. Configures HSBIAS output current sense through
the external 2.21-k resistor. HSBIAS_SENSE is hardware feature to reduce
the potential pop noise during the headset plug out slowly. But on some
platforms ESD voltage will affect it causing test to fail, especially
with CTIA headset type. For different hardware setups, a designer might
want to tweak default behavior.
Example:
cs42l42: cs42l42@48 {
compatible = "cirrus,cs42l42";
reg = <0x48>;
VA-supply = <&dummy_vreg>;
VP-supply = <&dummy_vreg>;
VCP-supply = <&dummy_vreg>;
VD_FILT-supply = <&dummy_vreg>;
VL-supply = <&dummy_vreg>;
reset-gpios = <&axi_gpio_0 1 0>;
interrupt-parent = <&gpio0>;
interrupts = <55 8>
cirrus,ts-inv = <0x00>;
cirrus,ts-dbnc-rise = <0x05>;
cirrus,ts-dbnc-fall = <0x00>;
cirrus,btn-det-init-dbnce = <100>;
cirrus,btn-det-event-dbnce = <10>;
cirrus,bias-lvls = <0x0F 0x08 0x04 0x01>;
cirrus,hs-bias-ramp-rate = <0x02>;
};

5
Documentation/devicetree/bindings/sound/linux,spdif-dit.yaml
View File

@ -9,6 +9,9 @@ title: Dummy SPDIF Transmitter Device Tree Bindings
maintainers:
- Mark Brown <broonie@kernel.org>
allOf:
- $ref: name-prefix.yaml#
properties:
compatible:
const: linux,spdif-dit
@ -16,6 +19,8 @@ properties:
"#sound-dai-cells":
const: 0
sound-name-prefix: true
required:
- "#sound-dai-cells"
- compatible

8
Documentation/devicetree/bindings/sound/mt8195-afe-pcm.yaml
View File

@ -19,6 +19,12 @@ properties:
interrupts:
maxItems: 1
memory-region:
maxItems: 1
description: |
Shared memory region for AFE memif. A "shared-dma-pool".
See ../reserved-memory/reserved-memory.txt for details.
mediatek,topckgen:
$ref: "/schemas/types.yaml#/definitions/phandle"
description: The phandle of the mediatek topckgen controller
@ -125,6 +131,7 @@ required:
- power-domains
- clocks
- clock-names
- memory-region
additionalProperties: false
@ -139,6 +146,7 @@ examples:
interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
mediatek,topckgen = <&topckgen>;
power-domains = <&spm 7>; //MT8195_POWER_DOMAIN_AUDIO
memory-region = <&snd_dma_mem_reserved>;
clocks = <&clk26m>,
<&topckgen 163>, //CLK_TOP_APLL1
<&topckgen 166>, //CLK_TOP_APLL2

4
Documentation/devicetree/bindings/sound/mt8195-mt6359-rt1011-rt5682.yaml
View File

@ -16,6 +16,10 @@ properties:
compatible:
const: mediatek,mt8195_mt6359_rt1011_rt5682
model:
$ref: /schemas/types.yaml#/definitions/string
description: User specified audio sound card name
mediatek,platform:
$ref: "/schemas/types.yaml#/definitions/phandle"
description: The phandle of MT8195 ASoC platform.

14
Documentation/devicetree/bindings/sound/mt8195-mt6359-rt1019-rt5682.yaml
View File

@ -16,6 +16,10 @@ properties:
compatible:
const: mediatek,mt8195_mt6359_rt1019_rt5682
model:
$ref: /schemas/types.yaml#/definitions/string
description: User specified audio sound card name
mediatek,platform:
$ref: "/schemas/types.yaml#/definitions/phandle"
description: The phandle of MT8195 ASoC platform.
@ -28,6 +32,16 @@ properties:
$ref: "/schemas/types.yaml#/definitions/phandle"
description: The phandle of MT8195 HDMI codec node.
mediatek,adsp:
$ref: "/schemas/types.yaml#/definitions/phandle"
description: The phandle of MT8195 ADSP platform.
mediatek,dai-link:
$ref: /schemas/types.yaml#/definitions/string-array
description:
A list of the desired dai-links in the sound card. Each entry is a
name defined in the machine driver.
additionalProperties: false
required:

48
Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt
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@ -1,48 +0,0 @@
NVIDIA Tegra audio complex
Required properties:
- compatible : "nvidia,tegra-audio-alc5632"
- clocks : Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names : Must include the following entries:
- pll_a
- pll_a_out0
- mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
- nvidia,model : The user-visible name of this sound complex.
- nvidia,audio-routing : A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
the second being the connection's source. Valid names for sources and
sinks are the ALC5632's pins as documented in the binding for the device
and:
* Headset Stereophone
* Int Spk
* Headset Mic
* Digital Mic
- nvidia,i2s-controller : The phandle of the Tegra I2S controller
- nvidia,audio-codec : The phandle of the ALC5632 audio codec
Example:
sound {
compatible = "nvidia,tegra-audio-alc5632-paz00",
"nvidia,tegra-audio-alc5632";
nvidia,model = "Compal PAZ00";
nvidia,audio-routing =
"Int Spk", "SPK_OUTP",
"Int Spk", "SPK_OUTN",
"Headset Mic","MICBIAS1",
"MIC1_N", "Headset Mic",
"MIC1_P", "Headset Mic",
"Headset Stereophone", "HP_OUT_R",
"Headset Stereophone", "HP_OUT_L";
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&alc5632>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-alc5632.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra audio complex with ALC5632 CODEC
maintainers:
- Jon Hunter <jonathanh@nvidia.com>
- Thierry Reding <thierry.reding@gmail.com>
allOf:
- $ref: nvidia,tegra-audio-common.yaml#
properties:
compatible:
items:
- pattern: '^[a-z0-9]+,tegra-audio-alc5632(-[a-z0-9]+)+$'
- const: nvidia,tegra-audio-alc5632
nvidia,audio-routing:
$ref: /schemas/types.yaml#/definitions/non-unique-string-array
description: |
A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
the second being the connection's source. Valid names for sources and
sinks are the pins (documented in the binding document),
and the jacks on the board.
minItems: 2
items:
enum:
# Board Connectors
- "Headset Stereophone"
- "Int Spk"
- "Headset Mic"
- "Digital Mic"
# CODEC Pins
- SPKOUT
- SPKOUTN
- MICBIAS1
- MIC1
- HPR
- HPL
- DMICDAT
required:
- nvidia,i2s-controller
unevaluatedProperties: false
examples:
- |
sound {
compatible = "nvidia,tegra-audio-alc5632-paz00",
"nvidia,tegra-audio-alc5632";
nvidia,model = "Compal PAZ00";
nvidia,audio-routing = "Int Spk", "SPKOUT",
"Int Spk", "SPKOUTN",
"Headset Mic", "MICBIAS1",
"MIC1", "Headset Mic",
"Headset Stereophone", "HPR",
"Headset Stereophone", "HPL",
"DMICDAT", "Digital Mic";
nvidia,i2s-controller = <&i2s>;
nvidia,audio-codec = <&codec>;
clocks = <&clk 112>, <&clk 113>, <&clk 93>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/sound/nvidia,tegra-audio-common.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Common properties for NVIDIA Tegra audio complexes
maintainers:
- Jon Hunter <jonathanh@nvidia.com>
- Thierry Reding <thierry.reding@gmail.com>
properties:
clocks:
items:
- description: PLL A clock
- description: PLL A OUT0 clock
- description: The Tegra cdev1/extern1 clock, which feeds the card's mclk
clock-names:
items:
- const: pll_a
- const: pll_a_out0
- const: mclk
nvidia,model:
$ref: /schemas/types.yaml#/definitions/string
description: The user-visible name of this sound complex.
nvidia,audio-routing:
$ref: /schemas/types.yaml#/definitions/non-unique-string-array
description: |
A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
the second being the connection's source. Valid names for sources and
sinks are the pins (documented in the binding document),
and the jacks on the board.
nvidia,ac97-controller:
$ref: /schemas/types.yaml#/definitions/phandle
description: The phandle of the AC97 controller
nvidia,i2s-controller:
$ref: /schemas/types.yaml#/definitions/phandle
description: The phandle of the Tegra I2S controller
nvidia,audio-codec:
$ref: /schemas/types.yaml#/definitions/phandle
description: The phandle of audio codec
nvidia,spkr-en-gpios:
maxItems: 1
description: The GPIO that enables the speakers
nvidia,hp-mute-gpios:
maxItems: 1
description: The GPIO that mutes the headphones
nvidia,hp-det-gpios:
maxItems: 1
description: The GPIO that detect headphones are plugged in
nvidia,mic-det-gpios:
maxItems: 1
description: The GPIO that detect microphone is plugged in
nvidia,ear-sel-gpios:
maxItems: 1
description: The GPIO that switch between the microphones
nvidia,int-mic-en-gpios:
maxItems: 1
description: The GPIO that enables the internal microphone
nvidia,ext-mic-en-gpios:
maxItems: 1
description: The GPIO that enables the external microphone
nvidia,headset:
type: boolean
description: The Mic Jack represents state of the headset microphone pin
additionalProperties: true

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@ -44,6 +44,16 @@ properties:
minItems: 1
maxItems: 3
interconnects:
items:
- description: APE read memory client
- description: APE write memory client
interconnect-names:
items:
- const: dma-mem # read
- const: write
iommus:
maxItems: 1

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NVIDIA Tegra audio complex, with MAX98090 CODEC
Required properties:
- compatible : "nvidia,tegra-audio-max98090"
- clocks : Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names : Must include the following entries:
- pll_a
- pll_a_out0
- mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
- nvidia,model : The user-visible name of this sound complex.
- nvidia,audio-routing : A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
the second being the connection's source. Valid names for sources and
sinks are the MAX98090's pins (as documented in its binding), and the jacks
on the board:
* Headphones
* Speakers
* Mic Jack
* Int Mic
- nvidia,i2s-controller : The phandle of the Tegra I2S controller that's
connected to the CODEC.
- nvidia,audio-codec : The phandle of the MAX98090 audio codec.
Optional properties:
- nvidia,hp-det-gpios : The GPIO that detect headphones are plugged in
- nvidia,mic-det-gpios : The GPIO that detect microphones are plugged in
Example:
sound {
compatible = "nvidia,tegra-audio-max98090-venice2",
"nvidia,tegra-audio-max98090";
nvidia,model = "NVIDIA Tegra Venice2";
nvidia,audio-routing =
"Headphones", "HPR",
"Headphones", "HPL",
"Speakers", "SPKR",
"Speakers", "SPKL",
"Mic Jack", "MICBIAS",
"IN34", "Mic Jack";
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&acodec>;
clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
<&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA124_CLK_EXTERN1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-max98090.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra audio complex with MAX98090 CODEC
maintainers:
- Jon Hunter <jonathanh@nvidia.com>
- Thierry Reding <thierry.reding@gmail.com>
allOf:
- $ref: nvidia,tegra-audio-common.yaml#
properties:
compatible:
oneOf:
- items:
- pattern: '^[a-z0-9]+,tegra-audio-max98090(-[a-z0-9]+)+$'
- const: nvidia,tegra-audio-max98090
- items:
- enum:
- nvidia,tegra-audio-max98090-nyan-big
- nvidia,tegra-audio-max98090-nyan-blaze
- const: nvidia,tegra-audio-max98090-nyan
- const: nvidia,tegra-audio-max98090
nvidia,audio-routing:
$ref: /schemas/types.yaml#/definitions/non-unique-string-array
description: |
A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
the second being the connection's source. Valid names for sources and
sinks are the pins (documented in the binding document),
and the jacks on the board.
minItems: 2
items:
enum:
# Board Connectors
- "Headphones"
- "Speakers"
- "Mic Jack"
- "Int Mic"
# CODEC Pins
- MIC1
- MIC2
- DMICL
- DMICR
- IN1
- IN2
- IN3
- IN4
- IN5
- IN6
- IN12
- IN34
- IN56
- HPL
- HPR
- SPKL
- SPKR
- RCVL
- RCVR
- MICBIAS
required:
- nvidia,i2s-controller
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/tegra124-car.h>
sound {
compatible = "nvidia,tegra-audio-max98090-venice2",
"nvidia,tegra-audio-max98090";
nvidia,model = "NVIDIA Tegra Venice2";
nvidia,audio-routing =
"Headphones", "HPR",
"Headphones", "HPL",
"Speakers", "SPKR",
"Speakers", "SPKL",
"Mic Jack", "MICBIAS",
"IN34", "Mic Jack";
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&acodec>;
clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
<&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA124_CLK_EXTERN1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};

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NVIDIA Tegra audio complex, with RT5640 CODEC
Required properties:
- compatible : "nvidia,tegra-audio-rt5640"
- clocks : Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names : Must include the following entries:
- pll_a
- pll_a_out0
- mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
- nvidia,model : The user-visible name of this sound complex.
- nvidia,audio-routing : A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
the second being the connection's source. Valid names for sources and
sinks are the RT5640's pins (as documented in its binding), and the jacks
on the board:
* Headphones
* Speakers
* Mic Jack
- nvidia,i2s-controller : The phandle of the Tegra I2S controller that's
connected to the CODEC.
- nvidia,audio-codec : The phandle of the RT5640 audio codec. This binding
assumes that AIF1 on the CODEC is connected to Tegra.
Optional properties:
- nvidia,hp-det-gpios : The GPIO that detects headphones are plugged in
Example:
sound {
compatible = "nvidia,tegra-audio-rt5640-dalmore",
"nvidia,tegra-audio-rt5640";
nvidia,model = "NVIDIA Tegra Dalmore";
nvidia,audio-routing =
"Headphones", "HPOR",
"Headphones", "HPOL",
"Speakers", "SPORP",
"Speakers", "SPORN",
"Speakers", "SPOLP",
"Speakers", "SPOLN";
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&rt5640>;
nvidia,hp-det-gpios = <&gpio 143 0>; /* GPIO PR7 */
clocks = <&tegra_car 216>, <&tegra_car 217>, <&tegra_car 120>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-rt5640.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra audio complex with RT5639 or RT5640 CODEC
maintainers:
- Jon Hunter <jonathanh@nvidia.com>
- Thierry Reding <thierry.reding@gmail.com>
allOf:
- $ref: nvidia,tegra-audio-common.yaml#
properties:
compatible:
items:
- pattern: '^[a-z0-9]+,tegra-audio-rt56(39|40)(-[a-z0-9]+)+$'
- const: nvidia,tegra-audio-rt5640
nvidia,audio-routing:
$ref: /schemas/types.yaml#/definitions/non-unique-string-array
description: |
A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
the second being the connection's source. Valid names for sources and
sinks are the pins (documented in the binding document),
and the jacks on the board.
minItems: 2
items:
enum:
# Board Connectors
- "Headphones"
- "Speakers"
- "Mic Jack"
# CODEC Pins
- DMIC1
- DMIC2
- MICBIAS1
- IN1P
- IN1R
- IN2P
- IN2R
- HPOL
- HPOR
- LOUTL
- LOUTR
- MONOP
- MONON
- SPOLP
- SPOLN
- SPORP
- SPORN
required:
- nvidia,i2s-controller
unevaluatedProperties: false
examples:
- |
sound {
compatible = "nvidia,tegra-audio-rt5640-dalmore",
"nvidia,tegra-audio-rt5640";
nvidia,model = "NVIDIA Tegra Dalmore";
nvidia,audio-routing =
"Headphones", "HPOR",
"Headphones", "HPOL",
"Speakers", "SPORP",
"Speakers", "SPORN",
"Speakers", "SPOLP",
"Speakers", "SPOLN";
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&rt5640>;
nvidia,hp-det-gpios = <&gpio 143 0>;
clocks = <&clk 216>, <&clk 217>, <&clk 120>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};

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NVIDIA Tegra audio complex, with RT5677 CODEC
Required properties:
- compatible : "nvidia,tegra-audio-rt5677"
- clocks : Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names : Must include the following entries:
- pll_a
- pll_a_out0
- mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
- nvidia,model : The user-visible name of this sound complex.
- nvidia,audio-routing : A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
the second being the connection's source. Valid names for sources and
sinks are the RT5677's pins (as documented in its binding), and the jacks
on the board:
* Headphone
* Speaker
* Headset Mic
* Internal Mic 1
* Internal Mic 2
- nvidia,i2s-controller : The phandle of the Tegra I2S controller that's
connected to the CODEC.
- nvidia,audio-codec : The phandle of the RT5677 audio codec. This binding
assumes that AIF1 on the CODEC is connected to Tegra.
Optional properties:
- nvidia,hp-det-gpios : The GPIO that detects headphones are plugged in
- nvidia,hp-en-gpios : The GPIO that enables headphone amplifier
- nvidia,mic-present-gpios: The GPIO that mic jack is plugged in
- nvidia,dmic-clk-en-gpios : The GPIO that gates DMIC clock signal
Example:
sound {
compatible = "nvidia,tegra-audio-rt5677-ryu",
"nvidia,tegra-audio-rt5677";
nvidia,model = "NVIDIA Tegra Ryu";
nvidia,audio-routing =
"Headphone", "LOUT2",
"Headphone", "LOUT1",
"Headset Mic", "MICBIAS1",
"IN1P", "Headset Mic",
"IN1N", "Headset Mic",
"DMIC L1", "Internal Mic 1",
"DMIC R1", "Internal Mic 1",
"DMIC L2", "Internal Mic 2",
"DMIC R2", "Internal Mic 2",
"Speaker", "PDM1L",
"Speaker", "PDM1R";
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&rt5677>;
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
nvidia,mic-present-gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>;
nvidia,hp-en-gpios = <&rt5677 1 GPIO_ACTIVE_HIGH>;
nvidia,dmic-clk-en-gpios = <&rt5677 2 GPIO_ACTIVE_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
<&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA124_CLK_EXTERN1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-rt5677.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra audio complex with RT5677 CODEC
maintainers:
- Jon Hunter <jonathanh@nvidia.com>
- Thierry Reding <thierry.reding@gmail.com>
allOf:
- $ref: nvidia,tegra-audio-common.yaml#
properties:
compatible:
items:
- pattern: '^[a-z0-9]+,tegra-audio-rt5677(-[a-z0-9]+)+$'
- const: nvidia,tegra-audio-rt5677
nvidia,audio-routing:
$ref: /schemas/types.yaml#/definitions/non-unique-string-array
description: |
A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
the second being the connection's source. Valid names for sources and
sinks are the pins (documented in the binding document),
and the jacks on the board.
minItems: 2
items:
enum:
# Board Connectors
- "Headphone"
- "Speaker"
- "Headset Mic"
- "Internal Mic 1"
- "Internal Mic 2"
# CODEC Pins
- IN1P
- IN1N
- IN2P
- IN2N
- MICBIAS1
- DMIC1
- DMIC2
- DMIC3
- DMIC4
- "DMIC L1"
- "DMIC L2"
- "DMIC L3"
- "DMIC L4"
- "DMIC R1"
- "DMIC R2"
- "DMIC R3"
- "DMIC R4"
- LOUT1
- LOUT2
- LOUT3
- PDM1L
- PDM1R
- PDM2L
- PDM2R
required:
- nvidia,i2s-controller
unevaluatedProperties: false
examples:
- |
sound {
compatible = "nvidia,tegra-audio-rt5677-ryu",
"nvidia,tegra-audio-rt5677";
nvidia,model = "NVIDIA Tegra Ryu";
nvidia,audio-routing =
"Headphone", "LOUT2",
"Headphone", "LOUT1",
"Headset Mic", "MICBIAS1",
"IN1P", "Headset Mic",
"IN1N", "Headset Mic",
"DMIC L1", "Internal Mic 1",
"DMIC R1", "Internal Mic 1",
"DMIC L2", "Internal Mic 2",
"DMIC R2", "Internal Mic 2",
"Speaker", "PDM1L",
"Speaker", "PDM1R";
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&rt5677>;
nvidia,hp-det-gpios = <&gpio 143 0>;
clocks = <&clk 216>,
<&clk 217>,
<&clk 121>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};

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NVIDIA Tegra audio complex, with SGTL5000 CODEC
Required properties:
- compatible : "nvidia,tegra-audio-sgtl5000"
- clocks : Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names : Must include the following entries:
- pll_a
- pll_a_out0
- mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
- nvidia,model : The user-visible name of this sound complex.
- nvidia,audio-routing : A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
the second being the connection's source. Valid names for sources and
sinks are the SGTL5000's pins (as documented in its binding), and the jacks
on the board:
* Headphone Jack
* Line In Jack
* Mic Jack
- nvidia,i2s-controller : The phandle of the Tegra I2S controller that's
connected to the CODEC.
- nvidia,audio-codec : The phandle of the SGTL5000 audio codec.
Example:
sound {
compatible = "toradex,tegra-audio-sgtl5000-apalis_t30",
"nvidia,tegra-audio-sgtl5000";
nvidia,model = "Toradex Apalis T30";
nvidia,audio-routing =
"Headphone Jack", "HP_OUT",
"LINE_IN", "Line In Jack",
"MIC_IN", "Mic Jack";
nvidia,i2s-controller = <&tegra_i2s2>;
nvidia,audio-codec = <&sgtl5000>;
clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
<&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA30_CLK_EXTERN1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-sgtl5000.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra audio complex with SGTL5000 CODEC
maintainers:
- Jon Hunter <jonathanh@nvidia.com>
- Thierry Reding <thierry.reding@gmail.com>
allOf:
- $ref: nvidia,tegra-audio-common.yaml#
properties:
compatible:
items:
- pattern: '^[a-z0-9]+,tegra-audio-sgtl5000([-_][a-z0-9]+)+$'
- const: nvidia,tegra-audio-sgtl5000
nvidia,audio-routing:
$ref: /schemas/types.yaml#/definitions/non-unique-string-array
description: |
A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
the second being the connection's source. Valid names for sources and
sinks are the pins (documented in the binding document),
and the jacks on the board.
minItems: 2
items:
enum:
# Board Connectors
- "Headphone Jack"
- "Line In Jack"
- "Mic Jack"
# CODEC Pins
- HP_OUT
- LINE_OUT
- LINE_IN
- MIC_IN
required:
- nvidia,i2s-controller
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/tegra30-car.h>
sound {
compatible = "toradex,tegra-audio-sgtl5000-apalis_t30",
"nvidia,tegra-audio-sgtl5000";
nvidia,model = "Toradex Apalis T30 SGTL5000";
nvidia,audio-routing =
"Headphone Jack", "HP_OUT",
"LINE_IN", "Line In Jack",
"MIC_IN", "Mic Jack";
nvidia,i2s-controller = <&tegra_i2s2>;
nvidia,audio-codec = <&codec>;
clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
<&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA30_CLK_EXTERN1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};

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NVIDIA Tegra audio complex for TrimSlice
Required properties:
- compatible : "nvidia,tegra-audio-trimslice"
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : Must include the following entries:
"pll_a" (The Tegra clock of that name),
"pll_a_out0" (The Tegra clock of that name),
"mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
- nvidia,i2s-controller : The phandle of the Tegra I2S1 controller
- nvidia,audio-codec : The phandle of the WM8903 audio codec
Example:
sound {
compatible = "nvidia,tegra-audio-trimslice";
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&codec>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-trimslice.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra audio complex with TrimSlice CODEC
maintainers:
- Jon Hunter <jonathanh@nvidia.com>
- Thierry Reding <thierry.reding@gmail.com>
allOf:
- $ref: nvidia,tegra-audio-common.yaml#
properties:
compatible:
const: nvidia,tegra-audio-trimslice
required:
- nvidia,i2s-controller
unevaluatedProperties: false
examples:
- |
sound {
compatible = "nvidia,tegra-audio-trimslice";
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&codec>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};

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NVIDIA Tegra audio complex
Required properties:
- compatible : "nvidia,tegra-audio-wm8753"
- clocks : Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names : Must include the following entries:
- pll_a
- pll_a_out0
- mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
- nvidia,model : The user-visible name of this sound complex.
- nvidia,audio-routing : A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
the second being the connection's source. Valid names for sources and
sinks are the WM8753's pins as documented in the binding for the WM8753,
and the jacks on the board:
* Headphone Jack
* Mic Jack
- nvidia,i2s-controller : The phandle of the Tegra I2S1 controller
- nvidia,audio-codec : The phandle of the WM8753 audio codec
Example:
sound {
compatible = "nvidia,tegra-audio-wm8753-whistler",
"nvidia,tegra-audio-wm8753"
nvidia,model = "tegra-wm8753-harmony";
nvidia,audio-routing =
"Headphone Jack", "LOUT1",
"Headphone Jack", "ROUT1";
nvidia,i2s-controller = <&i2s1>;
nvidia,audio-codec = <&wm8753>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-wm8753.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra audio complex with WM8753 CODEC
maintainers:
- Jon Hunter <jonathanh@nvidia.com>
- Thierry Reding <thierry.reding@gmail.com>
allOf:
- $ref: nvidia,tegra-audio-common.yaml#
properties:
compatible:
items:
- pattern: '^[a-z0-9]+,tegra-audio-wm8753(-[a-z0-9]+)+$'
- const: nvidia,tegra-audio-wm8753
nvidia,audio-routing:
$ref: /schemas/types.yaml#/definitions/non-unique-string-array
description: |
A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
the second being the connection's source. Valid names for sources and
sinks are the pins (documented in the binding document),
and the jacks on the board.
minItems: 2
items:
enum:
# Board Connectors
- "Headphone Jack"
- "Mic Jack"
# CODEC Pins
- LOUT1
- LOUT2
- ROUT1
- ROUT2
- MONO1
- MONO2
- OUT3
- OUT4
- LINE1
- LINE2
- RXP
- RXN
- ACIN
- ACOP
- MIC1N
- MIC1
- MIC2N
- MIC2
- "Mic Bias"
required:
- nvidia,i2s-controller
unevaluatedProperties: false
examples:
- |
sound {
compatible = "nvidia,tegra-audio-wm8753-whistler",
"nvidia,tegra-audio-wm8753";
nvidia,model = "tegra-wm8753-harmony";
nvidia,audio-routing =
"Headphone Jack", "LOUT1",
"Headphone Jack", "ROUT1";
nvidia,i2s-controller = <&i2s1>;
nvidia,audio-codec = <&wm8753>;
clocks = <&clk 112>, <&clk 113>, <&clk 93>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};

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NVIDIA Tegra audio complex
Required properties:
- compatible : "nvidia,tegra-audio-wm8903"
- clocks : Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names : Must include the following entries:
- pll_a
- pll_a_out0
- mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
- nvidia,model : The user-visible name of this sound complex.
- nvidia,audio-routing : A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
the second being the connection's source. Valid names for sources and
sinks are the WM8903's pins (documented in the WM8903 binding document),
and the jacks on the board:
* Headphone Jack
* Int Spk
* Mic Jack
* Int Mic
- nvidia,i2s-controller : The phandle of the Tegra I2S1 controller
- nvidia,audio-codec : The phandle of the WM8903 audio codec
Optional properties:
- nvidia,spkr-en-gpios : The GPIO that enables the speakers
- nvidia,hp-mute-gpios : The GPIO that mutes the headphones
- nvidia,hp-det-gpios : The GPIO that detect headphones are plugged in
- nvidia,int-mic-en-gpios : The GPIO that enables the internal microphone
- nvidia,ext-mic-en-gpios : The GPIO that enables the external microphone
- nvidia,headset : The Mic Jack represents state of the headset microphone pin
Example:
sound {
compatible = "nvidia,tegra-audio-wm8903-harmony",
"nvidia,tegra-audio-wm8903"
nvidia,model = "tegra-wm8903-harmony";
nvidia,audio-routing =
"Headphone Jack", "HPOUTR",
"Headphone Jack", "HPOUTL",
"Int Spk", "ROP",
"Int Spk", "RON",
"Int Spk", "LOP",
"Int Spk", "LON",
"Mic Jack", "MICBIAS",
"IN1L", "Mic Jack";
nvidia,i2s-controller = <&i2s1>;
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&codec 2 0>;
nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-wm8903.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra audio complex with WM8903 CODEC
maintainers:
- Jon Hunter <jonathanh@nvidia.com>
- Thierry Reding <thierry.reding@gmail.com>
allOf:
- $ref: nvidia,tegra-audio-common.yaml#
properties:
compatible:
oneOf:
- items:
- pattern: '^[a-z0-9]+,tegra-audio-wm8903(-[a-z0-9]+)+$'
- const: nvidia,tegra-audio-wm8903
- items:
- pattern: ad,tegra-audio-plutux
- const: nvidia,tegra-audio-wm8903
nvidia,audio-routing:
$ref: /schemas/types.yaml#/definitions/non-unique-string-array
description: |
A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
the second being the connection's source. Valid names for sources and
sinks are the pins (documented in the binding document),
and the jacks on the board.
minItems: 2
items:
enum:
# Board Connectors
- "Headphone Jack"
- "Int Spk"
- "Mic Jack"
- "Int Mic"
# CODEC Pins
- IN1L
- IN1R
- IN2L
- IN2R
- IN3L
- IN3R
- DMICDAT
- HPOUTL
- HPOUTR
- LINEOUTL
- LINEOUTR
- LOP
- LON
- ROP
- RON
- MICBIAS
required:
- nvidia,i2s-controller
unevaluatedProperties: false
examples:
- |
sound {
compatible = "nvidia,tegra-audio-wm8903-harmony",
"nvidia,tegra-audio-wm8903";
nvidia,model = "tegra-wm8903-harmony";
nvidia,audio-routing =
"Headphone Jack", "HPOUTR",
"Headphone Jack", "HPOUTL",
"Int Spk", "ROP",
"Int Spk", "RON",
"Int Spk", "LOP",
"Int Spk", "LON",
"Mic Jack", "MICBIAS",
"IN1L", "Mic Jack";
nvidia,i2s-controller = <&i2s1>;
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&codec 2 0>;
nvidia,hp-det-gpios = <&gpio 178 0>;
nvidia,int-mic-en-gpios = <&gpio 184 0>;
nvidia,ext-mic-en-gpios = <&gpio 185 0>;
clocks = <&clk 112>, <&clk 113>, <&clk 93>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};

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NVIDIA Tegra audio complex
Required properties:
- compatible : "nvidia,tegra-audio-wm9712"
- clocks : Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names : Must include the following entries:
- pll_a
- pll_a_out0
- mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
- nvidia,model : The user-visible name of this sound complex.
- nvidia,audio-routing : A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
the second being the connection's source. Valid names for sources and
sinks are the WM9712's pins, and the jacks on the board:
WM9712 pins:
* MONOOUT
* HPOUTL
* HPOUTR
* LOUT2
* ROUT2
* OUT3
* LINEINL
* LINEINR
* PHONE
* PCBEEP
* MIC1
* MIC2
* Mic Bias
Board connectors:
* Headphone
* LineIn
* Mic
- nvidia,ac97-controller : The phandle of the Tegra AC97 controller
Example:
sound {
compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
"nvidia,tegra-audio-wm9712";
nvidia,model = "Toradex Colibri T20";
nvidia,audio-routing =
"Headphone", "HPOUTL",
"Headphone", "HPOUTR",
"LineIn", "LINEINL",
"LineIn", "LINEINR",
"Mic", "MIC1";
nvidia,ac97-controller = <&ac97>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-wm9712.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra audio complex with WM9712 CODEC
maintainers:
- Jon Hunter <jonathanh@nvidia.com>
- Thierry Reding <thierry.reding@gmail.com>
allOf:
- $ref: nvidia,tegra-audio-common.yaml#
properties:
compatible:
items:
- pattern: '^[a-z0-9]+,tegra-audio-wm9712([-_][a-z0-9]+)+$'
- const: nvidia,tegra-audio-wm9712
nvidia,audio-routing:
$ref: /schemas/types.yaml#/definitions/non-unique-string-array
description: |
A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
the second being the connection's source. Valid names for sources and
sinks are the pins (documented in the binding document),
and the jacks on the board.
minItems: 2
items:
enum:
# Board Connectors
- "Headphone"
- "LineIn"
- "Mic"
# CODEC Pins
- MONOOUT
- HPOUTL
- HPOUTR
- LOUT2
- ROUT2
- OUT3
- LINEINL
- LINEINR
- PHONE
- PCBEEP
- MIC1
- MIC2
- "Mic Bias"
required:
- nvidia,ac97-controller
unevaluatedProperties: false
examples:
- |
sound {
compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
"nvidia,tegra-audio-wm9712";
nvidia,model = "Toradex Colibri T20";
nvidia,audio-routing =
"Headphone", "HPOUTL",
"Headphone", "HPOUTR",
"LineIn", "LINEINL",
"LineIn", "LINEINR",
"Mic", "MIC1";
nvidia,ac97-controller = <&ac97>;
clocks = <&clk 112>, <&clk 113>, <&clk 93>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};

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@ -1,30 +0,0 @@
NVIDIA Tegra 20 I2S controller
Required properties:
- compatible : "nvidia,tegra20-i2s"
- reg : Should contain I2S registers location and length
- interrupts : Should contain I2S interrupt
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names : Must include the following entries:
- i2s
- dmas : Must contain an entry for each entry in clock-names.
See ../dma/dma.txt for details.
- dma-names : Must include the following entries:
- rx
- tx
- clocks : Must contain one entry, for the module clock.
See ../clocks/clock-bindings.txt for details.
Example:
i2s@70002800 {
compatible = "nvidia,tegra20-i2s";
reg = <0x70002800 0x200>;
interrupts = < 45 >;
clocks = <&tegra_car 11>;
resets = <&tegra_car 11>;
reset-names = "i2s";
dmas = <&apbdma 21>, <&apbdma 21>;
dma-names = "rx", "tx";
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/nvidia,tegra20-i2s.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra20 I2S Controller
description: |
The I2S Controller streams synchronous serial audio data between system
memory and an external audio device. The controller supports the I2S Left
Justified Mode, Right Justified Mode, and DSP mode formats.
maintainers:
- Thierry Reding <treding@nvidia.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
const: nvidia,tegra20-i2s
reg:
maxItems: 1
resets:
maxItems: 1
reset-names:
const: i2s
interrupts:
maxItems: 1
clocks:
minItems: 1
dmas:
minItems: 2
dma-names:
items:
- const: rx
- const: tx
nvidia,fixed-parent-rate:
description: |
Specifies whether board prefers parent clock to stay at a fixed rate.
This allows multiple Tegra20 audio components work simultaneously by
limiting number of supportable audio rates.
type: boolean
required:
- compatible
- reg
- resets
- reset-names
- interrupts
- clocks
- dmas
- dma-names
additionalProperties: false
examples:
- |
i2s@70002800 {
compatible = "nvidia,tegra20-i2s";
reg = <0x70002800 0x200>;
interrupts = <45>;
clocks = <&tegra_car 11>;
resets = <&tegra_car 11>;
reset-names = "i2s";
dmas = <&apbdma 21>, <&apbdma 21>;
dma-names = "rx", "tx";
};
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/nvidia,tegra20-spdif.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra20 S/PDIF Controller
description: |
The S/PDIF controller supports both input and output in serial audio
digital interface format. The input controller can digitally recover
a clock from the received stream. The S/PDIF controller is also used
to generate the embedded audio for HDMI output channel.
maintainers:
- Thierry Reding <treding@nvidia.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
const: nvidia,tegra20-spdif
reg:
maxItems: 1
resets:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 2
clock-names:
items:
- const: out
- const: in
dmas:
minItems: 2
dma-names:
items:
- const: rx
- const: tx
"#sound-dai-cells":
const: 0
nvidia,fixed-parent-rate:
description: |
Specifies whether board prefers parent clock to stay at a fixed rate.
This allows multiple Tegra20 audio components work simultaneously by
limiting number of supportable audio rates.
type: boolean
required:
- compatible
- reg
- resets
- interrupts
- clocks
- clock-names
- dmas
- dma-names
- "#sound-dai-cells"
additionalProperties: false
examples:
- |
spdif@70002400 {
compatible = "nvidia,tegra20-spdif";
reg = <0x70002400 0x200>;
interrupts = <77>;
clocks = <&clk 99>, <&clk 98>;
clock-names = "out", "in";
resets = <&rst 10>;
dmas = <&apbdma 3>, <&apbdma 3>;
dma-names = "rx", "tx";
#sound-dai-cells = <0>;
};
...

2
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@ -50,9 +50,11 @@ properties:
- const: hda2codec_2x
resets:
minItems: 2
maxItems: 3
reset-names:
minItems: 2
items:
- const: hda
- const: hda2hdmi

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@ -24,11 +24,23 @@ properties:
'#sound-dai-cells':
const: 0
rcv-gpios:
description: optional GPIO to be asserted when receiver mode is enabled.
sound-name-prefix: true
vddd-supply:
description: regulator phandle for the VDDD power supply.
if:
not:
properties:
compatible:
const: nxp,tfa9897
then:
properties:
rcv-gpios: false
required:
- compatible
- reg
@ -55,3 +67,32 @@ examples:
#sound-dai-cells = <0>;
};
};
- |
#include <dt-bindings/gpio/gpio.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
speaker_codec_top: audio-codec@34 {
compatible = "nxp,tfa9897";
reg = <0x34>;
vddd-supply = <&pm8916_l6>;
rcv-gpios = <&msmgpio 50 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&speaker_top_default>;
sound-name-prefix = "Speaker Top";
#sound-dai-cells = <0>;
};
speaker_codec_bottom: audio-codec@36 {
compatible = "nxp,tfa9897";
reg = <0x36>;
vddd-supply = <&pm8916_l6>;
rcv-gpios = <&msmgpio 111 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&speaker_bottom_default>;
sound-name-prefix = "Speaker Bottom";
#sound-dai-cells = <0>;
};
};

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@ -1,96 +0,0 @@
* Qualcomm Technologies APQ8016 SBC ASoC machine driver
This node models the Qualcomm Technologies APQ8016 SBC ASoC machine driver
Required properties:
- compatible : "qcom,apq8016-sbc-sndcard"
- pinctrl-N : One property must exist for each entry in
pinctrl-names. See ../pinctrl/pinctrl-bindings.txt
for details of the property values.
- pinctrl-names : Must contain a "default" entry.
- reg : Must contain an address for each entry in reg-names.
- reg-names : A list which must include the following entries:
* "mic-iomux"
* "spkr-iomux"
- qcom,model : Name of the sound card.
- qcom,audio-routing : A list of the connections between audio components.
Each entry is a pair of strings, the first being the
connection's sink, the second being the connection's
source. Valid names could be power supplies, MicBias
of msm8x16_wcd codec and the jacks on the board:
Power supplies:
* MIC BIAS External1
* MIC BIAS External2
* MIC BIAS Internal1
* MIC BIAS Internal2
Board connectors:
* Headset Mic
* Secondary Mic
* DMIC
* Ext Spk
Optional properties:
- aux-devs : A list of phandles for auxiliary devices (e.g. analog
amplifiers) that do not appear directly within the DAI
links. Should be connected to another audio component
using "qcom,audio-routing".
Dai-link subnode properties and subnodes:
Required dai-link subnodes:
- cpu : CPU sub-node
- codec : CODEC sub-node
Required CPU/CODEC subnodes properties:
-link-name : Name of the dai link.
-sound-dai : phandle/s and port of CPU/CODEC
Example:
sound: sound {
compatible = "qcom,apq8016-sbc-sndcard";
reg = <0x07702000 0x4>, <0x07702004 0x4>;
reg-names = "mic-iomux", "spkr-iomux";
qcom,model = "DB410c";
qcom,audio-routing =
"MIC BIAS External1", "Handset Mic",
"MIC BIAS Internal2", "Headset Mic",
"MIC BIAS External1", "Secondary Mic",
"AMIC1", "MIC BIAS External1",
"AMIC2", "MIC BIAS Internal2",
"AMIC3", "MIC BIAS External1",
"DMIC1", "MIC BIAS Internal1",
"MIC BIAS Internal1", "Digital Mic1",
"DMIC2", "MIC BIAS Internal1",
"MIC BIAS Internal1", "Digital Mic2";
/* I2S - Internal codec */
internal-dai-link@0 {
cpu { /* PRIMARY */
sound-dai = <&lpass MI2S_PRIMARY>;
};
codec {
sound-dai = <&lpass_codec 0>, <&wcd_codec 0>;
};
};
/* External Primary or External Secondary -ADV7533 HDMI */
external-dai-link@0 {
link-name = "ADV7533";
cpu { /* QUAT */
sound-dai = <&lpass MI2S_QUATERNARY>;
};
codec {
sound-dai = <&adv_bridge 0>;
};
};
};

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@ -4,18 +4,20 @@
$id: http://devicetree.org/schemas/sound/qcom,sm8250.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies Inc. SM8250 ASoC sound card driver
title: Qualcomm Technologies Inc. ASoC sound card drivers
maintainers:
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
description:
This bindings describes SC8250 SoC based sound cards
This bindings describes Qualcomm SoC based sound cards
which uses LPASS internal codec for audio.
properties:
compatible:
enum:
- qcom,apq8016-sbc-sndcard
- qcom,msm8916-qdsp6-sndcard
- qcom,sm8250-sndcard
- qcom,qrb5165-rb5-sndcard
@ -27,10 +29,28 @@ properties:
being the connection's source. Valid names could be power supplies,
MicBias of codec and the jacks on the board.
aux-devs:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: |
List of phandles pointing to auxiliary devices, such
as amplifiers, to be added to the sound card.
model:
$ref: /schemas/types.yaml#/definitions/string
description: User visible long sound card name
pin-switches:
description: List of widget names for which pin switches should be created.
$ref: /schemas/types.yaml#/definitions/string-array
widgets:
description: User specified audio sound widgets.
$ref: /schemas/types.yaml#/definitions/non-unique-string-array
# Only valid for some compatibles (see allOf if below)
reg: true
reg-names: true
patternProperties:
".*-dai-link$":
description:
@ -73,6 +93,34 @@ required:
- compatible
- model
allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,apq8016-sbc-sndcard
- qcom,msm8916-qdsp6-sndcard
then:
properties:
reg:
items:
- description: Microphone I/O mux register address
- description: Speaker I/O mux register address
reg-names:
items:
- const: mic-iomux
- const: spkr-iomux
required:
- compatible
- model
- reg
- reg-names
else:
properties:
reg: false
reg-names: false
additionalProperties: false
examples:
@ -86,10 +134,7 @@ examples:
audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
"SpkrRight IN", "WSA_SPK2 OUT",
"VA DMIC0", "vdd-micb",
"VA DMIC1", "vdd-micb",
"MM_DL1", "MultiMedia1 Playback",
"MM_DL2", "MultiMedia2 Playback",
"MultiMedia3 Capture", "MM_UL3";
"VA DMIC1", "vdd-micb";
mm1-dai-link {
link-name = "MultiMedia0";
@ -157,3 +202,98 @@ examples:
};
};
};
- |
#include <dt-bindings/sound/qcom,lpass.h>
sound@7702000 {
compatible = "qcom,apq8016-sbc-sndcard";
reg = <0x07702000 0x4>, <0x07702004 0x4>;
reg-names = "mic-iomux", "spkr-iomux";
model = "DB410c";
audio-routing =
"AMIC2", "MIC BIAS Internal2",
"AMIC3", "MIC BIAS External1";
pinctrl-0 = <&cdc_pdm_lines_act &ext_sec_tlmm_lines_act &ext_mclk_tlmm_lines_act>;
pinctrl-1 = <&cdc_pdm_lines_sus &ext_sec_tlmm_lines_sus &ext_mclk_tlmm_lines_sus>;
pinctrl-names = "default", "sleep";
quaternary-dai-link {
link-name = "ADV7533";
cpu {
sound-dai = <&lpass MI2S_QUATERNARY>;
};
codec {
sound-dai = <&adv_bridge 0>;
};
};
primary-dai-link {
link-name = "WCD";
cpu {
sound-dai = <&lpass MI2S_PRIMARY>;
};
codec {
sound-dai = <&lpass_codec 0>, <&wcd_codec 0>;
};
};
tertiary-dai-link {
link-name = "WCD-Capture";
cpu {
sound-dai = <&lpass MI2S_TERTIARY>;
};
codec {
sound-dai = <&lpass_codec 1>, <&wcd_codec 1>;
};
};
};
- |
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/sound/qcom,q6asm.h>
sound@7702000 {
compatible = "qcom,msm8916-qdsp6-sndcard";
reg = <0x07702000 0x4>, <0x07702004 0x4>;
reg-names = "mic-iomux", "spkr-iomux";
model = "msm8916";
widgets =
"Speaker", "Speaker",
"Headphone", "Headphones";
pin-switches = "Speaker";
audio-routing =
"Speaker", "Speaker Amp OUT",
"Speaker Amp IN", "HPH_R",
"Headphones", "HPH_L",
"Headphones", "HPH_R",
"AMIC1", "MIC BIAS Internal1",
"AMIC2", "MIC BIAS Internal2",
"AMIC3", "MIC BIAS Internal3";
aux-devs = <&speaker_amp>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cdc_pdm_lines_act>;
pinctrl-1 = <&cdc_pdm_lines_sus>;
mm1-dai-link {
link-name = "MultiMedia1";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
};
};
primary-dai-link {
link-name = "Primary MI2S";
cpu {
sound-dai = <&q6afedai PRIMARY_MI2S_RX>;
};
platform {
sound-dai = <&q6routing>;
};
codec {
sound-dai = <&lpass_codec 0>, <&wcd_codec 0>;
};
};
};

4
Documentation/devicetree/bindings/sound/realtek,rt5682s.yaml
View File

@ -61,6 +61,10 @@ properties:
description: |
Set the delay time (ms) for the requirement of the particular DMIC.
realtek,amic-delay-ms:
description: |
Set the delay time (ms) for the requirement of the particular platform or AMIC.
realtek,dmic-clk-driving-high:
type: boolean
description: |

8
Documentation/devicetree/bindings/sound/simple-audio-amplifier.yaml
View File

@ -9,6 +9,9 @@ title: Simple Audio Amplifier Device Tree Bindings
maintainers:
- Jerome Brunet <jbrunet@baylibre.com>
allOf:
- $ref: name-prefix.yaml#
properties:
compatible:
enum:
@ -22,10 +25,7 @@ properties:
description: >
power supply for the device
sound-name-prefix:
$ref: /schemas/types.yaml#/definitions/string
description: >
See ./name-prefix.txt
sound-name-prefix: true
required:
- compatible

137
Documentation/devicetree/bindings/sound/ti,tlv320adc3xxx.yaml Normal file
View File

@ -0,0 +1,137 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/ti,tlv320adc3xxx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments TLV320ADC3001/TLV320ADC3101 Stereo ADC
maintainers:
- Ricard Wanderlof <ricardw@axis.com>
description: |
Texas Instruments TLV320ADC3001 and TLV320ADC3101 Stereo ADC
https://www.ti.com/product/TLV320ADC3001
https://www.ti.com/product/TLV320ADC3101
properties:
compatible:
enum:
- ti,tlv320adc3001
- ti,tlv320adc3101
reg:
maxItems: 1
description: I2C address
'#sound-dai-cells':
const: 0
'#gpio-cells':
const: 2
gpio-controller: true
reset-gpios:
maxItems: 1
description: GPIO pin used for codec reset (RESET pin)
clocks:
maxItems: 1
description: Master clock (MCLK)
ti,dmdin-gpio1:
$ref: /schemas/types.yaml#/definitions/uint32
enum:
- 0 # ADC3XXX_GPIO_DISABLED - I/O buffers powered down and not used
- 1 # ADC3XXX_GPIO_INPUT - Various non-GPIO input functions
- 2 # ADC3XXX_GPIO_GPI - General purpose input
- 3 # ADC3XXX_GPIO_GPO - General purpose output
- 4 # ADC3XXX_GPIO_CLKOUT - Clock source set in CLKOUT_MUX reg
- 5 # ADC3XXX_GPIO_INT1 - INT1 output
- 6 # ADC3XXX_GPIO_SECONDARY_BCLK - Codec interface secondary BCLK
- 7 # ADC3XXX_GPIO_SECONDARY_WCLK - Codec interface secondary WCLK
default: 0
description: |
Configuration for DMDIN/GPIO1 pin.
When ADC3XXX_GPIO_GPO is configured, this causes corresponding the
ALSA control "GPIOx Output" to appear, as a switch control.
ti,dmclk-gpio2:
$ref: /schemas/types.yaml#/definitions/uint32
enum:
- 0 # ADC3XXX_GPIO_DISABLED - I/O buffers powered down and not used
- 1 # ADC3XXX_GPIO_INPUT - Various non-GPIO input functions
- 2 # ADC3XXX_GPIO_GPI - General purpose input
- 3 # ADC3XXX_GPIO_GPO - General purpose output
- 4 # ADC3XXX_GPIO_CLKOUT - Clock source set in CLKOUT_MUX reg
- 5 # ADC3XXX_GPIO_INT1 - INT1 output
- 6 # ADC3XXX_GPIO_SECONDARY_BCLK - Codec interface secondary BCLK
- 7 # ADC3XXX_GPIO_SECONDARY_WCLK - Codec interface secondary WCLK
default: 0
description: |
Configuration for DMCLK/GPIO2 pin.
When ADC3XXX_GPIO_GPO is configured, this causes corresponding the
ALSA control "GPIOx Output" to appear, as a switch control.
Note that there is currently no support for reading the GPIO pins as
inputs.
ti,micbias1-vg:
$ref: /schemas/types.yaml#/definitions/uint32
enum:
- 0 # ADC3XXX_MICBIAS_OFF - Mic bias is powered down
- 1 # ADC3XXX_MICBIAS_2_0V - Mic bias is set to 2.0V
- 2 # ADC3XXX_MICBIAS_2_5V - Mic bias is set to 2.5V
- 3 # ADC3XXX_MICBIAS_AVDD - Mic bias is same as AVDD supply
default: 0
description: |
Mic bias voltage output on MICBIAS1 pin
ti,micbias2-vg:
$ref: /schemas/types.yaml#/definitions/uint32
enum:
- 0 # ADC3XXX_MICBIAS_OFF - Mic bias is powered down
- 1 # ADC3XXX_MICBIAS_2_0V - Mic bias is set to 2.0V
- 2 # ADC3XXX_MICBIAS_2_5V - Mic bias is set to 2.5V
- 3 # ADC3XXX_MICBIAS_AVDD - Mic bias is same as AVDD supply
default: 0
description: |
Mic bias voltage output on MICBIAS2 pin
required:
- compatible
- reg
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/sound/tlv320adc3xxx.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
tlv320adc3101: audio-codec@18 {
compatible = "ti,tlv320adc3101";
reg = <0x18>;
reset-gpios = <&gpio_pc 3 GPIO_ACTIVE_LOW>;
clocks = <&audio_mclk>;
gpio-controller;
#gpio-cells = <2>;
ti,dmdin-gpio1 = <ADC3XXX_GPIO_GPO>;
ti,micbias1-vg = <ADC3XXX_MICBIAS_AVDD>;
};
};
audio_mclk: clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
...

116
Documentation/devicetree/bindings/sound/wlf,wm8903.yaml Normal file
View File

@ -0,0 +1,116 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/sound/wlf,wm8903.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: WM8903 audio codec
description: |
This device supports I2C only.
Pins on the device (for linking into audio routes):
* IN1L
* IN1R
* IN2L
* IN2R
* IN3L
* IN3R
* DMICDAT
* HPOUTL
* HPOUTR
* LINEOUTL
* LINEOUTR
* LOP
* LON
* ROP
* RON
* MICBIAS
maintainers:
- patches@opensource.cirrus.com
properties:
compatible:
const: wlf,wm8903
reg:
maxItems: 1
gpio-controller: true
'#gpio-cells':
const: 2
interrupts:
maxItems: 1
micdet-cfg:
$ref: /schemas/types.yaml#/definitions/uint32
default: 0
description: Default register value for R6 (Mic Bias).
micdet-delay:
$ref: /schemas/types.yaml#/definitions/uint32
default: 100
description: The debounce delay for microphone detection in mS.
gpio-cfg:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: |
minItems: 5
maxItems: 5
A list of GPIO configuration register values.
If absent, no configuration of these registers is performed.
If any entry has the value 0xffffffff, that GPIO's
configuration will not be modified.
AVDD-supply:
description: Analog power supply regulator on the AVDD pin.
CPVDD-supply:
description: Charge pump supply regulator on the CPVDD pin.
DBVDD-supply:
description: Digital buffer supply regulator for the DBVDD pin.
DCVDD-supply:
description: Digital core supply regulator for the DCVDD pin.
required:
- compatible
- reg
- gpio-controller
- '#gpio-cells'
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
wm8903: codec@1a {
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupts = <347>;
AVDD-supply = <&fooreg_a>;
CPVDD-supply = <&fooreg_b>;
DBVDD-supply = <&fooreg_c>;
DCVDD-supply = <&fooreg_d>;
gpio-controller;
#gpio-cells = <2>;
micdet-cfg = <0>;
micdet-delay = <100>;
gpio-cfg = <
0x0600 /* DMIC_LR, output */
0x0680 /* DMIC_DAT, input */
0x0000 /* GPIO, output, low */
0x0200 /* Interrupt, output */
0x01a0 /* BCLK, input, active high */
>;
};
};

82
Documentation/devicetree/bindings/sound/wm8903.txt
View File

@ -1,82 +0,0 @@
WM8903 audio CODEC
This device supports I2C only.
Required properties:
- compatible : "wlf,wm8903"
- reg : the I2C address of the device.
- gpio-controller : Indicates this device is a GPIO controller.
- #gpio-cells : Should be two. The first cell is the pin number and the
second cell is used to specify optional parameters (currently unused).
Optional properties:
- interrupts : The interrupt line the codec is connected to.
- micdet-cfg : Default register value for R6 (Mic Bias). If absent, the
default is 0.
- micdet-delay : The debounce delay for microphone detection in mS. If
absent, the default is 100.
- gpio-cfg : A list of GPIO configuration register values. The list must
be 5 entries long. If absent, no configuration of these registers is
performed. If any entry has the value 0xffffffff, that GPIO's
configuration will not be modified.
- AVDD-supply : Analog power supply regulator on the AVDD pin.
- CPVDD-supply : Charge pump supply regulator on the CPVDD pin.
- DBVDD-supply : Digital buffer supply regulator for the DBVDD pin.
- DCVDD-supply : Digital core supply regulator for the DCVDD pin.
Pins on the device (for linking into audio routes):
* IN1L
* IN1R
* IN2L
* IN2R
* IN3L
* IN3R
* DMICDAT
* HPOUTL
* HPOUTR
* LINEOUTL
* LINEOUTR
* LOP
* LON
* ROP
* RON
* MICBIAS
Example:
wm8903: codec@1a {
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupts = < 347 >;
AVDD-supply = <&fooreg_a>;
CPVDD-supply = <&fooreg_b>;
DBVDD-supply = <&fooreg_c>;
DCVDC-supply = <&fooreg_d>;
gpio-controller;
#gpio-cells = <2>;
micdet-cfg = <0>;
micdet-delay = <100>;
gpio-cfg = <
0x0600 /* DMIC_LR, output */
0x0680 /* DMIC_DAT, input */
0x0000 /* GPIO, output, low */
0x0200 /* Interrupt, output */
0x01a0 /* BCLK, input, active high */
>;
};

11
MAINTAINERS
View File

@ -4568,9 +4568,12 @@ F: drivers/media/cec/i2c/ch7322.c
CIRRUS LOGIC AUDIO CODEC DRIVERS
M: James Schulman <james.schulman@cirrus.com>
M: David Rhodes <david.rhodes@cirrus.com>
M: Lucas Tanure <tanureal@opensource.cirrus.com>
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
L: patches@opensource.cirrus.com
S: Maintained
F: Documentation/devicetree/bindings/sound/cirrus,cs*
F: sound/pci/hda/cs*
F: sound/soc/codecs/cs*
CIRRUS LOGIC DSP FIRMWARE DRIVER
@ -17988,6 +17991,7 @@ F: Documentation/sound/
F: include/sound/
F: include/uapi/sound/
F: sound/
F: tools/testing/selftests/alsa
SOUND - COMPRESSED AUDIO
M: Vinod Koul <vkoul@kernel.org>
@ -18007,6 +18011,13 @@ F: include/sound/dmaengine_pcm.h
F: sound/core/pcm_dmaengine.c
F: sound/soc/soc-generic-dmaengine-pcm.c
SOUND - ALSA SELFTESTS
M: Mark Brown <broonie@kernel.org>
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
L: linux-kselftest@vger.kernel.org
S: Supported
F: tools/testing/selftests/alsa
SOUND - SOC LAYER / DYNAMIC AUDIO POWER MANAGEMENT (ASoC)
M: Liam Girdwood <lgirdwood@gmail.com>
M: Mark Brown <broonie@kernel.org>

5
arch/arm64/boot/dts/nvidia/tegra194.dtsi
View File

@ -995,9 +995,8 @@
<&bpmp TEGRA194_CLK_HDA2CODEC_2X>;
clock-names = "hda", "hda2hdmi", "hda2codec_2x";
resets = <&bpmp TEGRA194_RESET_HDA>,
<&bpmp TEGRA194_RESET_HDA2HDMICODEC>,
<&bpmp TEGRA194_RESET_HDA2CODEC_2X>;
reset-names = "hda", "hda2hdmi", "hda2codec_2x";
<&bpmp TEGRA194_RESET_HDA2HDMICODEC>;
reset-names = "hda", "hda2hdmi";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;

6
drivers/dma/mmp_pdma.c
View File

@ -727,12 +727,6 @@ static int mmp_pdma_config_write(struct dma_chan *dchan,
chan->dir = direction;
chan->dev_addr = addr;
/* FIXME: drivers should be ported over to use the filter
* function. Once that's done, the following two lines can
* be removed.
*/
if (cfg->slave_id)
chan->drcmr = cfg->slave_id;
return 0;
}

7
drivers/dma/pxa_dma.c
View File

@ -909,13 +909,6 @@ static void pxad_get_config(struct pxad_chan *chan,
*dcmd |= PXA_DCMD_BURST16;
else if (maxburst == 32)
*dcmd |= PXA_DCMD_BURST32;
/* FIXME: drivers should be ported over to use the filter
* function. Once that's done, the following two lines can
* be removed.
*/
if (chan->cfg.slave_id)
chan->drcmr = chan->cfg.slave_id;
}
static struct dma_async_tx_descriptor *

56
drivers/dma/qcom/qcom_adm.c
View File

@ -8,6 +8,7 @@
#include <linux/device.h>
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/dma/qcom_adm.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
@ -140,6 +141,8 @@ struct adm_chan {
struct adm_async_desc *curr_txd;
struct dma_slave_config slave;
u32 crci;
u32 mux;
struct list_head node;
int error;
@ -379,8 +382,8 @@ static struct dma_async_tx_descriptor *adm_prep_slave_sg(struct dma_chan *chan,
return ERR_PTR(-EINVAL);
}
crci = achan->slave.slave_id & 0xf;
if (!crci || achan->slave.slave_id > 0x1f) {
crci = achan->crci & 0xf;
if (!crci || achan->crci > 0x1f) {
dev_err(adev->dev, "invalid crci value\n");
return ERR_PTR(-EINVAL);
}
@ -403,9 +406,7 @@ static struct dma_async_tx_descriptor *adm_prep_slave_sg(struct dma_chan *chan,
if (!async_desc)
return ERR_PTR(-ENOMEM);
if (crci)
async_desc->mux = achan->slave.slave_id & ADM_CRCI_MUX_SEL ?
ADM_CRCI_CTL_MUX_SEL : 0;
async_desc->mux = achan->mux ? ADM_CRCI_CTL_MUX_SEL : 0;
async_desc->crci = crci;
async_desc->blk_size = blk_size;
async_desc->dma_len = single_count * sizeof(struct adm_desc_hw_single) +
@ -488,10 +489,13 @@ static int adm_terminate_all(struct dma_chan *chan)
static int adm_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg)
{
struct adm_chan *achan = to_adm_chan(chan);
struct qcom_adm_peripheral_config *config = cfg->peripheral_config;
unsigned long flag;
spin_lock_irqsave(&achan->vc.lock, flag);
memcpy(&achan->slave, cfg, sizeof(struct dma_slave_config));
if (cfg->peripheral_size == sizeof(config))
achan->crci = config->crci;
spin_unlock_irqrestore(&achan->vc.lock, flag);
return 0;
@ -694,6 +698,45 @@ static void adm_channel_init(struct adm_device *adev, struct adm_chan *achan,
achan->vc.desc_free = adm_dma_free_desc;
}
/**
* adm_dma_xlate
* @dma_spec: pointer to DMA specifier as found in the device tree
* @ofdma: pointer to DMA controller data
*
* This can use either 1-cell or 2-cell formats, the first cell
* identifies the slave device, while the optional second cell
* contains the crci value.
*
* Returns pointer to appropriate dma channel on success or NULL on error.
*/
static struct dma_chan *adm_dma_xlate(struct of_phandle_args *dma_spec,
struct of_dma *ofdma)
{
struct dma_device *dev = ofdma->of_dma_data;
struct dma_chan *chan, *candidate = NULL;
struct adm_chan *achan;
if (!dev || dma_spec->args_count > 2)
return NULL;
list_for_each_entry(chan, &dev->channels, device_node)
if (chan->chan_id == dma_spec->args[0]) {
candidate = chan;
break;
}
if (!candidate)
return NULL;
achan = to_adm_chan(candidate);
if (dma_spec->args_count == 2)
achan->crci = dma_spec->args[1];
else
achan->crci = 0;
return dma_get_slave_channel(candidate);
}
static int adm_dma_probe(struct platform_device *pdev)
{
struct adm_device *adev;
@ -838,8 +881,7 @@ static int adm_dma_probe(struct platform_device *pdev)
goto err_disable_clks;
}
ret = of_dma_controller_register(pdev->dev.of_node,
of_dma_xlate_by_chan_id,
ret = of_dma_controller_register(pdev->dev.of_node, adm_dma_xlate,
&adev->common);
if (ret)
goto err_unregister_dma;

8
drivers/dma/sh/shdma-base.c
View File

@ -786,14 +786,6 @@ static int shdma_config(struct dma_chan *chan,
if (!config)
return -EINVAL;
/*
* overriding the slave_id through dma_slave_config is deprecated,
* but possibly some out-of-tree drivers still do it.
*/
if (WARN_ON_ONCE(config->slave_id &&
config->slave_id != schan->real_slave_id))
schan->real_slave_id = config->slave_id;
/*
* We could lock this, but you shouldn't be configuring the
* channel, while using it...

3
drivers/dma/sprd-dma.c
View File

@ -795,9 +795,6 @@ static int sprd_dma_fill_desc(struct dma_chan *chan,
return dst_datawidth;
}
if (slave_cfg->slave_id)
schan->dev_id = slave_cfg->slave_id;
hw->cfg = SPRD_DMA_DONOT_WAIT_BDONE << SPRD_DMA_WAIT_BDONE_OFFSET;
/*

6
drivers/dma/tegra20-apb-dma.c
View File

@ -343,12 +343,6 @@ static int tegra_dma_slave_config(struct dma_chan *dc,
}
memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
if (tdc->slave_id == TEGRA_APBDMA_SLAVE_ID_INVALID &&
sconfig->device_fc) {
if (sconfig->slave_id > TEGRA_APBDMA_CSR_REQ_SEL_MASK)
return -EINVAL;
tdc->slave_id = sconfig->slave_id;
}
tdc->config_init = true;
return 0;

17
drivers/dma/xilinx/xilinx_dpdma.c
View File

@ -12,6 +12,7 @@
#include <linux/clk.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/dma/xilinx_dpdma.h>
#include <linux/dmaengine.h>
#include <linux/dmapool.h>
#include <linux/interrupt.h>
@ -1273,6 +1274,7 @@ static int xilinx_dpdma_config(struct dma_chan *dchan,
struct dma_slave_config *config)
{
struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
struct xilinx_dpdma_peripheral_config *pconfig;
unsigned long flags;
/*
@ -1282,15 +1284,18 @@ static int xilinx_dpdma_config(struct dma_chan *dchan,
* fixed both on the DPDMA side and on the DP controller side.
*/
spin_lock_irqsave(&chan->lock, flags);
/*
* Abuse the slave_id to indicate that the channel is part of a video
* group.
* Use the peripheral_config to indicate that the channel is part
* of a video group. This requires matching use of the custom
* structure in each driver.
*/
if (chan->id <= ZYNQMP_DPDMA_VIDEO2)
chan->video_group = config->slave_id != 0;
pconfig = config->peripheral_config;
if (WARN_ON(pconfig && config->peripheral_size != sizeof(*pconfig)))
return -EINVAL;
spin_lock_irqsave(&chan->lock, flags);
if (chan->id <= ZYNQMP_DPDMA_VIDEO2 && pconfig)
chan->video_group = pconfig->video_group;
spin_unlock_irqrestore(&chan->lock, flags);
return 0;

156
drivers/firmware/cirrus/cs_dsp.c
View File

@ -12,16 +12,10 @@
#include <linux/ctype.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/firmware.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
#include <linux/workqueue.h>
#include <linux/firmware/cirrus/cs_dsp.h>
#include <linux/firmware/cirrus/wmfw.h>
@ -622,7 +616,8 @@ static void cs_dsp_halo_show_fw_status(struct cs_dsp *dsp)
offs[0], offs[1], offs[2], offs[3]);
}
static int cs_dsp_coeff_base_reg(struct cs_dsp_coeff_ctl *ctl, unsigned int *reg)
static int cs_dsp_coeff_base_reg(struct cs_dsp_coeff_ctl *ctl, unsigned int *reg,
unsigned int off)
{
const struct cs_dsp_alg_region *alg_region = &ctl->alg_region;
struct cs_dsp *dsp = ctl->dsp;
@ -635,7 +630,7 @@ static int cs_dsp_coeff_base_reg(struct cs_dsp_coeff_ctl *ctl, unsigned int *reg
return -EINVAL;
}
*reg = dsp->ops->region_to_reg(mem, ctl->alg_region.base + ctl->offset);
*reg = dsp->ops->region_to_reg(mem, ctl->alg_region.base + ctl->offset + off);
return 0;
}
@ -659,10 +654,12 @@ int cs_dsp_coeff_write_acked_control(struct cs_dsp_coeff_ctl *ctl, unsigned int
unsigned int reg;
int i, ret;
lockdep_assert_held(&dsp->pwr_lock);
if (!dsp->running)
return -EPERM;
ret = cs_dsp_coeff_base_reg(ctl, &reg);
ret = cs_dsp_coeff_base_reg(ctl, &reg, 0);
if (ret)
return ret;
@ -716,14 +713,14 @@ int cs_dsp_coeff_write_acked_control(struct cs_dsp_coeff_ctl *ctl, unsigned int
EXPORT_SYMBOL_GPL(cs_dsp_coeff_write_acked_control);
static int cs_dsp_coeff_write_ctrl_raw(struct cs_dsp_coeff_ctl *ctl,
const void *buf, size_t len)
unsigned int off, const void *buf, size_t len)
{
struct cs_dsp *dsp = ctl->dsp;
void *scratch;
int ret;
unsigned int reg;
ret = cs_dsp_coeff_base_reg(ctl, &reg);
ret = cs_dsp_coeff_base_reg(ctl, &reg, off);
if (ret)
return ret;
@ -749,38 +746,49 @@ static int cs_dsp_coeff_write_ctrl_raw(struct cs_dsp_coeff_ctl *ctl,
/**
* cs_dsp_coeff_write_ctrl() - Writes the given buffer to the given coefficient control
* @ctl: pointer to coefficient control
* @off: word offset at which data should be written
* @buf: the buffer to write to the given control
* @len: the length of the buffer
* @len: the length of the buffer in bytes
*
* Must be called with pwr_lock held.
*
* Return: Zero for success, a negative number on error.
*/
int cs_dsp_coeff_write_ctrl(struct cs_dsp_coeff_ctl *ctl, const void *buf, size_t len)
int cs_dsp_coeff_write_ctrl(struct cs_dsp_coeff_ctl *ctl,
unsigned int off, const void *buf, size_t len)
{
int ret = 0;
if (!ctl)
return -ENOENT;
lockdep_assert_held(&ctl->dsp->pwr_lock);
if (len + off * sizeof(u32) > ctl->len)
return -EINVAL;
if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
ret = -EPERM;
else if (buf != ctl->cache)
memcpy(ctl->cache, buf, len);
memcpy(ctl->cache + off * sizeof(u32), buf, len);
ctl->set = 1;
if (ctl->enabled && ctl->dsp->running)
ret = cs_dsp_coeff_write_ctrl_raw(ctl, buf, len);
ret = cs_dsp_coeff_write_ctrl_raw(ctl, off, buf, len);
return ret;
}
EXPORT_SYMBOL_GPL(cs_dsp_coeff_write_ctrl);
static int cs_dsp_coeff_read_ctrl_raw(struct cs_dsp_coeff_ctl *ctl, void *buf, size_t len)
static int cs_dsp_coeff_read_ctrl_raw(struct cs_dsp_coeff_ctl *ctl,
unsigned int off, void *buf, size_t len)
{
struct cs_dsp *dsp = ctl->dsp;
void *scratch;
int ret;
unsigned int reg;
ret = cs_dsp_coeff_base_reg(ctl, &reg);
ret = cs_dsp_coeff_base_reg(ctl, &reg, off);
if (ret)
return ret;
@ -806,28 +814,38 @@ static int cs_dsp_coeff_read_ctrl_raw(struct cs_dsp_coeff_ctl *ctl, void *buf, s
/**
* cs_dsp_coeff_read_ctrl() - Reads the given coefficient control into the given buffer
* @ctl: pointer to coefficient control
* @off: word offset at which data should be read
* @buf: the buffer to store to the given control
* @len: the length of the buffer
* @len: the length of the buffer in bytes
*
* Must be called with pwr_lock held.
*
* Return: Zero for success, a negative number on error.
*/
int cs_dsp_coeff_read_ctrl(struct cs_dsp_coeff_ctl *ctl, void *buf, size_t len)
int cs_dsp_coeff_read_ctrl(struct cs_dsp_coeff_ctl *ctl,
unsigned int off, void *buf, size_t len)
{
int ret = 0;
if (!ctl)
return -ENOENT;
lockdep_assert_held(&ctl->dsp->pwr_lock);
if (len + off * sizeof(u32) > ctl->len)
return -EINVAL;
if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
if (ctl->enabled && ctl->dsp->running)
return cs_dsp_coeff_read_ctrl_raw(ctl, buf, len);
return cs_dsp_coeff_read_ctrl_raw(ctl, off, buf, len);
else
return -EPERM;
} else {
if (!ctl->flags && ctl->enabled && ctl->dsp->running)
ret = cs_dsp_coeff_read_ctrl_raw(ctl, ctl->cache, ctl->len);
ret = cs_dsp_coeff_read_ctrl_raw(ctl, 0, ctl->cache, ctl->len);
if (buf != ctl->cache)
memcpy(buf, ctl->cache, len);
memcpy(buf, ctl->cache + off * sizeof(u32), len);
}
return ret;
@ -851,7 +869,7 @@ static int cs_dsp_coeff_init_control_caches(struct cs_dsp *dsp)
* created so we don't need to do anything.
*/
if (!ctl->flags || (ctl->flags & WMFW_CTL_FLAG_READABLE)) {
ret = cs_dsp_coeff_read_ctrl_raw(ctl, ctl->cache, ctl->len);
ret = cs_dsp_coeff_read_ctrl_raw(ctl, 0, ctl->cache, ctl->len);
if (ret < 0)
return ret;
}
@ -869,7 +887,7 @@ static int cs_dsp_coeff_sync_controls(struct cs_dsp *dsp)
if (!ctl->enabled)
continue;
if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) {
ret = cs_dsp_coeff_write_ctrl_raw(ctl, ctl->cache,
ret = cs_dsp_coeff_write_ctrl_raw(ctl, 0, ctl->cache,
ctl->len);
if (ret < 0)
return ret;
@ -1159,6 +1177,7 @@ static int cs_dsp_parse_coeff(struct cs_dsp *dsp,
return -EINVAL;
break;
case WMFW_CTL_TYPE_HOSTEVENT:
case WMFW_CTL_TYPE_FWEVENT:
ret = cs_dsp_check_coeff_flags(dsp, &coeff_blk,
WMFW_CTL_FLAG_SYS |
WMFW_CTL_FLAG_VOLATILE |
@ -1459,6 +1478,8 @@ struct cs_dsp_coeff_ctl *cs_dsp_get_ctl(struct cs_dsp *dsp, const char *name, in
{
struct cs_dsp_coeff_ctl *pos, *rslt = NULL;
lockdep_assert_held(&dsp->pwr_lock);
list_for_each_entry(pos, &dsp->ctl_list, list) {
if (!pos->subname)
continue;
@ -1554,6 +1575,8 @@ struct cs_dsp_alg_region *cs_dsp_find_alg_region(struct cs_dsp *dsp,
{
struct cs_dsp_alg_region *alg_region;
lockdep_assert_held(&dsp->pwr_lock);
list_for_each_entry(alg_region, &dsp->alg_regions, list) {
if (id == alg_region->alg && type == alg_region->type)
return alg_region;
@ -1565,7 +1588,7 @@ EXPORT_SYMBOL_GPL(cs_dsp_find_alg_region);
static struct cs_dsp_alg_region *cs_dsp_create_region(struct cs_dsp *dsp,
int type, __be32 id,
__be32 base)
__be32 ver, __be32 base)
{
struct cs_dsp_alg_region *alg_region;
@ -1575,6 +1598,7 @@ static struct cs_dsp_alg_region *cs_dsp_create_region(struct cs_dsp *dsp,
alg_region->type = type;
alg_region->alg = be32_to_cpu(id);
alg_region->ver = be32_to_cpu(ver);
alg_region->base = be32_to_cpu(base);
list_add_tail(&alg_region->list, &dsp->alg_regions);
@ -1624,14 +1648,14 @@ static void cs_dsp_parse_wmfw_v3_id_header(struct cs_dsp *dsp,
nalgs);
}
static int cs_dsp_create_regions(struct cs_dsp *dsp, __be32 id, int nregions,
const int *type, __be32 *base)
static int cs_dsp_create_regions(struct cs_dsp *dsp, __be32 id, __be32 ver,
int nregions, const int *type, __be32 *base)
{
struct cs_dsp_alg_region *alg_region;
int i;
for (i = 0; i < nregions; i++) {
alg_region = cs_dsp_create_region(dsp, type[i], id, base[i]);
alg_region = cs_dsp_create_region(dsp, type[i], id, ver, base[i]);
if (IS_ERR(alg_region))
return PTR_ERR(alg_region);
}
@ -1666,12 +1690,14 @@ static int cs_dsp_adsp1_setup_algs(struct cs_dsp *dsp)
cs_dsp_parse_wmfw_id_header(dsp, &adsp1_id.fw, n_algs);
alg_region = cs_dsp_create_region(dsp, WMFW_ADSP1_ZM,
adsp1_id.fw.id, adsp1_id.zm);
adsp1_id.fw.id, adsp1_id.fw.ver,
adsp1_id.zm);
if (IS_ERR(alg_region))
return PTR_ERR(alg_region);
alg_region = cs_dsp_create_region(dsp, WMFW_ADSP1_DM,
adsp1_id.fw.id, adsp1_id.dm);
adsp1_id.fw.id, adsp1_id.fw.ver,
adsp1_id.dm);
if (IS_ERR(alg_region))
return PTR_ERR(alg_region);
@ -1694,6 +1720,7 @@ static int cs_dsp_adsp1_setup_algs(struct cs_dsp *dsp)
alg_region = cs_dsp_create_region(dsp, WMFW_ADSP1_DM,
adsp1_alg[i].alg.id,
adsp1_alg[i].alg.ver,
adsp1_alg[i].dm);
if (IS_ERR(alg_region)) {
ret = PTR_ERR(alg_region);
@ -1715,6 +1742,7 @@ static int cs_dsp_adsp1_setup_algs(struct cs_dsp *dsp)
alg_region = cs_dsp_create_region(dsp, WMFW_ADSP1_ZM,
adsp1_alg[i].alg.id,
adsp1_alg[i].alg.ver,
adsp1_alg[i].zm);
if (IS_ERR(alg_region)) {
ret = PTR_ERR(alg_region);
@ -1767,17 +1795,20 @@ static int cs_dsp_adsp2_setup_algs(struct cs_dsp *dsp)
cs_dsp_parse_wmfw_id_header(dsp, &adsp2_id.fw, n_algs);
alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_XM,
adsp2_id.fw.id, adsp2_id.xm);
adsp2_id.fw.id, adsp2_id.fw.ver,
adsp2_id.xm);
if (IS_ERR(alg_region))
return PTR_ERR(alg_region);
alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_YM,
adsp2_id.fw.id, adsp2_id.ym);
adsp2_id.fw.id, adsp2_id.fw.ver,
adsp2_id.ym);
if (IS_ERR(alg_region))
return PTR_ERR(alg_region);
alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_ZM,
adsp2_id.fw.id, adsp2_id.zm);
adsp2_id.fw.id, adsp2_id.fw.ver,
adsp2_id.zm);
if (IS_ERR(alg_region))
return PTR_ERR(alg_region);
@ -1802,6 +1833,7 @@ static int cs_dsp_adsp2_setup_algs(struct cs_dsp *dsp)
alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_XM,
adsp2_alg[i].alg.id,
adsp2_alg[i].alg.ver,
adsp2_alg[i].xm);
if (IS_ERR(alg_region)) {
ret = PTR_ERR(alg_region);
@ -1823,6 +1855,7 @@ static int cs_dsp_adsp2_setup_algs(struct cs_dsp *dsp)
alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_YM,
adsp2_alg[i].alg.id,
adsp2_alg[i].alg.ver,
adsp2_alg[i].ym);
if (IS_ERR(alg_region)) {
ret = PTR_ERR(alg_region);
@ -1844,6 +1877,7 @@ static int cs_dsp_adsp2_setup_algs(struct cs_dsp *dsp)
alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_ZM,
adsp2_alg[i].alg.id,
adsp2_alg[i].alg.ver,
adsp2_alg[i].zm);
if (IS_ERR(alg_region)) {
ret = PTR_ERR(alg_region);
@ -1869,7 +1903,7 @@ out:
return ret;
}
static int cs_dsp_halo_create_regions(struct cs_dsp *dsp, __be32 id,
static int cs_dsp_halo_create_regions(struct cs_dsp *dsp, __be32 id, __be32 ver,
__be32 xm_base, __be32 ym_base)
{
static const int types[] = {
@ -1878,7 +1912,7 @@ static int cs_dsp_halo_create_regions(struct cs_dsp *dsp, __be32 id,
};
__be32 bases[] = { xm_base, xm_base, ym_base, ym_base };
return cs_dsp_create_regions(dsp, id, ARRAY_SIZE(types), types, bases);
return cs_dsp_create_regions(dsp, id, ver, ARRAY_SIZE(types), types, bases);
}
static int cs_dsp_halo_setup_algs(struct cs_dsp *dsp)
@ -1906,7 +1940,7 @@ static int cs_dsp_halo_setup_algs(struct cs_dsp *dsp)
cs_dsp_parse_wmfw_v3_id_header(dsp, &halo_id.fw, n_algs);
ret = cs_dsp_halo_create_regions(dsp, halo_id.fw.id,
ret = cs_dsp_halo_create_regions(dsp, halo_id.fw.id, halo_id.fw.ver,
halo_id.xm_base, halo_id.ym_base);
if (ret)
return ret;
@ -1930,6 +1964,7 @@ static int cs_dsp_halo_setup_algs(struct cs_dsp *dsp)
be32_to_cpu(halo_alg[i].ym_base));
ret = cs_dsp_halo_create_regions(dsp, halo_alg[i].alg.id,
halo_alg[i].alg.ver,
halo_alg[i].xm_base,
halo_alg[i].ym_base);
if (ret)
@ -1951,7 +1986,8 @@ static int cs_dsp_load_coeff(struct cs_dsp *dsp, const struct firmware *firmware
const struct cs_dsp_region *mem;
struct cs_dsp_alg_region *alg_region;
const char *region_name;
int ret, pos, blocks, type, offset, reg;
int ret, pos, blocks, type, offset, reg, version;
char *text = NULL;
struct cs_dsp_buf *buf;
if (!firmware)
@ -1973,6 +2009,7 @@ static int cs_dsp_load_coeff(struct cs_dsp *dsp, const struct firmware *firmware
switch (be32_to_cpu(hdr->rev) & 0xff) {
case 1:
case 2:
break;
default:
cs_dsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
@ -1995,6 +2032,7 @@ static int cs_dsp_load_coeff(struct cs_dsp *dsp, const struct firmware *firmware
type = le16_to_cpu(blk->type);
offset = le16_to_cpu(blk->offset);
version = le32_to_cpu(blk->ver) >> 8;
cs_dsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
file, blocks, le32_to_cpu(blk->id),
@ -2008,6 +2046,8 @@ static int cs_dsp_load_coeff(struct cs_dsp *dsp, const struct firmware *firmware
region_name = "Unknown";
switch (type) {
case (WMFW_NAME_TEXT << 8):
text = kzalloc(le32_to_cpu(blk->len) + 1, GFP_KERNEL);
break;
case (WMFW_INFO_TEXT << 8):
case (WMFW_METADATA << 8):
break;
@ -2052,6 +2092,16 @@ static int cs_dsp_load_coeff(struct cs_dsp *dsp, const struct firmware *firmware
alg_region = cs_dsp_find_alg_region(dsp, type,
le32_to_cpu(blk->id));
if (alg_region) {
if (version != alg_region->ver)
cs_dsp_warn(dsp,
"Algorithm coefficient version %d.%d.%d but expected %d.%d.%d\n",
(version >> 16) & 0xFF,
(version >> 8) & 0xFF,
version & 0xFF,
(alg_region->ver >> 16) & 0xFF,
(alg_region->ver >> 8) & 0xFF,
alg_region->ver & 0xFF);
reg = alg_region->base;
reg = dsp->ops->region_to_reg(mem, reg);
reg += offset;
@ -2067,6 +2117,13 @@ static int cs_dsp_load_coeff(struct cs_dsp *dsp, const struct firmware *firmware
break;
}
if (text) {
memcpy(text, blk->data, le32_to_cpu(blk->len));
cs_dsp_info(dsp, "%s: %s\n", dsp->fw_name, text);
kfree(text);
text = NULL;
}
if (reg) {
if (le32_to_cpu(blk->len) >
firmware->size - pos - sizeof(*blk)) {
@ -2117,6 +2174,7 @@ static int cs_dsp_load_coeff(struct cs_dsp *dsp, const struct firmware *firmware
out_fw:
regmap_async_complete(regmap);
cs_dsp_buf_free(&buf_list);
kfree(text);
return ret;
}
@ -2600,6 +2658,12 @@ int cs_dsp_run(struct cs_dsp *dsp)
goto err;
}
if (dsp->client_ops->pre_run) {
ret = dsp->client_ops->pre_run(dsp);
if (ret)
goto err;
}
/* Sync set controls */
ret = cs_dsp_coeff_sync_controls(dsp);
if (ret != 0)
@ -2680,10 +2744,16 @@ EXPORT_SYMBOL_GPL(cs_dsp_stop);
static int cs_dsp_halo_start_core(struct cs_dsp *dsp)
{
return regmap_update_bits(dsp->regmap,
dsp->base + HALO_CCM_CORE_CONTROL,
HALO_CORE_RESET | HALO_CORE_EN,
HALO_CORE_RESET | HALO_CORE_EN);
int ret;
ret = regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL,
HALO_CORE_RESET | HALO_CORE_EN,
HALO_CORE_RESET | HALO_CORE_EN);
if (ret)
return ret;
return regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL,
HALO_CORE_RESET, 0);
}
static void cs_dsp_halo_stop_core(struct cs_dsp *dsp)
@ -2789,6 +2859,8 @@ int cs_dsp_read_raw_data_block(struct cs_dsp *dsp, int mem_type, unsigned int me
unsigned int reg;
int ret;
lockdep_assert_held(&dsp->pwr_lock);
if (!mem)
return -EINVAL;
@ -2842,6 +2914,8 @@ int cs_dsp_write_data_word(struct cs_dsp *dsp, int mem_type, unsigned int mem_ad
__be32 val = cpu_to_be32(data & 0x00ffffffu);
unsigned int reg;
lockdep_assert_held(&dsp->pwr_lock);
if (!mem)
return -EINVAL;

9
drivers/gpu/drm/xlnx/zynqmp_disp.c
View File

@ -24,6 +24,7 @@
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dma/xilinx_dpdma.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/module.h>
@ -1058,14 +1059,18 @@ static void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer,
zynqmp_disp_avbuf_set_format(layer->disp, layer, layer->disp_fmt);
/*
* Set slave_id for each DMA channel to indicate they're part of a
* Set pconfig for each DMA channel to indicate they're part of a
* video group.
*/
for (i = 0; i < info->num_planes; i++) {
struct zynqmp_disp_layer_dma *dma = &layer->dmas[i];
struct xilinx_dpdma_peripheral_config pconfig = {
.video_group = true,
};
struct dma_slave_config config = {
.direction = DMA_MEM_TO_DEV,
.slave_id = 1,
.peripheral_config = &pconfig,
.peripheral_size = sizeof(pconfig),
};
dmaengine_slave_config(dma->chan, &config);

2
drivers/mmc/host/bcm2835.c
View File

@ -1293,14 +1293,12 @@ static int bcm2835_add_host(struct bcm2835_host *host)
host->dma_cfg_tx.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
host->dma_cfg_tx.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
host->dma_cfg_tx.slave_id = 13; /* DREQ channel */
host->dma_cfg_tx.direction = DMA_MEM_TO_DEV;
host->dma_cfg_tx.src_addr = 0;
host->dma_cfg_tx.dst_addr = host->phys_addr + SDDATA;
host->dma_cfg_rx.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
host->dma_cfg_rx.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
host->dma_cfg_rx.slave_id = 13; /* DREQ channel */
host->dma_cfg_rx.direction = DMA_DEV_TO_MEM;
host->dma_cfg_rx.src_addr = host->phys_addr + SDDATA;
host->dma_cfg_rx.dst_addr = 0;

14
drivers/mtd/nand/raw/qcom_nandc.c
View File

@ -6,6 +6,7 @@
#include <linux/clk.h>
#include <linux/slab.h>
#include <linux/bitops.h>
#include <linux/dma/qcom_adm.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/module.h>
@ -952,6 +953,7 @@ static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
struct dma_async_tx_descriptor *dma_desc;
struct scatterlist *sgl;
struct dma_slave_config slave_conf;
struct qcom_adm_peripheral_config periph_conf = {};
enum dma_transfer_direction dir_eng;
int ret;
@ -983,11 +985,19 @@ static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
if (read) {
slave_conf.src_maxburst = 16;
slave_conf.src_addr = nandc->base_dma + reg_off;
slave_conf.slave_id = nandc->data_crci;
if (nandc->data_crci) {
periph_conf.crci = nandc->data_crci;
slave_conf.peripheral_config = &periph_conf;
slave_conf.peripheral_size = sizeof(periph_conf);
}
} else {
slave_conf.dst_maxburst = 16;
slave_conf.dst_addr = nandc->base_dma + reg_off;
slave_conf.slave_id = nandc->cmd_crci;
if (nandc->cmd_crci) {
periph_conf.crci = nandc->cmd_crci;
slave_conf.peripheral_config = &periph_conf;
slave_conf.peripheral_size = sizeof(periph_conf);
}
}
ret = dmaengine_slave_config(nandc->chan, &slave_conf);

15
drivers/soc/mediatek/mtk-scpsys.c
View File

@ -411,12 +411,17 @@ out:
return ret;
}
static void init_clks(struct platform_device *pdev, struct clk **clk)
static int init_clks(struct platform_device *pdev, struct clk **clk)
{
int i;
for (i = CLK_NONE + 1; i < CLK_MAX; i++)
for (i = CLK_NONE + 1; i < CLK_MAX; i++) {
clk[i] = devm_clk_get(&pdev->dev, clk_names[i]);
if (IS_ERR(clk[i]))
return PTR_ERR(clk[i]);
}
return 0;
}
static struct scp *init_scp(struct platform_device *pdev,
@ -426,7 +431,7 @@ static struct scp *init_scp(struct platform_device *pdev,
{
struct genpd_onecell_data *pd_data;
struct resource *res;
int i, j;
int i, j, ret;
struct scp *scp;
struct clk *clk[CLK_MAX];
@ -481,7 +486,9 @@ static struct scp *init_scp(struct platform_device *pdev,
pd_data->num_domains = num;
init_clks(pdev, clk);
ret = init_clks(pdev, clk);
if (ret)
return ERR_PTR(ret);
for (i = 0; i < num; i++) {
struct scp_domain *scpd = &scp->domains[i];

36
drivers/soundwire/cadence_master.c
View File

@ -1178,9 +1178,6 @@ int sdw_cdns_pdi_init(struct sdw_cdns *cdns,
cdns->pcm.num_bd = config.pcm_bd;
cdns->pcm.num_in = config.pcm_in;
cdns->pcm.num_out = config.pcm_out;
cdns->pdm.num_bd = config.pdm_bd;
cdns->pdm.num_in = config.pdm_in;
cdns->pdm.num_out = config.pdm_out;
/* Allocate PDIs for PCMs */
stream = &cdns->pcm;
@ -1211,32 +1208,6 @@ int sdw_cdns_pdi_init(struct sdw_cdns *cdns,
stream->num_pdi = stream->num_bd + stream->num_in + stream->num_out;
cdns->num_ports = stream->num_pdi;
/* Allocate PDIs for PDMs */
stream = &cdns->pdm;
ret = cdns_allocate_pdi(cdns, &stream->bd,
stream->num_bd, offset);
if (ret)
return ret;
offset += stream->num_bd;
ret = cdns_allocate_pdi(cdns, &stream->in,
stream->num_in, offset);
if (ret)
return ret;
offset += stream->num_in;
ret = cdns_allocate_pdi(cdns, &stream->out,
stream->num_out, offset);
if (ret)
return ret;
/* Update total number of PDM PDIs */
stream->num_pdi = stream->num_bd + stream->num_in + stream->num_out;
cdns->num_ports += stream->num_pdi;
return 0;
}
EXPORT_SYMBOL(sdw_cdns_pdi_init);
@ -1681,7 +1652,7 @@ int sdw_cdns_probe(struct sdw_cdns *cdns)
EXPORT_SYMBOL(sdw_cdns_probe);
int cdns_set_sdw_stream(struct snd_soc_dai *dai,
void *stream, bool pcm, int direction)
void *stream, int direction)
{
struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
struct sdw_cdns_dma_data *dma;
@ -1705,10 +1676,7 @@ int cdns_set_sdw_stream(struct snd_soc_dai *dai,
if (!dma)
return -ENOMEM;
if (pcm)
dma->stream_type = SDW_STREAM_PCM;
else
dma->stream_type = SDW_STREAM_PDM;
dma->stream_type = SDW_STREAM_PCM;
dma->bus = &cdns->bus;
dma->link_id = cdns->instance;

14
drivers/soundwire/cadence_master.h
View File

@ -17,7 +17,7 @@
* @h_ch_num: high channel for PDI
* @ch_count: total channel count for PDI
* @dir: data direction
* @type: stream type, PDM or PCM
* @type: stream type, (only PCM supported)
*/
struct sdw_cdns_pdi {
int num;
@ -62,17 +62,11 @@ struct sdw_cdns_streams {
* @pcm_bd: number of bidirectional PCM streams supported
* @pcm_in: number of input PCM streams supported
* @pcm_out: number of output PCM streams supported
* @pdm_bd: number of bidirectional PDM streams supported
* @pdm_in: number of input PDM streams supported
* @pdm_out: number of output PDM streams supported
*/
struct sdw_cdns_stream_config {
unsigned int pcm_bd;
unsigned int pcm_in;
unsigned int pcm_out;
unsigned int pdm_bd;
unsigned int pdm_in;
unsigned int pdm_out;
};
/**
@ -86,6 +80,7 @@ struct sdw_cdns_stream_config {
* @link_id: Master link id
* @hw_params: hw_params to be applied in .prepare step
* @suspended: status set when suspended, to be used in .prepare
* @paused: status set in .trigger, to be used in suspend
*/
struct sdw_cdns_dma_data {
char *name;
@ -96,6 +91,7 @@ struct sdw_cdns_dma_data {
int link_id;
struct snd_pcm_hw_params *hw_params;
bool suspended;
bool paused;
};
/**
@ -109,7 +105,6 @@ struct sdw_cdns_dma_data {
* @ports: Data ports
* @num_ports: Total number of data ports
* @pcm: PCM streams
* @pdm: PDM streams
* @registers: Cadence registers
* @link_up: Link status
* @msg_count: Messages sent on bus
@ -127,7 +122,6 @@ struct sdw_cdns {
int num_ports;
struct sdw_cdns_streams pcm;
struct sdw_cdns_streams pdm;
int pdi_loopback_source;
int pdi_loopback_target;
@ -186,7 +180,7 @@ cdns_xfer_msg_defer(struct sdw_bus *bus,
int cdns_bus_conf(struct sdw_bus *bus, struct sdw_bus_params *params);
int cdns_set_sdw_stream(struct snd_soc_dai *dai,
void *stream, bool pcm, int direction);
void *stream, int direction);
void sdw_cdns_check_self_clearing_bits(struct sdw_cdns *cdns, const char *string,
bool initial_delay, int reset_iterations);

253
drivers/soundwire/intel.c
View File

@ -564,7 +564,7 @@ static void intel_pdi_init(struct sdw_intel *sdw,
{
void __iomem *shim = sdw->link_res->shim;
unsigned int link_id = sdw->instance;
int pcm_cap, pdm_cap;
int pcm_cap;
/* PCM Stream Capability */
pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id));
@ -575,41 +575,25 @@ static void intel_pdi_init(struct sdw_intel *sdw,
dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n",
config->pcm_bd, config->pcm_in, config->pcm_out);
/* PDM Stream Capability */
pdm_cap = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
config->pdm_bd = FIELD_GET(SDW_SHIM_PDMSCAP_BSS, pdm_cap);
config->pdm_in = FIELD_GET(SDW_SHIM_PDMSCAP_ISS, pdm_cap);
config->pdm_out = FIELD_GET(SDW_SHIM_PDMSCAP_OSS, pdm_cap);
dev_dbg(sdw->cdns.dev, "PDM cap bd:%d in:%d out:%d\n",
config->pdm_bd, config->pdm_in, config->pdm_out);
}
static int
intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num, bool pcm)
intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num)
{
void __iomem *shim = sdw->link_res->shim;
unsigned int link_id = sdw->instance;
int count;
if (pcm) {
count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num));
count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num));
/*
* WORKAROUND: on all existing Intel controllers, pdi
* number 2 reports channel count as 1 even though it
* supports 8 channels. Performing hardcoding for pdi
* number 2.
*/
if (pdi_num == 2)
count = 7;
} else {
count = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
count = FIELD_GET(SDW_SHIM_PDMSCAP_CPSS, count);
}
/*
* WORKAROUND: on all existing Intel controllers, pdi
* number 2 reports channel count as 1 even though it
* supports 8 channels. Performing hardcoding for pdi
* number 2.
*/
if (pdi_num == 2)
count = 7;
/* zero based values for channel count in register */
count++;
@ -620,12 +604,12 @@ intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num, bool pcm)
static int intel_pdi_get_ch_update(struct sdw_intel *sdw,
struct sdw_cdns_pdi *pdi,
unsigned int num_pdi,
unsigned int *num_ch, bool pcm)
unsigned int *num_ch)
{
int i, ch_count = 0;
for (i = 0; i < num_pdi; i++) {
pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num, pcm);
pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num);
ch_count += pdi->ch_count;
pdi++;
}
@ -635,25 +619,23 @@ static int intel_pdi_get_ch_update(struct sdw_intel *sdw,
}
static int intel_pdi_stream_ch_update(struct sdw_intel *sdw,
struct sdw_cdns_streams *stream, bool pcm)
struct sdw_cdns_streams *stream)
{
intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd,
&stream->num_ch_bd, pcm);
&stream->num_ch_bd);
intel_pdi_get_ch_update(sdw, stream->in, stream->num_in,
&stream->num_ch_in, pcm);
&stream->num_ch_in);
intel_pdi_get_ch_update(sdw, stream->out, stream->num_out,
&stream->num_ch_out, pcm);
&stream->num_ch_out);
return 0;
}
static int intel_pdi_ch_update(struct sdw_intel *sdw)
{
/* First update PCM streams followed by PDM streams */
intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm, true);
intel_pdi_stream_ch_update(sdw, &sdw->cdns.pdm, false);
intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm);
return 0;
}
@ -711,7 +693,7 @@ intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
}
static int intel_params_stream(struct sdw_intel *sdw,
struct snd_pcm_substream *substream,
int stream,
struct snd_soc_dai *dai,
struct snd_pcm_hw_params *hw_params,
int link_id, int alh_stream_id)
@ -719,7 +701,7 @@ static int intel_params_stream(struct sdw_intel *sdw,
struct sdw_intel_link_res *res = sdw->link_res;
struct sdw_intel_stream_params_data params_data;
params_data.substream = substream;
params_data.stream = stream; /* direction */
params_data.dai = dai;
params_data.hw_params = hw_params;
params_data.link_id = link_id;
@ -732,14 +714,14 @@ static int intel_params_stream(struct sdw_intel *sdw,
}
static int intel_free_stream(struct sdw_intel *sdw,
struct snd_pcm_substream *substream,
int stream,
struct snd_soc_dai *dai,
int link_id)
{
struct sdw_intel_link_res *res = sdw->link_res;
struct sdw_intel_stream_free_data free_data;
free_data.substream = substream;
free_data.stream = stream; /* direction */
free_data.dai = dai;
free_data.link_id = link_id;
@ -840,7 +822,6 @@ static int intel_hw_params(struct snd_pcm_substream *substream,
struct sdw_port_config *pconfig;
int ch, dir;
int ret;
bool pcm = true;
dma = snd_soc_dai_get_dma_data(dai, substream);
if (!dma)
@ -852,13 +833,7 @@ static int intel_hw_params(struct snd_pcm_substream *substream,
else
dir = SDW_DATA_DIR_TX;
if (dma->stream_type == SDW_STREAM_PDM)
pcm = false;
if (pcm)
pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, ch, dir, dai->id);
else
pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pdm, ch, dir, dai->id);
pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, ch, dir, dai->id);
if (!pdi) {
ret = -EINVAL;
@ -871,12 +846,13 @@ static int intel_hw_params(struct snd_pcm_substream *substream,
sdw_cdns_config_stream(cdns, ch, dir, pdi);
/* store pdi and hw_params, may be needed in prepare step */
dma->paused = false;
dma->suspended = false;
dma->pdi = pdi;
dma->hw_params = params;
/* Inform DSP about PDI stream number */
ret = intel_params_stream(sdw, substream, dai, params,
ret = intel_params_stream(sdw, substream->stream, dai, params,
sdw->instance,
pdi->intel_alh_id);
if (ret)
@ -887,12 +863,7 @@ static int intel_hw_params(struct snd_pcm_substream *substream,
sconfig.frame_rate = params_rate(params);
sconfig.type = dma->stream_type;
if (dma->stream_type == SDW_STREAM_PDM) {
sconfig.frame_rate *= 50;
sconfig.bps = 1;
} else {
sconfig.bps = snd_pcm_format_width(params_format(params));
}
sconfig.bps = snd_pcm_format_width(params_format(params));
/* Port configuration */
pconfig = kzalloc(sizeof(*pconfig), GFP_KERNEL);
@ -953,7 +924,7 @@ static int intel_prepare(struct snd_pcm_substream *substream,
sdw_cdns_config_stream(cdns, ch, dir, dma->pdi);
/* Inform DSP about PDI stream number */
ret = intel_params_stream(sdw, substream, dai,
ret = intel_params_stream(sdw, substream->stream, dai,
dma->hw_params,
sdw->instance,
dma->pdi->intel_alh_id);
@ -987,7 +958,7 @@ intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
return ret;
}
ret = intel_free_stream(sdw, substream, dai, sdw->instance);
ret = intel_free_stream(sdw, substream->stream, dai, sdw->instance);
if (ret < 0) {
dev_err(dai->dev, "intel_free_stream: failed %d\n", ret);
return ret;
@ -1008,39 +979,10 @@ static void intel_shutdown(struct snd_pcm_substream *substream,
pm_runtime_put_autosuspend(cdns->dev);
}
static int intel_component_dais_suspend(struct snd_soc_component *component)
{
struct sdw_cdns_dma_data *dma;
struct snd_soc_dai *dai;
for_each_component_dais(component, dai) {
/*
* we don't have a .suspend dai_ops, and we don't have access
* to the substream, so let's mark both capture and playback
* DMA contexts as suspended
*/
dma = dai->playback_dma_data;
if (dma)
dma->suspended = true;
dma = dai->capture_dma_data;
if (dma)
dma->suspended = true;
}
return 0;
}
static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai,
void *stream, int direction)
{
return cdns_set_sdw_stream(dai, stream, true, direction);
}
static int intel_pdm_set_sdw_stream(struct snd_soc_dai *dai,
void *stream, int direction)
{
return cdns_set_sdw_stream(dai, stream, false, direction);
return cdns_set_sdw_stream(dai, stream, direction);
}
static void *intel_get_sdw_stream(struct snd_soc_dai *dai,
@ -1059,24 +1001,100 @@ static void *intel_get_sdw_stream(struct snd_soc_dai *dai,
return dma->stream;
}
static int intel_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai)
{
struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
struct sdw_intel *sdw = cdns_to_intel(cdns);
struct sdw_cdns_dma_data *dma;
int ret = 0;
dma = snd_soc_dai_get_dma_data(dai, substream);
if (!dma) {
dev_err(dai->dev, "failed to get dma data in %s\n",
__func__);
return -EIO;
}
switch (cmd) {
case SNDRV_PCM_TRIGGER_SUSPEND:
/*
* The .prepare callback is used to deal with xruns and resume operations.
* In the case of xruns, the DMAs and SHIM registers cannot be touched,
* but for resume operations the DMAs and SHIM registers need to be initialized.
* the .trigger callback is used to track the suspend case only.
*/
dma->suspended = true;
ret = intel_free_stream(sdw, substream->stream, dai, sdw->instance);
break;
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
dma->paused = true;
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
dma->paused = false;
break;
default:
break;
}
return ret;
}
static int intel_component_dais_suspend(struct snd_soc_component *component)
{
struct snd_soc_dai *dai;
/*
* In the corner case where a SUSPEND happens during a PAUSE, the ALSA core
* does not throw the TRIGGER_SUSPEND. This leaves the DAIs in an unbalanced state.
* Since the component suspend is called last, we can trap this corner case
* and force the DAIs to release their resources.
*/
for_each_component_dais(component, dai) {
struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
struct sdw_intel *sdw = cdns_to_intel(cdns);
struct sdw_cdns_dma_data *dma;
int stream;
int ret;
dma = dai->playback_dma_data;
stream = SNDRV_PCM_STREAM_PLAYBACK;
if (!dma) {
dma = dai->capture_dma_data;
stream = SNDRV_PCM_STREAM_CAPTURE;
}
if (!dma)
continue;
if (dma->suspended)
continue;
if (dma->paused) {
dma->suspended = true;
ret = intel_free_stream(sdw, stream, dai, sdw->instance);
if (ret < 0)
return ret;
}
}
return 0;
}
static const struct snd_soc_dai_ops intel_pcm_dai_ops = {
.startup = intel_startup,
.hw_params = intel_hw_params,
.prepare = intel_prepare,
.hw_free = intel_hw_free,
.trigger = intel_trigger,
.shutdown = intel_shutdown,
.set_sdw_stream = intel_pcm_set_sdw_stream,
.get_sdw_stream = intel_get_sdw_stream,
};
static const struct snd_soc_dai_ops intel_pdm_dai_ops = {
.startup = intel_startup,
.hw_params = intel_hw_params,
.prepare = intel_prepare,
.hw_free = intel_hw_free,
.shutdown = intel_shutdown,
.set_sdw_stream = intel_pdm_set_sdw_stream,
.get_sdw_stream = intel_get_sdw_stream,
.set_stream = intel_pcm_set_sdw_stream,
.get_stream = intel_get_sdw_stream,
};
static const struct snd_soc_component_driver dai_component = {
@ -1087,7 +1105,7 @@ static const struct snd_soc_component_driver dai_component = {
static int intel_create_dai(struct sdw_cdns *cdns,
struct snd_soc_dai_driver *dais,
enum intel_pdi_type type,
u32 num, u32 off, u32 max_ch, bool pcm)
u32 num, u32 off, u32 max_ch)
{
int i;
@ -1116,10 +1134,7 @@ static int intel_create_dai(struct sdw_cdns *cdns,
dais[i].capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
}
if (pcm)
dais[i].ops = &intel_pcm_dai_ops;
else
dais[i].ops = &intel_pdm_dai_ops;
dais[i].ops = &intel_pcm_dai_ops;
}
return 0;
@ -1133,7 +1148,7 @@ static int intel_register_dai(struct sdw_intel *sdw)
int num_dai, ret, off = 0;
/* DAIs are created based on total number of PDIs supported */
num_dai = cdns->pcm.num_pdi + cdns->pdm.num_pdi;
num_dai = cdns->pcm.num_pdi;
dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL);
if (!dais)
@ -1143,39 +1158,19 @@ static int intel_register_dai(struct sdw_intel *sdw)
stream = &cdns->pcm;
ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pcm.num_in,
off, stream->num_ch_in, true);
off, stream->num_ch_in);
if (ret)
return ret;
off += cdns->pcm.num_in;
ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out,
off, stream->num_ch_out, true);
off, stream->num_ch_out);
if (ret)
return ret;
off += cdns->pcm.num_out;
ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd,
off, stream->num_ch_bd, true);
if (ret)
return ret;
/* Create PDM DAIs */
stream = &cdns->pdm;
off += cdns->pcm.num_bd;
ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pdm.num_in,
off, stream->num_ch_in, false);
if (ret)
return ret;
off += cdns->pdm.num_in;
ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pdm.num_out,
off, stream->num_ch_out, false);
if (ret)
return ret;
off += cdns->pdm.num_out;
ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pdm.num_bd,
off, stream->num_ch_bd, false);
off, stream->num_ch_bd);
if (ret)
return ret;
@ -1549,7 +1544,7 @@ static int __maybe_unused intel_pm_prepare(struct device *dev)
struct sdw_intel *sdw = cdns_to_intel(cdns);
struct sdw_bus *bus = &cdns->bus;
u32 clock_stop_quirks;
int ret = 0;
int ret;
if (bus->prop.hw_disabled || !sdw->startup_done) {
dev_dbg(dev, "SoundWire master %d is disabled or not-started, ignoring\n",

8
drivers/soundwire/qcom.c
View File

@ -1024,8 +1024,8 @@ static int qcom_swrm_startup(struct snd_pcm_substream *substream,
ctrl->sruntime[dai->id] = sruntime;
for_each_rtd_codec_dais(rtd, i, codec_dai) {
ret = snd_soc_dai_set_sdw_stream(codec_dai, sruntime,
substream->stream);
ret = snd_soc_dai_set_stream(codec_dai, sruntime,
substream->stream);
if (ret < 0 && ret != -ENOTSUPP) {
dev_err(dai->dev, "Failed to set sdw stream on %s\n",
codec_dai->name);
@ -1051,8 +1051,8 @@ static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = {
.hw_free = qcom_swrm_hw_free,
.startup = qcom_swrm_startup,
.shutdown = qcom_swrm_shutdown,
.set_sdw_stream = qcom_swrm_set_sdw_stream,
.get_sdw_stream = qcom_swrm_get_sdw_stream,
.set_stream = qcom_swrm_set_sdw_stream,
.get_stream = qcom_swrm_get_sdw_stream,
};
static const struct snd_soc_component_driver qcom_swrm_dai_component = {

4
drivers/soundwire/stream.c
View File

@ -1863,7 +1863,7 @@ static int set_stream(struct snd_pcm_substream *substream,
/* Set stream pointer on all DAIs */
for_each_rtd_dais(rtd, i, dai) {
ret = snd_soc_dai_set_sdw_stream(dai, sdw_stream, substream->stream);
ret = snd_soc_dai_set_stream(dai, sdw_stream, substream->stream);
if (ret < 0) {
dev_err(rtd->dev, "failed to set stream pointer on dai %s\n", dai->name);
break;
@ -1934,7 +1934,7 @@ void sdw_shutdown_stream(void *sdw_substream)
/* Find stream from first CPU DAI */
dai = asoc_rtd_to_cpu(rtd, 0);
sdw_stream = snd_soc_dai_get_sdw_stream(dai, substream->stream);
sdw_stream = snd_soc_dai_get_stream(dai, substream->stream);
if (IS_ERR(sdw_stream)) {
dev_err(rtd->dev, "no stream found for DAI %s\n", dai->name);

2
drivers/spi/spi-pic32.c
View File

@ -370,7 +370,6 @@ static int pic32_spi_dma_config(struct pic32_spi *pic32s, u32 dma_width)
cfg.src_addr_width = dma_width;
cfg.dst_addr_width = dma_width;
/* tx channel */
cfg.slave_id = pic32s->tx_irq;
cfg.direction = DMA_MEM_TO_DEV;
ret = dmaengine_slave_config(master->dma_tx, &cfg);
if (ret) {
@ -378,7 +377,6 @@ static int pic32_spi_dma_config(struct pic32_spi *pic32s, u32 dma_width)
return ret;
}
/* rx channel */
cfg.slave_id = pic32s->rx_irq;
cfg.direction = DMA_DEV_TO_MEM;
ret = dmaengine_slave_config(master->dma_rx, &cfg);
if (ret)

15
drivers/tty/serial/msm_serial.c
View File

@ -9,6 +9,7 @@
#include <linux/kernel.h>
#include <linux/atomic.h>
#include <linux/dma/qcom_adm.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/module.h>
@ -290,6 +291,7 @@ static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base)
{
struct device *dev = msm_port->uart.dev;
struct dma_slave_config conf;
struct qcom_adm_peripheral_config periph_conf = {};
struct msm_dma *dma;
u32 crci = 0;
int ret;
@ -308,7 +310,11 @@ static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base)
conf.device_fc = true;
conf.dst_addr = base + UARTDM_TF;
conf.dst_maxburst = UARTDM_BURST_SIZE;
conf.slave_id = crci;
if (crci) {
conf.peripheral_config = &periph_conf;
conf.peripheral_size = sizeof(periph_conf);
periph_conf.crci = crci;
}
ret = dmaengine_slave_config(dma->chan, &conf);
if (ret)
@ -333,6 +339,7 @@ static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base)
{
struct device *dev = msm_port->uart.dev;
struct dma_slave_config conf;
struct qcom_adm_peripheral_config periph_conf = {};
struct msm_dma *dma;
u32 crci = 0;
int ret;
@ -355,7 +362,11 @@ static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base)
conf.device_fc = true;
conf.src_addr = base + UARTDM_RF;
conf.src_maxburst = UARTDM_BURST_SIZE;
conf.slave_id = crci;
if (crci) {
conf.peripheral_config = &periph_conf;
conf.peripheral_size = sizeof(periph_conf);
periph_conf.crci = crci;
}
ret = dmaengine_slave_config(dma->chan, &conf);
if (ret)

1
include/dt-bindings/sound/rt5640.h
View File

@ -16,6 +16,7 @@
#define RT5640_JD_SRC_GPIO2 4
#define RT5640_JD_SRC_GPIO3 5
#define RT5640_JD_SRC_GPIO4 6
#define RT5640_JD_SRC_HDA_HEADER 7
#define RT5640_OVCD_SF_0P5 0
#define RT5640_OVCD_SF_0P75 1

28
include/dt-bindings/sound/tlv320adc3xxx.h Normal file
View File

@ -0,0 +1,28 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Devicetree bindings definitions for tlv320adc3xxx driver.
*
* Copyright (C) 2021 Axis Communications AB
*/
#ifndef __DT_TLV320ADC3XXX_H
#define __DT_TLV320ADC3XXX_H
#define ADC3XXX_GPIO_DISABLED 0 /* I/O buffers powered down */
#define ADC3XXX_GPIO_INPUT 1 /* Various non-GPIO inputs */
#define ADC3XXX_GPIO_GPI 2 /* General purpose input */
#define ADC3XXX_GPIO_GPO 3 /* General purpose output */
#define ADC3XXX_GPIO_CLKOUT 4 /* Source set in reg. CLKOUT_MUX */
#define ADC3XXX_GPIO_INT1 5 /* INT1 output */
#define ADC3XXX_GPIO_INT2 6 /* INT2 output */
/* value 7 is reserved */
#define ADC3XXX_GPIO_SECONDARY_BCLK 8 /* Codec interface secondary BCLK */
#define ADC3XXX_GPIO_SECONDARY_WCLK 9 /* Codec interface secondary WCLK */
#define ADC3XXX_GPIO_ADC_MOD_CLK 10 /* Clock output for digital mics */
/* values 11-15 reserved */
#define ADC3XXX_MICBIAS_OFF 0 /* Micbias pin powered off */
#define ADC3XXX_MICBIAS_2_0V 1 /* Micbias pin set to 2.0V */
#define ADC3XXX_MICBIAS_2_5V 2 /* Micbias pin set to 2.5V */
#define ADC3XXX_MICBIAS_AVDD 3 /* Use AVDD voltage for micbias pin */
#endif /* __DT_TLV320ADC3XXX_H */

12
include/linux/dma/qcom_adm.h Normal file
View File

@ -0,0 +1,12 @@
// SPDX-License-Identifier: GPL-2.0-only
#ifndef __LINUX_DMA_QCOM_ADM_H
#define __LINUX_DMA_QCOM_ADM_H
#include <linux/types.h>
struct qcom_adm_peripheral_config {
u32 crci;
u32 mux;
};
#endif /* __LINUX_DMA_QCOM_ADM_H */

11
include/linux/dma/xilinx_dpdma.h Normal file
View File

@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0
#ifndef __LINUX_DMA_XILINX_DPDMA_H
#define __LINUX_DMA_XILINX_DPDMA_H
#include <linux/types.h>
struct xilinx_dpdma_peripheral_config {
bool video_group;
};
#endif /* __LINUX_DMA_XILINX_DPDMA_H */

4
include/linux/dmaengine.h
View File

@ -418,9 +418,6 @@ enum dma_slave_buswidth {
* @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
* with 'true' if peripheral should be flow controller. Direction will be
* selected at Runtime.
* @slave_id: Slave requester id. Only valid for slave channels. The dma
* slave peripheral will have unique id as dma requester which need to be
* pass as slave config.
* @peripheral_config: peripheral configuration for programming peripheral
* for dmaengine transfer
* @peripheral_size: peripheral configuration buffer size
@ -448,7 +445,6 @@ struct dma_slave_config {
u32 src_port_window_size;
u32 dst_port_window_size;
bool device_fc;
unsigned int slave_id;
void *peripheral_config;
size_t peripheral_size;
};

21
include/linux/firmware/cirrus/cs_dsp.h
View File

@ -11,6 +11,11 @@
#ifndef __CS_DSP_H
#define __CS_DSP_H
#include <linux/device.h>
#include <linux/firmware.h>
#include <linux/list.h>
#include <linux/regmap.h>
#define CS_ADSP2_REGION_0 BIT(0)
#define CS_ADSP2_REGION_1 BIT(1)
#define CS_ADSP2_REGION_2 BIT(2)
@ -49,12 +54,14 @@ struct cs_dsp_region {
* struct cs_dsp_alg_region - Describes a logical algorithm region in DSP address space
* @list: List node for internal use
* @alg: Algorithm id
* @ver: Expected algorithm version
* @type: Memory region type
* @base: Address of region
*/
struct cs_dsp_alg_region {
struct list_head list;
unsigned int alg;
unsigned int ver;
int type;
unsigned int base;
};
@ -69,8 +76,8 @@ struct cs_dsp_alg_region {
* @enabled: Flag indicating whether control is enabled
* @list: List node for internal use
* @cache: Cached value of the control
* @offset: Offset of control within alg_region
* @len: Length of the cached value
* @offset: Offset of control within alg_region in words
* @len: Length of the cached value in bytes
* @set: Flag indicating the value has been written by the user
* @flags: Bitfield of WMFW_CTL_FLAG_ control flags defined in wmfw.h
* @type: One of the WMFW_CTL_TYPE_ control types defined in wmfw.h
@ -180,7 +187,8 @@ struct cs_dsp {
* struct cs_dsp_client_ops - client callbacks
* @control_add: Called under the pwr_lock when a control is created
* @control_remove: Called under the pwr_lock when a control is destroyed
* @post_run: Called under the pwr_lock by cs_dsp_run()
* @pre_run: Called under the pwr_lock by cs_dsp_run() before the core is started
* @post_run: Called under the pwr_lock by cs_dsp_run() after the core is started
* @post_stop: Called under the pwr_lock by cs_dsp_stop()
* @watchdog_expired: Called when a watchdog expiry is detected
*
@ -190,6 +198,7 @@ struct cs_dsp {
struct cs_dsp_client_ops {
int (*control_add)(struct cs_dsp_coeff_ctl *ctl);
void (*control_remove)(struct cs_dsp_coeff_ctl *ctl);
int (*pre_run)(struct cs_dsp *dsp);
int (*post_run)(struct cs_dsp *dsp);
void (*post_stop)(struct cs_dsp *dsp);
void (*watchdog_expired)(struct cs_dsp *dsp);
@ -223,8 +232,10 @@ void cs_dsp_init_debugfs(struct cs_dsp *dsp, struct dentry *debugfs_root);
void cs_dsp_cleanup_debugfs(struct cs_dsp *dsp);
int cs_dsp_coeff_write_acked_control(struct cs_dsp_coeff_ctl *ctl, unsigned int event_id);
int cs_dsp_coeff_write_ctrl(struct cs_dsp_coeff_ctl *ctl, const void *buf, size_t len);
int cs_dsp_coeff_read_ctrl(struct cs_dsp_coeff_ctl *ctl, void *buf, size_t len);
int cs_dsp_coeff_write_ctrl(struct cs_dsp_coeff_ctl *ctl, unsigned int off,
const void *buf, size_t len);
int cs_dsp_coeff_read_ctrl(struct cs_dsp_coeff_ctl *ctl, unsigned int off,
void *buf, size_t len);
struct cs_dsp_coeff_ctl *cs_dsp_get_ctl(struct cs_dsp *dsp, const char *name, int type,
unsigned int alg);

1
include/linux/firmware/cirrus/wmfw.h
View File

@ -29,6 +29,7 @@
#define WMFW_CTL_TYPE_ACKED 0x1000 /* acked control */
#define WMFW_CTL_TYPE_HOSTEVENT 0x1001 /* event control */
#define WMFW_CTL_TYPE_HOST_BUFFER 0x1002 /* host buffer pointer */
#define WMFW_CTL_TYPE_FWEVENT 0x1004 /* firmware event control */
struct wmfw_header {
char magic[4];

4
include/linux/soundwire/sdw_intel.h
View File

@ -92,7 +92,7 @@
* firmware.
*/
struct sdw_intel_stream_params_data {
struct snd_pcm_substream *substream;
int stream;
struct snd_soc_dai *dai;
struct snd_pcm_hw_params *hw_params;
int link_id;
@ -105,7 +105,7 @@ struct sdw_intel_stream_params_data {
* firmware.
*/
struct sdw_intel_stream_free_data {
struct snd_pcm_substream *substream;
int stream;
struct snd_soc_dai *dai;
int link_id;
};

746
include/sound/cs35l41.h
View File

@ -10,6 +10,725 @@
#ifndef __CS35L41_H
#define __CS35L41_H
#include <linux/regmap.h>
#define CS35L41_FIRSTREG 0x00000000
#define CS35L41_LASTREG 0x03804FE8
#define CS35L41_DEVID 0x00000000
#define CS35L41_REVID 0x00000004
#define CS35L41_FABID 0x00000008
#define CS35L41_RELID 0x0000000C
#define CS35L41_OTPID 0x00000010
#define CS35L41_SFT_RESET 0x00000020
#define CS35L41_TEST_KEY_CTL 0x00000040
#define CS35L41_USER_KEY_CTL 0x00000044
#define CS35L41_OTP_MEM0 0x00000400
#define CS35L41_OTP_MEM31 0x0000047C
#define CS35L41_OTP_CTRL0 0x00000500
#define CS35L41_OTP_CTRL1 0x00000504
#define CS35L41_OTP_CTRL3 0x00000508
#define CS35L41_OTP_CTRL4 0x0000050C
#define CS35L41_OTP_CTRL5 0x00000510
#define CS35L41_OTP_CTRL6 0x00000514
#define CS35L41_OTP_CTRL7 0x00000518
#define CS35L41_OTP_CTRL8 0x0000051C
#define CS35L41_PWR_CTRL1 0x00002014
#define CS35L41_PWR_CTRL2 0x00002018
#define CS35L41_PWR_CTRL3 0x0000201C
#define CS35L41_CTRL_OVRRIDE 0x00002020
#define CS35L41_AMP_OUT_MUTE 0x00002024
#define CS35L41_PROTECT_REL_ERR_IGN 0x00002034
#define CS35L41_GPIO_PAD_CONTROL 0x0000242C
#define CS35L41_JTAG_CONTROL 0x00002438
#define CS35L41_PWRMGT_CTL 0x00002900
#define CS35L41_WAKESRC_CTL 0x00002904
#define CS35L41_PWRMGT_STS 0x00002908
#define CS35L41_PLL_CLK_CTRL 0x00002C04
#define CS35L41_DSP_CLK_CTRL 0x00002C08
#define CS35L41_GLOBAL_CLK_CTRL 0x00002C0C
#define CS35L41_DATA_FS_SEL 0x00002C10
#define CS35L41_TST_FS_MON0 0x00002D10
#define CS35L41_MDSYNC_EN 0x00003400
#define CS35L41_MDSYNC_TX_ID 0x00003408
#define CS35L41_MDSYNC_PWR_CTRL 0x0000340C
#define CS35L41_MDSYNC_DATA_TX 0x00003410
#define CS35L41_MDSYNC_TX_STATUS 0x00003414
#define CS35L41_MDSYNC_DATA_RX 0x0000341C
#define CS35L41_MDSYNC_RX_STATUS 0x00003420
#define CS35L41_MDSYNC_ERR_STATUS 0x00003424
#define CS35L41_MDSYNC_SYNC_PTE2 0x00003528
#define CS35L41_MDSYNC_SYNC_PTE3 0x0000352C
#define CS35L41_MDSYNC_SYNC_MSM_STATUS 0x0000353C
#define CS35L41_BSTCVRT_VCTRL1 0x00003800
#define CS35L41_BSTCVRT_VCTRL2 0x00003804
#define CS35L41_BSTCVRT_PEAK_CUR 0x00003808
#define CS35L41_BSTCVRT_SFT_RAMP 0x0000380C
#define CS35L41_BSTCVRT_COEFF 0x00003810
#define CS35L41_BSTCVRT_SLOPE_LBST 0x00003814
#define CS35L41_BSTCVRT_SW_FREQ 0x00003818
#define CS35L41_BSTCVRT_DCM_CTRL 0x0000381C
#define CS35L41_BSTCVRT_DCM_MODE_FORCE 0x00003820
#define CS35L41_BSTCVRT_OVERVOLT_CTRL 0x00003830
#define CS35L41_VI_VOL_POL 0x00004000
#define CS35L41_VIMON_SPKMON_RESYNC 0x00004100
#define CS35L41_DTEMP_WARN_THLD 0x00004220
#define CS35L41_DTEMP_CFG 0x00004224
#define CS35L41_DTEMP_EN 0x00004308
#define CS35L41_VPVBST_FS_SEL 0x00004400
#define CS35L41_SP_ENABLES 0x00004800
#define CS35L41_SP_RATE_CTRL 0x00004804
#define CS35L41_SP_FORMAT 0x00004808
#define CS35L41_SP_HIZ_CTRL 0x0000480C
#define CS35L41_SP_FRAME_TX_SLOT 0x00004810
#define CS35L41_SP_FRAME_RX_SLOT 0x00004820
#define CS35L41_SP_TX_WL 0x00004830
#define CS35L41_SP_RX_WL 0x00004840
#define CS35L41_ASP_CONTROL4 0x00004854
#define CS35L41_DAC_PCM1_SRC 0x00004C00
#define CS35L41_ASP_TX1_SRC 0x00004C20
#define CS35L41_ASP_TX2_SRC 0x00004C24
#define CS35L41_ASP_TX3_SRC 0x00004C28
#define CS35L41_ASP_TX4_SRC 0x00004C2C
#define CS35L41_DSP1_RX1_SRC 0x00004C40
#define CS35L41_DSP1_RX2_SRC 0x00004C44
#define CS35L41_DSP1_RX3_SRC 0x00004C48
#define CS35L41_DSP1_RX4_SRC 0x00004C4C
#define CS35L41_DSP1_RX5_SRC 0x00004C50
#define CS35L41_DSP1_RX6_SRC 0x00004C54
#define CS35L41_DSP1_RX7_SRC 0x00004C58
#define CS35L41_DSP1_RX8_SRC 0x00004C5C
#define CS35L41_NGATE1_SRC 0x00004C60
#define CS35L41_NGATE2_SRC 0x00004C64
#define CS35L41_AMP_DIG_VOL_CTRL 0x00006000
#define CS35L41_VPBR_CFG 0x00006404
#define CS35L41_VBBR_CFG 0x00006408
#define CS35L41_VPBR_STATUS 0x0000640C
#define CS35L41_VBBR_STATUS 0x00006410
#define CS35L41_OVERTEMP_CFG 0x00006414
#define CS35L41_AMP_ERR_VOL 0x00006418
#define CS35L41_VOL_STATUS_TO_DSP 0x00006450
#define CS35L41_CLASSH_CFG 0x00006800
#define CS35L41_WKFET_CFG 0x00006804
#define CS35L41_NG_CFG 0x00006808
#define CS35L41_AMP_GAIN_CTRL 0x00006C04
#define CS35L41_DAC_MSM_CFG 0x00007400
#define CS35L41_IRQ1_CFG 0x00010000
#define CS35L41_IRQ1_STATUS 0x00010004
#define CS35L41_IRQ1_STATUS1 0x00010010
#define CS35L41_IRQ1_STATUS2 0x00010014
#define CS35L41_IRQ1_STATUS3 0x00010018
#define CS35L41_IRQ1_STATUS4 0x0001001C
#define CS35L41_IRQ1_RAW_STATUS1 0x00010090
#define CS35L41_IRQ1_RAW_STATUS2 0x00010094
#define CS35L41_IRQ1_RAW_STATUS3 0x00010098
#define CS35L41_IRQ1_RAW_STATUS4 0x0001009C
#define CS35L41_IRQ1_MASK1 0x00010110
#define CS35L41_IRQ1_MASK2 0x00010114
#define CS35L41_IRQ1_MASK3 0x00010118
#define CS35L41_IRQ1_MASK4 0x0001011C
#define CS35L41_IRQ1_FRC1 0x00010190
#define CS35L41_IRQ1_FRC2 0x00010194
#define CS35L41_IRQ1_FRC3 0x00010198
#define CS35L41_IRQ1_FRC4 0x0001019C
#define CS35L41_IRQ1_EDGE1 0x00010210
#define CS35L41_IRQ1_EDGE4 0x0001021C
#define CS35L41_IRQ1_POL1 0x00010290
#define CS35L41_IRQ1_POL2 0x00010294
#define CS35L41_IRQ1_POL3 0x00010298
#define CS35L41_IRQ1_POL4 0x0001029C
#define CS35L41_IRQ1_DB3 0x00010318
#define CS35L41_IRQ2_CFG 0x00010800
#define CS35L41_IRQ2_STATUS 0x00010804
#define CS35L41_IRQ2_STATUS1 0x00010810
#define CS35L41_IRQ2_STATUS2 0x00010814
#define CS35L41_IRQ2_STATUS3 0x00010818
#define CS35L41_IRQ2_STATUS4 0x0001081C
#define CS35L41_IRQ2_RAW_STATUS1 0x00010890
#define CS35L41_IRQ2_RAW_STATUS2 0x00010894
#define CS35L41_IRQ2_RAW_STATUS3 0x00010898
#define CS35L41_IRQ2_RAW_STATUS4 0x0001089C
#define CS35L41_IRQ2_MASK1 0x00010910
#define CS35L41_IRQ2_MASK2 0x00010914
#define CS35L41_IRQ2_MASK3 0x00010918
#define CS35L41_IRQ2_MASK4 0x0001091C
#define CS35L41_IRQ2_FRC1 0x00010990
#define CS35L41_IRQ2_FRC2 0x00010994
#define CS35L41_IRQ2_FRC3 0x00010998
#define CS35L41_IRQ2_FRC4 0x0001099C
#define CS35L41_IRQ2_EDGE1 0x00010A10
#define CS35L41_IRQ2_EDGE4 0x00010A1C
#define CS35L41_IRQ2_POL1 0x00010A90
#define CS35L41_IRQ2_POL2 0x00010A94
#define CS35L41_IRQ2_POL3 0x00010A98
#define CS35L41_IRQ2_POL4 0x00010A9C
#define CS35L41_IRQ2_DB3 0x00010B18
#define CS35L41_GPIO_STATUS1 0x00011000
#define CS35L41_GPIO1_CTRL1 0x00011008
#define CS35L41_GPIO2_CTRL1 0x0001100C
#define CS35L41_MIXER_NGATE_CFG 0x00012000
#define CS35L41_MIXER_NGATE_CH1_CFG 0x00012004
#define CS35L41_MIXER_NGATE_CH2_CFG 0x00012008
#define CS35L41_DSP_MBOX_1 0x00013000
#define CS35L41_DSP_MBOX_2 0x00013004
#define CS35L41_DSP_MBOX_3 0x00013008
#define CS35L41_DSP_MBOX_4 0x0001300C
#define CS35L41_DSP_MBOX_5 0x00013010
#define CS35L41_DSP_MBOX_6 0x00013014
#define CS35L41_DSP_MBOX_7 0x00013018
#define CS35L41_DSP_MBOX_8 0x0001301C
#define CS35L41_DSP_VIRT1_MBOX_1 0x00013020
#define CS35L41_DSP_VIRT1_MBOX_2 0x00013024
#define CS35L41_DSP_VIRT1_MBOX_3 0x00013028
#define CS35L41_DSP_VIRT1_MBOX_4 0x0001302C
#define CS35L41_DSP_VIRT1_MBOX_5 0x00013030
#define CS35L41_DSP_VIRT1_MBOX_6 0x00013034
#define CS35L41_DSP_VIRT1_MBOX_7 0x00013038
#define CS35L41_DSP_VIRT1_MBOX_8 0x0001303C
#define CS35L41_DSP_VIRT2_MBOX_1 0x00013040
#define CS35L41_DSP_VIRT2_MBOX_2 0x00013044
#define CS35L41_DSP_VIRT2_MBOX_3 0x00013048
#define CS35L41_DSP_VIRT2_MBOX_4 0x0001304C
#define CS35L41_DSP_VIRT2_MBOX_5 0x00013050
#define CS35L41_DSP_VIRT2_MBOX_6 0x00013054
#define CS35L41_DSP_VIRT2_MBOX_7 0x00013058
#define CS35L41_DSP_VIRT2_MBOX_8 0x0001305C
#define CS35L41_CLOCK_DETECT_1 0x00014000
#define CS35L41_TIMER1_CONTROL 0x00015000
#define CS35L41_TIMER1_COUNT_PRESET 0x00015004
#define CS35L41_TIMER1_START_STOP 0x0001500C
#define CS35L41_TIMER1_STATUS 0x00015010
#define CS35L41_TIMER1_COUNT_READBACK 0x00015014
#define CS35L41_TIMER1_DSP_CLK_CFG 0x00015018
#define CS35L41_TIMER1_DSP_CLK_STATUS 0x0001501C
#define CS35L41_TIMER2_CONTROL 0x00015100
#define CS35L41_TIMER2_COUNT_PRESET 0x00015104
#define CS35L41_TIMER2_START_STOP 0x0001510C
#define CS35L41_TIMER2_STATUS 0x00015110
#define CS35L41_TIMER2_COUNT_READBACK 0x00015114
#define CS35L41_TIMER2_DSP_CLK_CFG 0x00015118
#define CS35L41_TIMER2_DSP_CLK_STATUS 0x0001511C
#define CS35L41_DFT_JTAG_CONTROL 0x00016000
#define CS35L41_DIE_STS1 0x00017040
#define CS35L41_DIE_STS2 0x00017044
#define CS35L41_TEMP_CAL1 0x00017048
#define CS35L41_TEMP_CAL2 0x0001704C
#define CS35L41_DSP1_XMEM_PACK_0 0x02000000
#define CS35L41_DSP1_XMEM_PACK_3068 0x02002FF0
#define CS35L41_DSP1_XMEM_UNPACK32_0 0x02400000
#define CS35L41_DSP1_XMEM_UNPACK32_2046 0x02401FF8
#define CS35L41_DSP1_TIMESTAMP_COUNT 0x025C0800
#define CS35L41_DSP1_SYS_ID 0x025E0000
#define CS35L41_DSP1_SYS_VERSION 0x025E0004
#define CS35L41_DSP1_SYS_CORE_ID 0x025E0008
#define CS35L41_DSP1_SYS_AHB_ADDR 0x025E000C
#define CS35L41_DSP1_SYS_XSRAM_SIZE 0x025E0010
#define CS35L41_DSP1_SYS_YSRAM_SIZE 0x025E0018
#define CS35L41_DSP1_SYS_PSRAM_SIZE 0x025E0020
#define CS35L41_DSP1_SYS_PM_BOOT_SIZE 0x025E0028
#define CS35L41_DSP1_SYS_FEATURES 0x025E002C
#define CS35L41_DSP1_SYS_FIR_FILTERS 0x025E0030
#define CS35L41_DSP1_SYS_LMS_FILTERS 0x025E0034
#define CS35L41_DSP1_SYS_XM_BANK_SIZE 0x025E0038
#define CS35L41_DSP1_SYS_YM_BANK_SIZE 0x025E003C
#define CS35L41_DSP1_SYS_PM_BANK_SIZE 0x025E0040
#define CS35L41_DSP1_AHBM_WIN0_CTRL0 0x025E2000
#define CS35L41_DSP1_AHBM_WIN0_CTRL1 0x025E2004
#define CS35L41_DSP1_AHBM_WIN1_CTRL0 0x025E2008
#define CS35L41_DSP1_AHBM_WIN1_CTRL1 0x025E200C
#define CS35L41_DSP1_AHBM_WIN2_CTRL0 0x025E2010
#define CS35L41_DSP1_AHBM_WIN2_CTRL1 0x025E2014
#define CS35L41_DSP1_AHBM_WIN3_CTRL0 0x025E2018
#define CS35L41_DSP1_AHBM_WIN3_CTRL1 0x025E201C
#define CS35L41_DSP1_AHBM_WIN4_CTRL0 0x025E2020
#define CS35L41_DSP1_AHBM_WIN4_CTRL1 0x025E2024
#define CS35L41_DSP1_AHBM_WIN5_CTRL0 0x025E2028
#define CS35L41_DSP1_AHBM_WIN5_CTRL1 0x025E202C
#define CS35L41_DSP1_AHBM_WIN6_CTRL0 0x025E2030
#define CS35L41_DSP1_AHBM_WIN6_CTRL1 0x025E2034
#define CS35L41_DSP1_AHBM_WIN7_CTRL0 0x025E2038
#define CS35L41_DSP1_AHBM_WIN7_CTRL1 0x025E203C
#define CS35L41_DSP1_AHBM_WIN_DBG_CTRL0 0x025E2040
#define CS35L41_DSP1_AHBM_WIN_DBG_CTRL1 0x025E2044
#define CS35L41_DSP1_XMEM_UNPACK24_0 0x02800000
#define CS35L41_DSP1_XMEM_UNPACK24_4093 0x02803FF4
#define CS35L41_DSP1_CTRL_BASE 0x02B80000
#define CS35L41_DSP1_CORE_SOFT_RESET 0x02B80010
#define CS35L41_DSP1_DEBUG 0x02B80040
#define CS35L41_DSP1_TIMER_CTRL 0x02B80048
#define CS35L41_DSP1_STREAM_ARB_CTRL 0x02B80050
#define CS35L41_DSP1_RX1_RATE 0x02B80080
#define CS35L41_DSP1_RX2_RATE 0x02B80088
#define CS35L41_DSP1_RX3_RATE 0x02B80090
#define CS35L41_DSP1_RX4_RATE 0x02B80098
#define CS35L41_DSP1_RX5_RATE 0x02B800A0
#define CS35L41_DSP1_RX6_RATE 0x02B800A8
#define CS35L41_DSP1_RX7_RATE 0x02B800B0
#define CS35L41_DSP1_RX8_RATE 0x02B800B8
#define CS35L41_DSP1_TX1_RATE 0x02B80280
#define CS35L41_DSP1_TX2_RATE 0x02B80288
#define CS35L41_DSP1_TX3_RATE 0x02B80290
#define CS35L41_DSP1_TX4_RATE 0x02B80298
#define CS35L41_DSP1_TX5_RATE 0x02B802A0
#define CS35L41_DSP1_TX6_RATE 0x02B802A8
#define CS35L41_DSP1_TX7_RATE 0x02B802B0
#define CS35L41_DSP1_TX8_RATE 0x02B802B8
#define CS35L41_DSP1_NMI_CTRL1 0x02B80480
#define CS35L41_DSP1_NMI_CTRL2 0x02B80488
#define CS35L41_DSP1_NMI_CTRL3 0x02B80490
#define CS35L41_DSP1_NMI_CTRL4 0x02B80498
#define CS35L41_DSP1_NMI_CTRL5 0x02B804A0
#define CS35L41_DSP1_NMI_CTRL6 0x02B804A8
#define CS35L41_DSP1_NMI_CTRL7 0x02B804B0
#define CS35L41_DSP1_NMI_CTRL8 0x02B804B8
#define CS35L41_DSP1_RESUME_CTRL 0x02B80500
#define CS35L41_DSP1_IRQ1_CTRL 0x02B80508
#define CS35L41_DSP1_IRQ2_CTRL 0x02B80510
#define CS35L41_DSP1_IRQ3_CTRL 0x02B80518
#define CS35L41_DSP1_IRQ4_CTRL 0x02B80520
#define CS35L41_DSP1_IRQ5_CTRL 0x02B80528
#define CS35L41_DSP1_IRQ6_CTRL 0x02B80530
#define CS35L41_DSP1_IRQ7_CTRL 0x02B80538
#define CS35L41_DSP1_IRQ8_CTRL 0x02B80540
#define CS35L41_DSP1_IRQ9_CTRL 0x02B80548
#define CS35L41_DSP1_IRQ10_CTRL 0x02B80550
#define CS35L41_DSP1_IRQ11_CTRL 0x02B80558
#define CS35L41_DSP1_IRQ12_CTRL 0x02B80560
#define CS35L41_DSP1_IRQ13_CTRL 0x02B80568
#define CS35L41_DSP1_IRQ14_CTRL 0x02B80570
#define CS35L41_DSP1_IRQ15_CTRL 0x02B80578
#define CS35L41_DSP1_IRQ16_CTRL 0x02B80580
#define CS35L41_DSP1_IRQ17_CTRL 0x02B80588
#define CS35L41_DSP1_IRQ18_CTRL 0x02B80590
#define CS35L41_DSP1_IRQ19_CTRL 0x02B80598
#define CS35L41_DSP1_IRQ20_CTRL 0x02B805A0
#define CS35L41_DSP1_IRQ21_CTRL 0x02B805A8
#define CS35L41_DSP1_IRQ22_CTRL 0x02B805B0
#define CS35L41_DSP1_IRQ23_CTRL 0x02B805B8
#define CS35L41_DSP1_SCRATCH1 0x02B805C0
#define CS35L41_DSP1_SCRATCH2 0x02B805C8
#define CS35L41_DSP1_SCRATCH3 0x02B805D0
#define CS35L41_DSP1_SCRATCH4 0x02B805D8
#define CS35L41_DSP1_CCM_CORE_CTRL 0x02BC1000
#define CS35L41_DSP1_CCM_CLK_OVERRIDE 0x02BC1008
#define CS35L41_DSP1_XM_MSTR_EN 0x02BC2000
#define CS35L41_DSP1_XM_CORE_PRI 0x02BC2008
#define CS35L41_DSP1_XM_AHB_PACK_PL_PRI 0x02BC2010
#define CS35L41_DSP1_XM_AHB_UP_PL_PRI 0x02BC2018
#define CS35L41_DSP1_XM_ACCEL_PL0_PRI 0x02BC2020
#define CS35L41_DSP1_XM_NPL0_PRI 0x02BC2078
#define CS35L41_DSP1_YM_MSTR_EN 0x02BC20C0
#define CS35L41_DSP1_YM_CORE_PRI 0x02BC20C8
#define CS35L41_DSP1_YM_AHB_PACK_PL_PRI 0x02BC20D0
#define CS35L41_DSP1_YM_AHB_UP_PL_PRI 0x02BC20D8
#define CS35L41_DSP1_YM_ACCEL_PL0_PRI 0x02BC20E0
#define CS35L41_DSP1_YM_NPL0_PRI 0x02BC2138
#define CS35L41_DSP1_PM_MSTR_EN 0x02BC2180
#define CS35L41_DSP1_PM_PATCH0_ADDR 0x02BC2188
#define CS35L41_DSP1_PM_PATCH0_EN 0x02BC218C
#define CS35L41_DSP1_PM_PATCH0_DATA_LO 0x02BC2190
#define CS35L41_DSP1_PM_PATCH0_DATA_HI 0x02BC2194
#define CS35L41_DSP1_PM_PATCH1_ADDR 0x02BC2198
#define CS35L41_DSP1_PM_PATCH1_EN 0x02BC219C
#define CS35L41_DSP1_PM_PATCH1_DATA_LO 0x02BC21A0
#define CS35L41_DSP1_PM_PATCH1_DATA_HI 0x02BC21A4
#define CS35L41_DSP1_PM_PATCH2_ADDR 0x02BC21A8
#define CS35L41_DSP1_PM_PATCH2_EN 0x02BC21AC
#define CS35L41_DSP1_PM_PATCH2_DATA_LO 0x02BC21B0
#define CS35L41_DSP1_PM_PATCH2_DATA_HI 0x02BC21B4
#define CS35L41_DSP1_PM_PATCH3_ADDR 0x02BC21B8
#define CS35L41_DSP1_PM_PATCH3_EN 0x02BC21BC
#define CS35L41_DSP1_PM_PATCH3_DATA_LO 0x02BC21C0
#define CS35L41_DSP1_PM_PATCH3_DATA_HI 0x02BC21C4
#define CS35L41_DSP1_PM_PATCH4_ADDR 0x02BC21C8
#define CS35L41_DSP1_PM_PATCH4_EN 0x02BC21CC
#define CS35L41_DSP1_PM_PATCH4_DATA_LO 0x02BC21D0
#define CS35L41_DSP1_PM_PATCH4_DATA_HI 0x02BC21D4
#define CS35L41_DSP1_PM_PATCH5_ADDR 0x02BC21D8
#define CS35L41_DSP1_PM_PATCH5_EN 0x02BC21DC
#define CS35L41_DSP1_PM_PATCH5_DATA_LO 0x02BC21E0
#define CS35L41_DSP1_PM_PATCH5_DATA_HI 0x02BC21E4
#define CS35L41_DSP1_PM_PATCH6_ADDR 0x02BC21E8
#define CS35L41_DSP1_PM_PATCH6_EN 0x02BC21EC
#define CS35L41_DSP1_PM_PATCH6_DATA_LO 0x02BC21F0
#define CS35L41_DSP1_PM_PATCH6_DATA_HI 0x02BC21F4
#define CS35L41_DSP1_PM_PATCH7_ADDR 0x02BC21F8
#define CS35L41_DSP1_PM_PATCH7_EN 0x02BC21FC
#define CS35L41_DSP1_PM_PATCH7_DATA_LO 0x02BC2200
#define CS35L41_DSP1_PM_PATCH7_DATA_HI 0x02BC2204
#define CS35L41_DSP1_MPU_XM_ACCESS0 0x02BC3000
#define CS35L41_DSP1_MPU_YM_ACCESS0 0x02BC3004
#define CS35L41_DSP1_MPU_WNDW_ACCESS0 0x02BC3008
#define CS35L41_DSP1_MPU_XREG_ACCESS0 0x02BC300C
#define CS35L41_DSP1_MPU_YREG_ACCESS0 0x02BC3014
#define CS35L41_DSP1_MPU_XM_ACCESS1 0x02BC3018
#define CS35L41_DSP1_MPU_YM_ACCESS1 0x02BC301C
#define CS35L41_DSP1_MPU_WNDW_ACCESS1 0x02BC3020
#define CS35L41_DSP1_MPU_XREG_ACCESS1 0x02BC3024
#define CS35L41_DSP1_MPU_YREG_ACCESS1 0x02BC302C
#define CS35L41_DSP1_MPU_XM_ACCESS2 0x02BC3030
#define CS35L41_DSP1_MPU_YM_ACCESS2 0x02BC3034
#define CS35L41_DSP1_MPU_WNDW_ACCESS2 0x02BC3038
#define CS35L41_DSP1_MPU_XREG_ACCESS2 0x02BC303C
#define CS35L41_DSP1_MPU_YREG_ACCESS2 0x02BC3044
#define CS35L41_DSP1_MPU_XM_ACCESS3 0x02BC3048
#define CS35L41_DSP1_MPU_YM_ACCESS3 0x02BC304C
#define CS35L41_DSP1_MPU_WNDW_ACCESS3 0x02BC3050
#define CS35L41_DSP1_MPU_XREG_ACCESS3 0x02BC3054
#define CS35L41_DSP1_MPU_YREG_ACCESS3 0x02BC305C
#define CS35L41_DSP1_MPU_XM_VIO_ADDR 0x02BC3100
#define CS35L41_DSP1_MPU_XM_VIO_STATUS 0x02BC3104
#define CS35L41_DSP1_MPU_YM_VIO_ADDR 0x02BC3108
#define CS35L41_DSP1_MPU_YM_VIO_STATUS 0x02BC310C
#define CS35L41_DSP1_MPU_PM_VIO_ADDR 0x02BC3110
#define CS35L41_DSP1_MPU_PM_VIO_STATUS 0x02BC3114
#define CS35L41_DSP1_MPU_LOCK_CONFIG 0x02BC3140
#define CS35L41_DSP1_MPU_WDT_RST_CTRL 0x02BC3180
#define CS35L41_DSP1_STRMARB_MSTR0_CFG0 0x02BC5000
#define CS35L41_DSP1_STRMARB_MSTR0_CFG1 0x02BC5004
#define CS35L41_DSP1_STRMARB_MSTR0_CFG2 0x02BC5008
#define CS35L41_DSP1_STRMARB_MSTR1_CFG0 0x02BC5010
#define CS35L41_DSP1_STRMARB_MSTR1_CFG1 0x02BC5014
#define CS35L41_DSP1_STRMARB_MSTR1_CFG2 0x02BC5018
#define CS35L41_DSP1_STRMARB_MSTR2_CFG0 0x02BC5020
#define CS35L41_DSP1_STRMARB_MSTR2_CFG1 0x02BC5024
#define CS35L41_DSP1_STRMARB_MSTR2_CFG2 0x02BC5028
#define CS35L41_DSP1_STRMARB_MSTR3_CFG0 0x02BC5030
#define CS35L41_DSP1_STRMARB_MSTR3_CFG1 0x02BC5034
#define CS35L41_DSP1_STRMARB_MSTR3_CFG2 0x02BC5038
#define CS35L41_DSP1_STRMARB_MSTR4_CFG0 0x02BC5040
#define CS35L41_DSP1_STRMARB_MSTR4_CFG1 0x02BC5044
#define CS35L41_DSP1_STRMARB_MSTR4_CFG2 0x02BC5048
#define CS35L41_DSP1_STRMARB_MSTR5_CFG0 0x02BC5050
#define CS35L41_DSP1_STRMARB_MSTR5_CFG1 0x02BC5054
#define CS35L41_DSP1_STRMARB_MSTR5_CFG2 0x02BC5058
#define CS35L41_DSP1_STRMARB_MSTR6_CFG0 0x02BC5060
#define CS35L41_DSP1_STRMARB_MSTR6_CFG1 0x02BC5064
#define CS35L41_DSP1_STRMARB_MSTR6_CFG2 0x02BC5068
#define CS35L41_DSP1_STRMARB_MSTR7_CFG0 0x02BC5070
#define CS35L41_DSP1_STRMARB_MSTR7_CFG1 0x02BC5074
#define CS35L41_DSP1_STRMARB_MSTR7_CFG2 0x02BC5078
#define CS35L41_DSP1_STRMARB_TX0_CFG0 0x02BC5200
#define CS35L41_DSP1_STRMARB_TX0_CFG1 0x02BC5204
#define CS35L41_DSP1_STRMARB_TX1_CFG0 0x02BC5208
#define CS35L41_DSP1_STRMARB_TX1_CFG1 0x02BC520C
#define CS35L41_DSP1_STRMARB_TX2_CFG0 0x02BC5210
#define CS35L41_DSP1_STRMARB_TX2_CFG1 0x02BC5214
#define CS35L41_DSP1_STRMARB_TX3_CFG0 0x02BC5218
#define CS35L41_DSP1_STRMARB_TX3_CFG1 0x02BC521C
#define CS35L41_DSP1_STRMARB_TX4_CFG0 0x02BC5220
#define CS35L41_DSP1_STRMARB_TX4_CFG1 0x02BC5224
#define CS35L41_DSP1_STRMARB_TX5_CFG0 0x02BC5228
#define CS35L41_DSP1_STRMARB_TX5_CFG1 0x02BC522C
#define CS35L41_DSP1_STRMARB_TX6_CFG0 0x02BC5230
#define CS35L41_DSP1_STRMARB_TX6_CFG1 0x02BC5234
#define CS35L41_DSP1_STRMARB_TX7_CFG0 0x02BC5238
#define CS35L41_DSP1_STRMARB_TX7_CFG1 0x02BC523C
#define CS35L41_DSP1_STRMARB_RX0_CFG0 0x02BC5400
#define CS35L41_DSP1_STRMARB_RX0_CFG1 0x02BC5404
#define CS35L41_DSP1_STRMARB_RX1_CFG0 0x02BC5408
#define CS35L41_DSP1_STRMARB_RX1_CFG1 0x02BC540C
#define CS35L41_DSP1_STRMARB_RX2_CFG0 0x02BC5410
#define CS35L41_DSP1_STRMARB_RX2_CFG1 0x02BC5414
#define CS35L41_DSP1_STRMARB_RX3_CFG0 0x02BC5418
#define CS35L41_DSP1_STRMARB_RX3_CFG1 0x02BC541C
#define CS35L41_DSP1_STRMARB_RX4_CFG0 0x02BC5420
#define CS35L41_DSP1_STRMARB_RX4_CFG1 0x02BC5424
#define CS35L41_DSP1_STRMARB_RX5_CFG0 0x02BC5428
#define CS35L41_DSP1_STRMARB_RX5_CFG1 0x02BC542C
#define CS35L41_DSP1_STRMARB_RX6_CFG0 0x02BC5430
#define CS35L41_DSP1_STRMARB_RX6_CFG1 0x02BC5434
#define CS35L41_DSP1_STRMARB_RX7_CFG0 0x02BC5438
#define CS35L41_DSP1_STRMARB_RX7_CFG1 0x02BC543C
#define CS35L41_DSP1_STRMARB_IRQ0_CFG0 0x02BC5600
#define CS35L41_DSP1_STRMARB_IRQ0_CFG1 0x02BC5604
#define CS35L41_DSP1_STRMARB_IRQ0_CFG2 0x02BC5608
#define CS35L41_DSP1_STRMARB_IRQ1_CFG0 0x02BC5610
#define CS35L41_DSP1_STRMARB_IRQ1_CFG1 0x02BC5614
#define CS35L41_DSP1_STRMARB_IRQ1_CFG2 0x02BC5618
#define CS35L41_DSP1_STRMARB_IRQ2_CFG0 0x02BC5620
#define CS35L41_DSP1_STRMARB_IRQ2_CFG1 0x02BC5624
#define CS35L41_DSP1_STRMARB_IRQ2_CFG2 0x02BC5628
#define CS35L41_DSP1_STRMARB_IRQ3_CFG0 0x02BC5630
#define CS35L41_DSP1_STRMARB_IRQ3_CFG1 0x02BC5634
#define CS35L41_DSP1_STRMARB_IRQ3_CFG2 0x02BC5638
#define CS35L41_DSP1_STRMARB_IRQ4_CFG0 0x02BC5640
#define CS35L41_DSP1_STRMARB_IRQ4_CFG1 0x02BC5644
#define CS35L41_DSP1_STRMARB_IRQ4_CFG2 0x02BC5648
#define CS35L41_DSP1_STRMARB_IRQ5_CFG0 0x02BC5650
#define CS35L41_DSP1_STRMARB_IRQ5_CFG1 0x02BC5654
#define CS35L41_DSP1_STRMARB_IRQ5_CFG2 0x02BC5658
#define CS35L41_DSP1_STRMARB_IRQ6_CFG0 0x02BC5660
#define CS35L41_DSP1_STRMARB_IRQ6_CFG1 0x02BC5664
#define CS35L41_DSP1_STRMARB_IRQ6_CFG2 0x02BC5668
#define CS35L41_DSP1_STRMARB_IRQ7_CFG0 0x02BC5670
#define CS35L41_DSP1_STRMARB_IRQ7_CFG1 0x02BC5674
#define CS35L41_DSP1_STRMARB_IRQ7_CFG2 0x02BC5678
#define CS35L41_DSP1_STRMARB_RESYNC_MSK 0x02BC5A00
#define CS35L41_DSP1_STRMARB_ERR_STATUS 0x02BC5A08
#define CS35L41_DSP1_INTPCTL_RES_STATIC 0x02BC6000
#define CS35L41_DSP1_INTPCTL_RES_DYN 0x02BC6004
#define CS35L41_DSP1_INTPCTL_NMI_CTRL 0x02BC6008
#define CS35L41_DSP1_INTPCTL_IRQ_INV 0x02BC6010
#define CS35L41_DSP1_INTPCTL_IRQ_MODE 0x02BC6014
#define CS35L41_DSP1_INTPCTL_IRQ_EN 0x02BC6018
#define CS35L41_DSP1_INTPCTL_IRQ_MSK 0x02BC601C
#define CS35L41_DSP1_INTPCTL_IRQ_FLUSH 0x02BC6020
#define CS35L41_DSP1_INTPCTL_IRQ_MSKCLR 0x02BC6024
#define CS35L41_DSP1_INTPCTL_IRQ_FRC 0x02BC6028
#define CS35L41_DSP1_INTPCTL_IRQ_MSKSET 0x02BC602C
#define CS35L41_DSP1_INTPCTL_IRQ_ERR 0x02BC6030
#define CS35L41_DSP1_INTPCTL_IRQ_PEND 0x02BC6034
#define CS35L41_DSP1_INTPCTL_IRQ_GEN 0x02BC6038
#define CS35L41_DSP1_INTPCTL_TESTBITS 0x02BC6040
#define CS35L41_DSP1_WDT_CONTROL 0x02BC7000
#define CS35L41_DSP1_WDT_STATUS 0x02BC7008
#define CS35L41_DSP1_YMEM_PACK_0 0x02C00000
#define CS35L41_DSP1_YMEM_PACK_1532 0x02C017F0
#define CS35L41_DSP1_YMEM_UNPACK32_0 0x03000000
#define CS35L41_DSP1_YMEM_UNPACK32_1022 0x03000FF8
#define CS35L41_DSP1_YMEM_UNPACK24_0 0x03400000
#define CS35L41_DSP1_YMEM_UNPACK24_2045 0x03401FF4
#define CS35L41_DSP1_PMEM_0 0x03800000
#define CS35L41_DSP1_PMEM_5114 0x03804FE8
/*test regs for emulation bringup*/
#define CS35L41_PLL_OVR 0x00003018
#define CS35L41_BST_TEST_DUTY 0x00003900
#define CS35L41_DIGPWM_IOCTRL 0x0000706C
/*registers populated by OTP*/
#define CS35L41_OTP_TRIM_1 0x0000208c
#define CS35L41_OTP_TRIM_2 0x00002090
#define CS35L41_OTP_TRIM_3 0x00003010
#define CS35L41_OTP_TRIM_4 0x0000300C
#define CS35L41_OTP_TRIM_5 0x0000394C
#define CS35L41_OTP_TRIM_6 0x00003950
#define CS35L41_OTP_TRIM_7 0x00003954
#define CS35L41_OTP_TRIM_8 0x00003958
#define CS35L41_OTP_TRIM_9 0x0000395C
#define CS35L41_OTP_TRIM_10 0x0000416C
#define CS35L41_OTP_TRIM_11 0x00004160
#define CS35L41_OTP_TRIM_12 0x00004170
#define CS35L41_OTP_TRIM_13 0x00004360
#define CS35L41_OTP_TRIM_14 0x00004448
#define CS35L41_OTP_TRIM_15 0x0000444C
#define CS35L41_OTP_TRIM_16 0x00006E30
#define CS35L41_OTP_TRIM_17 0x00006E34
#define CS35L41_OTP_TRIM_18 0x00006E38
#define CS35L41_OTP_TRIM_19 0x00006E3C
#define CS35L41_OTP_TRIM_20 0x00006E40
#define CS35L41_OTP_TRIM_21 0x00006E44
#define CS35L41_OTP_TRIM_22 0x00006E48
#define CS35L41_OTP_TRIM_23 0x00006E4C
#define CS35L41_OTP_TRIM_24 0x00006E50
#define CS35L41_OTP_TRIM_25 0x00006E54
#define CS35L41_OTP_TRIM_26 0x00006E58
#define CS35L41_OTP_TRIM_27 0x00006E5C
#define CS35L41_OTP_TRIM_28 0x00006E60
#define CS35L41_OTP_TRIM_29 0x00006E64
#define CS35L41_OTP_TRIM_30 0x00007418
#define CS35L41_OTP_TRIM_31 0x0000741C
#define CS35L41_OTP_TRIM_32 0x00007434
#define CS35L41_OTP_TRIM_33 0x00007068
#define CS35L41_OTP_TRIM_34 0x0000410C
#define CS35L41_OTP_TRIM_35 0x0000400C
#define CS35L41_OTP_TRIM_36 0x00002030
#define CS35L41_MAX_CACHE_REG 36
#define CS35L41_OTP_SIZE_WORDS 32
#define CS35L41_NUM_OTP_ELEM 100
#define CS35L41_VALID_PDATA 0x80000000
#define CS35L41_NUM_SUPPLIES 2
#define CS35L41_SCLK_MSTR_MASK 0x10
#define CS35L41_SCLK_MSTR_SHIFT 4
#define CS35L41_LRCLK_MSTR_MASK 0x01
#define CS35L41_LRCLK_MSTR_SHIFT 0
#define CS35L41_SCLK_INV_MASK 0x40
#define CS35L41_SCLK_INV_SHIFT 6
#define CS35L41_LRCLK_INV_MASK 0x04
#define CS35L41_LRCLK_INV_SHIFT 2
#define CS35L41_SCLK_FRC_MASK 0x20
#define CS35L41_SCLK_FRC_SHIFT 5
#define CS35L41_LRCLK_FRC_MASK 0x02
#define CS35L41_LRCLK_FRC_SHIFT 1
#define CS35L41_AMP_GAIN_PCM_MASK 0x3E0
#define CS35L41_AMP_GAIN_ZC_MASK 0x0400
#define CS35L41_AMP_GAIN_ZC_SHIFT 10
#define CS35L41_BST_CTL_MASK 0xFF
#define CS35L41_BST_CTL_SEL_MASK 0x03
#define CS35L41_BST_CTL_SEL_REG 0x00
#define CS35L41_BST_CTL_SEL_CLASSH 0x01
#define CS35L41_BST_IPK_MASK 0x7F
#define CS35L41_BST_IPK_SHIFT 0
#define CS35L41_BST_LIM_MASK 0x4
#define CS35L41_BST_LIM_SHIFT 2
#define CS35L41_BST_K1_MASK 0x000000FF
#define CS35L41_BST_K1_SHIFT 0
#define CS35L41_BST_K2_MASK 0x0000FF00
#define CS35L41_BST_K2_SHIFT 8
#define CS35L41_BST_SLOPE_MASK 0x0000FF00
#define CS35L41_BST_SLOPE_SHIFT 8
#define CS35L41_BST_LBST_VAL_MASK 0x00000003
#define CS35L41_BST_LBST_VAL_SHIFT 0
#define CS35L41_TEMP_THLD_MASK 0x03
#define CS35L41_VMON_IMON_VOL_MASK 0x07FF07FF
#define CS35L41_PDM_MODE_MASK 0x01
#define CS35L41_PDM_MODE_SHIFT 0
#define CS35L41_CH_MEM_DEPTH_MASK 0x07
#define CS35L41_CH_MEM_DEPTH_SHIFT 0
#define CS35L41_CH_HDRM_CTL_MASK 0x007F0000
#define CS35L41_CH_HDRM_CTL_SHIFT 16
#define CS35L41_CH_REL_RATE_MASK 0xFF00
#define CS35L41_CH_REL_RATE_SHIFT 8
#define CS35L41_CH_WKFET_DLY_MASK 0x001C
#define CS35L41_CH_WKFET_DLY_SHIFT 2
#define CS35L41_CH_WKFET_THLD_MASK 0x0F00
#define CS35L41_CH_WKFET_THLD_SHIFT 8
#define CS35L41_HW_NG_SEL_MASK 0x3F00
#define CS35L41_HW_NG_SEL_SHIFT 8
#define CS35L41_HW_NG_DLY_MASK 0x0070
#define CS35L41_HW_NG_DLY_SHIFT 4
#define CS35L41_HW_NG_THLD_MASK 0x0007
#define CS35L41_HW_NG_THLD_SHIFT 0
#define CS35L41_DSP_NG_ENABLE_MASK 0x00010000
#define CS35L41_DSP_NG_ENABLE_SHIFT 16
#define CS35L41_DSP_NG_THLD_MASK 0x7
#define CS35L41_DSP_NG_THLD_SHIFT 0
#define CS35L41_DSP_NG_DELAY_MASK 0x0F00
#define CS35L41_DSP_NG_DELAY_SHIFT 8
#define CS35L41_ASP_FMT_MASK 0x0700
#define CS35L41_ASP_FMT_SHIFT 8
#define CS35L41_ASP_DOUT_HIZ_MASK 0x03
#define CS35L41_ASP_DOUT_HIZ_SHIFT 0
#define CS35L41_ASP_WIDTH_16 0x10
#define CS35L41_ASP_WIDTH_24 0x18
#define CS35L41_ASP_WIDTH_32 0x20
#define CS35L41_ASP_WIDTH_TX_MASK 0xFF0000
#define CS35L41_ASP_WIDTH_TX_SHIFT 16
#define CS35L41_ASP_WIDTH_RX_MASK 0xFF000000
#define CS35L41_ASP_WIDTH_RX_SHIFT 24
#define CS35L41_ASP_RX1_SLOT_MASK 0x3F
#define CS35L41_ASP_RX1_SLOT_SHIFT 0
#define CS35L41_ASP_RX2_SLOT_MASK 0x3F00
#define CS35L41_ASP_RX2_SLOT_SHIFT 8
#define CS35L41_ASP_RX_WL_MASK 0x3F
#define CS35L41_ASP_TX_WL_MASK 0x3F
#define CS35L41_ASP_RX_WL_SHIFT 0
#define CS35L41_ASP_TX_WL_SHIFT 0
#define CS35L41_ASP_SOURCE_MASK 0x7F
#define CS35L41_INPUT_SRC_ASPRX1 0x08
#define CS35L41_INPUT_SRC_ASPRX2 0x09
#define CS35L41_INPUT_SRC_VMON 0x18
#define CS35L41_INPUT_SRC_IMON 0x19
#define CS35L41_INPUT_SRC_CLASSH 0x21
#define CS35L41_INPUT_SRC_VPMON 0x28
#define CS35L41_INPUT_SRC_VBSTMON 0x29
#define CS35L41_INPUT_SRC_TEMPMON 0x3A
#define CS35L41_INPUT_SRC_RSVD 0x3B
#define CS35L41_INPUT_DSP_TX1 0x32
#define CS35L41_INPUT_DSP_TX2 0x33
#define CS35L41_WR_PEND_STS_MASK 0x2
#define CS35L41_PLL_CLK_SEL_MASK 0x07
#define CS35L41_PLL_CLK_SEL_SHIFT 0
#define CS35L41_PLL_CLK_EN_MASK 0x10
#define CS35L41_PLL_CLK_EN_SHIFT 4
#define CS35L41_PLL_OPENLOOP_MASK 0x0800
#define CS35L41_PLL_OPENLOOP_SHIFT 11
#define CS35L41_PLLSRC_SCLK 0
#define CS35L41_PLLSRC_LRCLK 1
#define CS35L41_PLLSRC_SELF 3
#define CS35L41_PLLSRC_PDMCLK 4
#define CS35L41_PLLSRC_MCLK 5
#define CS35L41_PLLSRC_SWIRE 7
#define CS35L41_REFCLK_FREQ_MASK 0x7E0
#define CS35L41_REFCLK_FREQ_SHIFT 5
#define CS35L41_GLOBAL_FS_MASK 0x1F
#define CS35L41_GLOBAL_FS_SHIFT 0
#define CS35L41_GLOBAL_EN_MASK 0x01
#define CS35L41_GLOBAL_EN_SHIFT 0
#define CS35L41_BST_EN_MASK 0x0030
#define CS35L41_BST_EN_SHIFT 4
#define CS35L41_BST_EN_DEFAULT 0x2
#define CS35L41_AMP_EN_SHIFT 0
#define CS35L41_AMP_EN_MASK 1
#define CS35L41_PDN_DONE_MASK 0x00800000
#define CS35L41_PDN_DONE_SHIFT 23
#define CS35L41_PUP_DONE_MASK 0x01000000
#define CS35L41_PUP_DONE_SHIFT 24
#define CS35L36_PUP_DONE_IRQ_UNMASK 0x5F
#define CS35L36_PUP_DONE_IRQ_MASK 0xBF
#define CS35L41_AMP_SHORT_ERR 0x80000000
#define CS35L41_BST_SHORT_ERR 0x0100
#define CS35L41_TEMP_WARN 0x8000
#define CS35L41_TEMP_ERR 0x00020000
#define CS35L41_BST_OVP_ERR 0x40
#define CS35L41_BST_DCM_UVP_ERR 0x80
#define CS35L41_OTP_BOOT_DONE 0x02
#define CS35L41_PLL_UNLOCK 0x10
#define CS35L41_OTP_BOOT_ERR 0x80000000
#define CS35L41_AMP_SHORT_ERR_RLS 0x02
#define CS35L41_BST_SHORT_ERR_RLS 0x04
#define CS35L41_BST_OVP_ERR_RLS 0x08
#define CS35L41_BST_UVP_ERR_RLS 0x10
#define CS35L41_TEMP_WARN_ERR_RLS 0x20
#define CS35L41_TEMP_ERR_RLS 0x40
#define CS35L41_INT1_MASK_DEFAULT 0x7FFCFE3F
#define CS35L41_INT1_UNMASK_PUP 0xFEFFFFFF
#define CS35L41_INT1_UNMASK_PDN 0xFF7FFFFF
#define CS35L41_GPIO_DIR_MASK 0x80000000
#define CS35L41_GPIO_DIR_SHIFT 31
#define CS35L41_GPIO1_CTRL_MASK 0x00030000
#define CS35L41_GPIO1_CTRL_SHIFT 16
#define CS35L41_GPIO2_CTRL_MASK 0x07000000
#define CS35L41_GPIO2_CTRL_SHIFT 24
#define CS35L41_GPIO_CTRL_OPEN_INT 2
#define CS35L41_GPIO_CTRL_ACTV_LO 4
#define CS35L41_GPIO_CTRL_ACTV_HI 5
#define CS35L41_GPIO_POL_MASK 0x1000
#define CS35L41_GPIO_POL_SHIFT 12
#define CS35L41_AMP_INV_PCM_SHIFT 14
#define CS35L41_AMP_INV_PCM_MASK BIT(CS35L41_AMP_INV_PCM_SHIFT)
#define CS35L41_AMP_PCM_VOL_SHIFT 3
#define CS35L41_AMP_PCM_VOL_MASK (0x7FF << 3)
#define CS35L41_AMP_PCM_VOL_MUTE 0x4CF
#define CS35L41_CHIP_ID 0x35a40
#define CS35L41R_CHIP_ID 0x35b40
#define CS35L41_MTLREVID_MASK 0x0F
#define CS35L41_REVID_A0 0xA0
#define CS35L41_REVID_B0 0xB0
#define CS35L41_REVID_B2 0xB2
#define CS35L41_HALO_CORE_RESET 0x00000200
#define CS35L41_FS1_WINDOW_MASK 0x000007FF
#define CS35L41_FS2_WINDOW_MASK 0x00FFF800
#define CS35L41_FS2_WINDOW_SHIFT 12
#define CS35L41_SPI_MAX_FREQ 4000000
#define CS35L41_REGSTRIDE 4
enum cs35l41_clk_ids {
CS35L41_CLKID_SCLK = 0,
CS35L41_CLKID_LRCLK = 1,
@ -31,4 +750,31 @@ struct cs35l41_platform_data {
struct cs35l41_irq_cfg irq_config2;
};
struct cs35l41_otp_packed_element_t {
u32 reg;
u8 shift;
u8 size;
};
struct cs35l41_otp_map_element_t {
u32 id;
u32 num_elements;
const struct cs35l41_otp_packed_element_t *map;
u32 bit_offset;
u32 word_offset;
};
extern struct regmap_config cs35l41_regmap_i2c;
extern struct regmap_config cs35l41_regmap_spi;
int cs35l41_test_key_unlock(struct device *dev, struct regmap *regmap);
int cs35l41_test_key_lock(struct device *dev, struct regmap *regmap);
int cs35l41_otp_unpack(struct device *dev, struct regmap *regmap);
int cs35l41_register_errata_patch(struct device *dev, struct regmap *reg, unsigned int reg_revid);
int cs35l41_set_channels(struct device *dev, struct regmap *reg,
unsigned int tx_num, unsigned int *tx_slot,
unsigned int rx_num, unsigned int *rx_slot);
int cs35l41_boost_config(struct device *dev, struct regmap *regmap, int boost_ind, int boost_cap,
int boost_ipk);
#endif /* __CS35L41_H */

2
include/sound/dmaengine_pcm.h
View File

@ -60,7 +60,6 @@ struct dma_chan *snd_dmaengine_pcm_get_chan(struct snd_pcm_substream *substream)
* @maxburst: Maximum number of words(note: words, as in units of the
* src_addr_width member, not bytes) that can be send to or received from the
* DAI in one burst.
* @slave_id: Slave requester id for the DMA channel.
* @filter_data: Custom DMA channel filter data, this will usually be used when
* requesting the DMA channel.
* @chan_name: Custom channel name to use when requesting DMA channel.
@ -74,7 +73,6 @@ struct snd_dmaengine_dai_dma_data {
dma_addr_t addr;
enum dma_slave_buswidth addr_width;
u32 maxburst;
unsigned int slave_id;
void *filter_data;
const char *chan_name;
unsigned int fifo_size;

8
include/sound/hda_codec.h
View File

@ -8,7 +8,7 @@
#ifndef __SOUND_HDA_CODEC_H
#define __SOUND_HDA_CODEC_H
#include <linux/kref.h>
#include <linux/refcount.h>
#include <linux/mod_devicetable.h>
#include <sound/info.h>
#include <sound/control.h>
@ -166,8 +166,8 @@ struct hda_pcm {
bool own_chmap; /* codec driver provides own channel maps */
/* private: */
struct hda_codec *codec;
struct kref kref;
struct list_head list;
unsigned int disconnected:1;
};
/* codec information */
@ -187,6 +187,8 @@ struct hda_codec {
/* PCM to create, set by patch_ops.build_pcms callback */
struct list_head pcm_list_head;
refcount_t pcm_ref;
wait_queue_head_t remove_sleep;
/* codec specific info */
void *spec;
@ -420,7 +422,7 @@ void snd_hda_codec_cleanup_for_unbind(struct hda_codec *codec);
static inline void snd_hda_codec_pcm_get(struct hda_pcm *pcm)
{
kref_get(&pcm->kref);
refcount_inc(&pcm->codec->pcm_ref);
}
void snd_hda_codec_pcm_put(struct hda_pcm *pcm);

1
include/sound/hdaudio.h
View File

@ -558,6 +558,7 @@ int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start);
void snd_hdac_stream_clear(struct hdac_stream *azx_dev);
void snd_hdac_stream_stop(struct hdac_stream *azx_dev);
void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus);
void snd_hdac_stream_reset(struct hdac_stream *azx_dev);
void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
unsigned int streams, unsigned int reg);

27
include/sound/hdaudio_ext.h
View File

@ -78,36 +78,35 @@ struct hdac_ext_stream {
container_of(s, struct hdac_ext_stream, hstream)
void snd_hdac_ext_stream_init(struct hdac_bus *bus,
struct hdac_ext_stream *stream, int idx,
int direction, int tag);
struct hdac_ext_stream *hext_stream, int idx,
int direction, int tag);
int snd_hdac_ext_stream_init_all(struct hdac_bus *bus, int start_idx,
int num_stream, int dir);
int num_stream, int dir);
void snd_hdac_stream_free_all(struct hdac_bus *bus);
void snd_hdac_link_free_all(struct hdac_bus *bus);
struct hdac_ext_stream *snd_hdac_ext_stream_assign(struct hdac_bus *bus,
struct snd_pcm_substream *substream,
int type);
void snd_hdac_ext_stream_release(struct hdac_ext_stream *azx_dev, int type);
void snd_hdac_ext_stream_release(struct hdac_ext_stream *hext_stream, int type);
void snd_hdac_ext_stream_decouple_locked(struct hdac_bus *bus,
struct hdac_ext_stream *azx_dev, bool decouple);
struct hdac_ext_stream *hext_stream, bool decouple);
void snd_hdac_ext_stream_decouple(struct hdac_bus *bus,
struct hdac_ext_stream *azx_dev, bool decouple);
void snd_hdac_ext_stop_streams(struct hdac_bus *bus);
int snd_hdac_ext_stream_set_spib(struct hdac_bus *bus,
struct hdac_ext_stream *stream, u32 value);
struct hdac_ext_stream *hext_stream, u32 value);
int snd_hdac_ext_stream_get_spbmaxfifo(struct hdac_bus *bus,
struct hdac_ext_stream *stream);
struct hdac_ext_stream *hext_stream);
void snd_hdac_ext_stream_drsm_enable(struct hdac_bus *bus,
bool enable, int index);
int snd_hdac_ext_stream_set_dpibr(struct hdac_bus *bus,
struct hdac_ext_stream *stream, u32 value);
int snd_hdac_ext_stream_set_lpib(struct hdac_ext_stream *stream, u32 value);
struct hdac_ext_stream *hext_stream, u32 value);
int snd_hdac_ext_stream_set_lpib(struct hdac_ext_stream *hext_stream, u32 value);
void snd_hdac_ext_link_stream_start(struct hdac_ext_stream *hstream);
void snd_hdac_ext_link_stream_clear(struct hdac_ext_stream *hstream);
void snd_hdac_ext_link_stream_reset(struct hdac_ext_stream *hstream);
int snd_hdac_ext_link_stream_setup(struct hdac_ext_stream *stream, int fmt);
void snd_hdac_ext_link_stream_start(struct hdac_ext_stream *hext_stream);
void snd_hdac_ext_link_stream_clear(struct hdac_ext_stream *hext_stream);
void snd_hdac_ext_link_stream_reset(struct hdac_ext_stream *hext_stream);
int snd_hdac_ext_link_stream_setup(struct hdac_ext_stream *hext_stream, int fmt);
struct hdac_ext_link {
struct hdac_bus *bus;

37
include/sound/intel-nhlt.h
View File

@ -10,6 +10,14 @@
#include <linux/acpi.h>
enum nhlt_link_type {
NHLT_LINK_HDA = 0,
NHLT_LINK_DSP = 1,
NHLT_LINK_DMIC = 2,
NHLT_LINK_SSP = 3,
NHLT_LINK_INVALID
};
#if IS_ENABLED(CONFIG_ACPI) && IS_ENABLED(CONFIG_SND_INTEL_NHLT)
struct wav_fmt {
@ -33,14 +41,6 @@ struct wav_fmt_ext {
u8 sub_fmt[16];
} __packed;
enum nhlt_link_type {
NHLT_LINK_HDA = 0,
NHLT_LINK_DSP = 1,
NHLT_LINK_DMIC = 2,
NHLT_LINK_SSP = 3,
NHLT_LINK_INVALID
};
enum nhlt_device_type {
NHLT_DEVICE_BT = 0,
NHLT_DEVICE_DMIC = 1,
@ -132,6 +132,12 @@ void intel_nhlt_free(struct nhlt_acpi_table *addr);
int intel_nhlt_get_dmic_geo(struct device *dev, struct nhlt_acpi_table *nhlt);
bool intel_nhlt_has_endpoint_type(struct nhlt_acpi_table *nhlt, u8 link_type);
struct nhlt_specific_cfg *
intel_nhlt_get_endpoint_blob(struct device *dev, struct nhlt_acpi_table *nhlt,
u32 bus_id, u8 link_type, u8 vbps, u8 bps,
u8 num_ch, u32 rate, u8 dir, u8 dev_type);
#else
struct nhlt_acpi_table;
@ -150,6 +156,21 @@ static inline int intel_nhlt_get_dmic_geo(struct device *dev,
{
return 0;
}
static inline bool intel_nhlt_has_endpoint_type(struct nhlt_acpi_table *nhlt,
u8 link_type)
{
return false;
}
static inline struct nhlt_specific_cfg *
intel_nhlt_get_endpoint_blob(struct device *dev, struct nhlt_acpi_table *nhlt,
u32 bus_id, u8 link_type, u8 vbps, u8 bps,
u8 num_ch, u32 rate, u8 dir, u8 dev_type)
{
return NULL;
}
#endif
#endif

14
include/sound/memalloc.h
View File

@ -36,13 +36,6 @@ struct snd_dma_device {
#define SNDRV_DMA_TYPE_CONTINUOUS 1 /* continuous no-DMA memory */
#define SNDRV_DMA_TYPE_DEV 2 /* generic device continuous */
#define SNDRV_DMA_TYPE_DEV_WC 5 /* continuous write-combined */
#ifdef CONFIG_SND_DMA_SGBUF
#define SNDRV_DMA_TYPE_DEV_SG 3 /* generic device SG-buffer */
#define SNDRV_DMA_TYPE_DEV_WC_SG 6 /* SG write-combined */
#else
#define SNDRV_DMA_TYPE_DEV_SG SNDRV_DMA_TYPE_DEV /* no SG-buf support */
#define SNDRV_DMA_TYPE_DEV_WC_SG SNDRV_DMA_TYPE_DEV_WC
#endif
#ifdef CONFIG_GENERIC_ALLOCATOR
#define SNDRV_DMA_TYPE_DEV_IRAM 4 /* generic device iram-buffer */
#else
@ -51,6 +44,13 @@ struct snd_dma_device {
#define SNDRV_DMA_TYPE_VMALLOC 7 /* vmalloc'ed buffer */
#define SNDRV_DMA_TYPE_NONCONTIG 8 /* non-coherent SG buffer */
#define SNDRV_DMA_TYPE_NONCOHERENT 9 /* non-coherent buffer */
#ifdef CONFIG_SND_DMA_SGBUF
#define SNDRV_DMA_TYPE_DEV_SG SNDRV_DMA_TYPE_NONCONTIG
#define SNDRV_DMA_TYPE_DEV_WC_SG 6 /* SG write-combined */
#else
#define SNDRV_DMA_TYPE_DEV_SG SNDRV_DMA_TYPE_DEV /* no SG-buf support */
#define SNDRV_DMA_TYPE_DEV_WC_SG SNDRV_DMA_TYPE_DEV_WC
#endif
/*
* info for buffer allocation

3
include/sound/pcm.h
View File

@ -147,6 +147,9 @@ struct snd_pcm_ops {
#define SNDRV_PCM_FMTBIT_S24_BE _SNDRV_PCM_FMTBIT(S24_BE)
#define SNDRV_PCM_FMTBIT_U24_LE _SNDRV_PCM_FMTBIT(U24_LE)
#define SNDRV_PCM_FMTBIT_U24_BE _SNDRV_PCM_FMTBIT(U24_BE)
// For S32/U32 formats, 'msbits' hardware parameter is often used to deliver information about the
// available bit count in most significant bit. It's for the case of so-called 'left-justified' or
// `right-padding` sample which has less width than 32 bit.
#define SNDRV_PCM_FMTBIT_S32_LE _SNDRV_PCM_FMTBIT(S32_LE)
#define SNDRV_PCM_FMTBIT_S32_BE _SNDRV_PCM_FMTBIT(S32_BE)
#define SNDRV_PCM_FMTBIT_U32_LE _SNDRV_PCM_FMTBIT(U32_LE)

1
include/sound/rt5682s.h
View File

@ -40,6 +40,7 @@ struct rt5682s_platform_data {
enum rt5682s_jd_src jd_src;
unsigned int dmic_clk_rate;
unsigned int dmic_delay;
unsigned int amic_delay;
bool dmic_clk_driving_high;
const char *dai_clk_names[RT5682S_DAI_NUM_CLKS];

4
include/sound/soc-component.h
View File

@ -148,6 +148,8 @@ struct snd_soc_component_driver {
struct vm_area_struct *vma);
int (*ack)(struct snd_soc_component *component,
struct snd_pcm_substream *substream);
snd_pcm_sframes_t (*delay)(struct snd_soc_component *component,
struct snd_pcm_substream *substream);
const struct snd_compress_ops *compress_ops;
@ -505,5 +507,7 @@ int snd_soc_pcm_component_pm_runtime_get(struct snd_soc_pcm_runtime *rtd,
void snd_soc_pcm_component_pm_runtime_put(struct snd_soc_pcm_runtime *rtd,
void *stream, int rollback);
int snd_soc_pcm_component_ack(struct snd_pcm_substream *substream);
void snd_soc_pcm_component_delay(struct snd_pcm_substream *substream,
snd_pcm_sframes_t *cpu_delay, snd_pcm_sframes_t *codec_delay);
#endif /* __SOC_COMPONENT_H */

36
include/sound/soc-dai.h
View File

@ -208,8 +208,6 @@ int snd_soc_dai_startup(struct snd_soc_dai *dai,
struct snd_pcm_substream *substream);
void snd_soc_dai_shutdown(struct snd_soc_dai *dai,
struct snd_pcm_substream *substream, int rollback);
snd_pcm_sframes_t snd_soc_dai_delay(struct snd_soc_dai *dai,
struct snd_pcm_substream *substream);
void snd_soc_dai_suspend(struct snd_soc_dai *dai);
void snd_soc_dai_resume(struct snd_soc_dai *dai);
int snd_soc_dai_compress_new(struct snd_soc_dai *dai,
@ -238,6 +236,8 @@ int snd_soc_pcm_dai_trigger(struct snd_pcm_substream *substream, int cmd,
int rollback);
int snd_soc_pcm_dai_bespoke_trigger(struct snd_pcm_substream *substream,
int cmd);
void snd_soc_pcm_dai_delay(struct snd_pcm_substream *substream,
snd_pcm_sframes_t *cpu_delay, snd_pcm_sframes_t *codec_delay);
int snd_soc_dai_compr_startup(struct snd_soc_dai *dai,
struct snd_compr_stream *cstream);
@ -295,9 +295,9 @@ struct snd_soc_dai_ops {
unsigned int *rx_num, unsigned int *rx_slot);
int (*set_tristate)(struct snd_soc_dai *dai, int tristate);
int (*set_sdw_stream)(struct snd_soc_dai *dai,
void *stream, int direction);
void *(*get_sdw_stream)(struct snd_soc_dai *dai, int direction);
int (*set_stream)(struct snd_soc_dai *dai,
void *stream, int direction);
void *(*get_stream)(struct snd_soc_dai *dai, int direction);
/*
* DAI digital mute - optional.
@ -515,42 +515,42 @@ static inline void *snd_soc_dai_get_drvdata(struct snd_soc_dai *dai)
}
/**
* snd_soc_dai_set_sdw_stream() - Configures a DAI for SDW stream operation
* snd_soc_dai_set_stream() - Configures a DAI for stream operation
* @dai: DAI
* @stream: STREAM
* @stream: STREAM (opaque structure depending on DAI type)
* @direction: Stream direction(Playback/Capture)
* SoundWire subsystem doesn't have a notion of direction and we reuse
* Some subsystems, such as SoundWire, don't have a notion of direction and we reuse
* the ASoC stream direction to configure sink/source ports.
* Playback maps to source ports and Capture for sink ports.
*
* This should be invoked with NULL to clear the stream set previously.
* Returns 0 on success, a negative error code otherwise.
*/
static inline int snd_soc_dai_set_sdw_stream(struct snd_soc_dai *dai,
void *stream, int direction)
static inline int snd_soc_dai_set_stream(struct snd_soc_dai *dai,
void *stream, int direction)
{
if (dai->driver->ops->set_sdw_stream)
return dai->driver->ops->set_sdw_stream(dai, stream, direction);
if (dai->driver->ops->set_stream)
return dai->driver->ops->set_stream(dai, stream, direction);
else
return -ENOTSUPP;
}
/**
* snd_soc_dai_get_sdw_stream() - Retrieves SDW stream from DAI
* snd_soc_dai_get_stream() - Retrieves stream from DAI
* @dai: DAI
* @direction: Stream direction(Playback/Capture)
*
* This routine only retrieves that was previously configured
* with snd_soc_dai_get_sdw_stream()
* with snd_soc_dai_get_stream()
*
* Returns pointer to stream or an ERR_PTR value, e.g.
* ERR_PTR(-ENOTSUPP) if callback is not supported;
*/
static inline void *snd_soc_dai_get_sdw_stream(struct snd_soc_dai *dai,
int direction)
static inline void *snd_soc_dai_get_stream(struct snd_soc_dai *dai,
int direction)
{
if (dai->driver->ops->get_sdw_stream)
return dai->driver->ops->get_sdw_stream(dai, direction);
if (dai->driver->ops->get_stream)
return dai->driver->ops->get_stream(dai, direction);
else
return ERR_PTR(-ENOTSUPP);
}

2
include/sound/soc-dpcm.h
View File

@ -101,6 +101,8 @@ struct snd_soc_dpcm_runtime {
enum snd_soc_dpcm_state state;
int trigger_pending; /* trigger cmd + 1 if pending, 0 if not */
int be_start; /* refcount protected by BE stream pcm lock */
};
#define for_each_dpcm_fe(be, stream, _dpcm) \

3
include/sound/soc.h
View File

@ -893,8 +893,6 @@ struct snd_soc_card {
struct mutex pcm_mutex;
enum snd_soc_pcm_subclass pcm_subclass;
spinlock_t dpcm_lock;
int (*probe)(struct snd_soc_card *card);
int (*late_probe)(struct snd_soc_card *card);
int (*remove)(struct snd_soc_card *card);
@ -1213,6 +1211,7 @@ int snd_soc_of_parse_card_name(struct snd_soc_card *card,
const char *propname);
int snd_soc_of_parse_audio_simple_widgets(struct snd_soc_card *card,
const char *propname);
int snd_soc_of_parse_pin_switches(struct snd_soc_card *card, const char *prop);
int snd_soc_of_get_slot_mask(struct device_node *np,
const char *prop_name,
unsigned int *mask);

22
include/sound/sof.h
View File

@ -17,6 +17,28 @@
struct snd_sof_dsp_ops;
/**
* enum sof_fw_state - DSP firmware state definitions
* @SOF_FW_BOOT_NOT_STARTED: firmware boot is not yet started
* @SOF_FW_BOOT_PREPARE: preparing for boot (firmware loading for exaqmple)
* @SOF_FW_BOOT_IN_PROGRESS: firmware boot is in progress
* @SOF_FW_BOOT_FAILED: firmware boot failed
* @SOF_FW_BOOT_READY_FAILED: firmware booted but fw_ready op failed
* @SOF_FW_BOOT_READY_OK: firmware booted and fw_ready op passed
* @SOF_FW_BOOT_COMPLETE: firmware is booted up and functional
* @SOF_FW_CRASHED: firmware crashed after successful boot
*/
enum sof_fw_state {
SOF_FW_BOOT_NOT_STARTED = 0,
SOF_FW_BOOT_PREPARE,
SOF_FW_BOOT_IN_PROGRESS,
SOF_FW_BOOT_FAILED,
SOF_FW_BOOT_READY_FAILED,
SOF_FW_BOOT_READY_OK,
SOF_FW_BOOT_COMPLETE,
SOF_FW_CRASHED,
};
/*
* SOF Platform data.
*/

21
include/sound/sof/dai-amd.h Normal file
View File

@ -0,0 +1,21 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* Copyright(c) 2021 Advanced Micro Devices, Inc.. All rights reserved.
*/
#ifndef __INCLUDE_SOUND_SOF_DAI_AMD_H__
#define __INCLUDE_SOUND_SOF_DAI_AMD_H__
#include <sound/sof/header.h>
/* ACP Configuration Request - SOF_IPC_DAI_AMD_CONFIG */
struct sof_ipc_dai_acp_params {
struct sof_ipc_hdr hdr;
uint32_t fsync_rate; /* FSYNC frequency in Hz */
uint32_t tdm_slots;
} __packed;
#endif

23
include/sound/sof/dai-mediatek.h Normal file
View File

@ -0,0 +1,23 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/*
* Copyright(c) 2021 Mediatek Corporation. All rights reserved.
*
* Author: Bo Pan <bo.pan@mediatek.com>
*/
#ifndef __INCLUDE_SOUND_SOF_DAI_MEDIATEK_H__
#define __INCLUDE_SOUND_SOF_DAI_MEDIATEK_H__
#include <sound/sof/header.h>
struct sof_ipc_dai_mtk_afe_params {
struct sof_ipc_hdr hdr;
u32 channels;
u32 rate;
u32 format;
u32 stream_id;
u32 reserved[4]; /* reserve for future */
} __packed;
#endif

35
include/sound/sof/dai.h
View File

@ -12,6 +12,8 @@
#include <sound/sof/header.h>
#include <sound/sof/dai-intel.h>
#include <sound/sof/dai-imx.h>
#include <sound/sof/dai-amd.h>
#include <sound/sof/dai-mediatek.h>
/*
* DAI Configuration.
@ -50,12 +52,25 @@
#define SOF_DAI_FMT_INV_MASK 0x0f00
#define SOF_DAI_FMT_CLOCK_PROVIDER_MASK 0xf000
/* DAI_CONFIG flags */
#define SOF_DAI_CONFIG_FLAGS_MASK 0x3
#define SOF_DAI_CONFIG_FLAGS_NONE (0 << 0) /**< DAI_CONFIG sent without stage information */
#define SOF_DAI_CONFIG_FLAGS_HW_PARAMS (1 << 0) /**< DAI_CONFIG sent during hw_params stage */
#define SOF_DAI_CONFIG_FLAGS_HW_FREE (2 << 0) /**< DAI_CONFIG sent during hw_free stage */
#define SOF_DAI_CONFIG_FLAGS_RFU (3 << 0) /**< not used, reserved for future use */
/*
* DAI_CONFIG flags. The 4 LSB bits are used for the commands, HW_PARAMS, HW_FREE and PAUSE
* representing when the IPC is sent. The 4 MSB bits are used to add quirks along with the above
* commands.
*/
#define SOF_DAI_CONFIG_FLAGS_CMD_MASK 0xF
#define SOF_DAI_CONFIG_FLAGS_NONE 0 /**< DAI_CONFIG sent without stage information */
#define SOF_DAI_CONFIG_FLAGS_HW_PARAMS BIT(0) /**< DAI_CONFIG sent during hw_params stage */
#define SOF_DAI_CONFIG_FLAGS_HW_FREE BIT(1) /**< DAI_CONFIG sent during hw_free stage */
/**< DAI_CONFIG sent during pause trigger. Only available ABI 3.20 onwards */
#define SOF_DAI_CONFIG_FLAGS_PAUSE BIT(2)
#define SOF_DAI_CONFIG_FLAGS_QUIRK_SHIFT 4
#define SOF_DAI_CONFIG_FLAGS_QUIRK_MASK (0xF << SOF_DAI_CONFIG_FLAGS_QUIRK_SHIFT)
/*
* This should be used along with the SOF_DAI_CONFIG_FLAGS_HW_PARAMS to indicate that pipeline
* stop/pause and DAI DMA stop/pause should happen in two steps. This change is only available
* ABI 3.20 onwards.
*/
#define SOF_DAI_CONFIG_FLAGS_2_STEP_STOP BIT(0)
/** \brief Types of DAI */
enum sof_ipc_dai_type {
@ -66,6 +81,10 @@ enum sof_ipc_dai_type {
SOF_DAI_INTEL_ALH, /**< Intel ALH */
SOF_DAI_IMX_SAI, /**< i.MX SAI */
SOF_DAI_IMX_ESAI, /**< i.MX ESAI */
SOF_DAI_AMD_BT, /**< AMD ACP BT*/
SOF_DAI_AMD_SP, /**< AMD ACP SP */
SOF_DAI_AMD_DMIC, /**< AMD ACP DMIC */
SOF_DAI_MEDIATEK_AFE, /**< Mediatek AFE */
};
/* general purpose DAI configuration */
@ -90,6 +109,10 @@ struct sof_ipc_dai_config {
struct sof_ipc_dai_alh_params alh;
struct sof_ipc_dai_esai_params esai;
struct sof_ipc_dai_sai_params sai;
struct sof_ipc_dai_acp_params acpbt;
struct sof_ipc_dai_acp_params acpsp;
struct sof_ipc_dai_acp_params acpdmic;
struct sof_ipc_dai_mtk_afe_params afe;
};
} __packed;

2
include/sound/sof/debug.h
View File

@ -19,6 +19,8 @@ enum sof_ipc_dbg_mem_zone {
SOF_IPC_MEM_ZONE_SYS_RUNTIME = 1, /**< System-runtime zone */
SOF_IPC_MEM_ZONE_RUNTIME = 2, /**< Runtime zone */
SOF_IPC_MEM_ZONE_BUFFER = 3, /**< Buffer zone */
SOF_IPC_MEM_ZONE_RUNTIME_SHARED = 4, /**< System runtime zone */
SOF_IPC_MEM_ZONE_SYS_SHARED = 5, /**< System shared zone */
};
/** ABI3.18 */

1
include/sound/sof/header.h
View File

@ -119,6 +119,7 @@
#define SOF_IPC_TRACE_DMA_POSITION SOF_CMD_TYPE(0x002)
#define SOF_IPC_TRACE_DMA_PARAMS_EXT SOF_CMD_TYPE(0x003)
#define SOF_IPC_TRACE_FILTER_UPDATE SOF_CMD_TYPE(0x004) /**< ABI3.17 */
#define SOF_IPC_TRACE_DMA_FREE SOF_CMD_TYPE(0x005) /**< ABI3.20 */
/* debug */
#define SOF_IPC_DEBUG_MEM_USAGE SOF_CMD_TYPE(0x001)

7
include/uapi/sound/asound.h
View File

@ -202,6 +202,11 @@ typedef int __bitwise snd_pcm_format_t;
#define SNDRV_PCM_FORMAT_S24_BE ((__force snd_pcm_format_t) 7) /* low three bytes */
#define SNDRV_PCM_FORMAT_U24_LE ((__force snd_pcm_format_t) 8) /* low three bytes */
#define SNDRV_PCM_FORMAT_U24_BE ((__force snd_pcm_format_t) 9) /* low three bytes */
/*
* For S32/U32 formats, 'msbits' hardware parameter is often used to deliver information about the
* available bit count in most significant bit. It's for the case of so-called 'left-justified' or
* `right-padding` sample which has less width than 32 bit.
*/
#define SNDRV_PCM_FORMAT_S32_LE ((__force snd_pcm_format_t) 10)
#define SNDRV_PCM_FORMAT_S32_BE ((__force snd_pcm_format_t) 11)
#define SNDRV_PCM_FORMAT_U32_LE ((__force snd_pcm_format_t) 12)
@ -300,7 +305,7 @@ typedef int __bitwise snd_pcm_subformat_t;
#define SNDRV_PCM_INFO_HAS_LINK_ESTIMATED_ATIME 0x04000000 /* report estimated link audio time */
#define SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 0x08000000 /* report synchronized audio/system time */
#define SNDRV_PCM_INFO_EXPLICIT_SYNC 0x10000000 /* needs explicit sync of pointers and data */
#define SNDRV_PCM_INFO_NO_REWINDS 0x20000000 /* hardware can only support monotonic changes of appl_ptr */
#define SNDRV_PCM_INFO_DRAIN_TRIGGER 0x40000000 /* internal kernel flag - trigger in drain */
#define SNDRV_PCM_INFO_FIFO_IN_FRAMES 0x80000000 /* internal kernel flag - FIFO size is in frames */

5
include/uapi/sound/sof/tokens.h
View File

@ -140,4 +140,9 @@
#define SOF_TKN_INTEL_HDA_RATE 1500
#define SOF_TKN_INTEL_HDA_CH 1501
/* AFE */
#define SOF_TKN_MEDIATEK_AFE_RATE 1600
#define SOF_TKN_MEDIATEK_AFE_CH 1601
#define SOF_TKN_MEDIATEK_AFE_FORMAT 1602
#endif

1
sound/core/Makefile
View File

@ -19,7 +19,6 @@ snd-$(CONFIG_SND_JACK) += ctljack.o jack.o
snd-pcm-y := pcm.o pcm_native.o pcm_lib.o pcm_misc.o \
pcm_memory.o memalloc.o
snd-pcm-$(CONFIG_SND_PCM_TIMER) += pcm_timer.o
snd-pcm-$(CONFIG_SND_DMA_SGBUF) += sgbuf.o
snd-pcm-$(CONFIG_SND_PCM_ELD) += pcm_drm_eld.o
snd-pcm-$(CONFIG_SND_PCM_IEC958) += pcm_iec958.o

2
sound/core/control_led.c
View File

@ -509,7 +509,7 @@ static char *parse_string(char *s, char *val, size_t val_size)
return s;
}
static char *parse_iface(char *s, unsigned int *val)
static char *parse_iface(char *s, snd_ctl_elem_iface_t *val)
{
if (!strncasecmp(s, "card", 4))
*val = SNDRV_CTL_ELEM_IFACE_CARD;

6
sound/core/info_oss.c
View File

@ -32,10 +32,8 @@ int snd_oss_info_register(int dev, int num, char *string)
mutex_lock(&strings);
if (string == NULL) {
x = snd_sndstat_strings[num][dev];
if (x) {
kfree(x);
x = NULL;
}
kfree(x);
x = NULL;
} else {
x = kstrdup(string, GFP_KERNEL);
if (x == NULL) {

3
sound/core/jack.c
View File

@ -62,10 +62,13 @@ static int snd_jack_dev_free(struct snd_device *device)
struct snd_card *card = device->card;
struct snd_jack_kctl *jack_kctl, *tmp_jack_kctl;
down_write(&card->controls_rwsem);
list_for_each_entry_safe(jack_kctl, tmp_jack_kctl, &jack->kctl_list, list) {
list_del_init(&jack_kctl->list);
snd_ctl_remove(card, jack_kctl->kctl);
}
up_write(&card->controls_rwsem);
if (jack->private_free)
jack->private_free(jack);

53
sound/core/memalloc.c
View File

@ -620,6 +620,52 @@ static const struct snd_malloc_ops snd_dma_noncontig_ops = {
.get_chunk_size = snd_dma_noncontig_get_chunk_size,
};
/* x86-specific SG-buffer with WC pages */
#ifdef CONFIG_SND_DMA_SGBUF
#define sg_wc_address(it) ((unsigned long)page_address(sg_page_iter_page(it)))
static void *snd_dma_sg_wc_alloc(struct snd_dma_buffer *dmab, size_t size)
{
void *p = snd_dma_noncontig_alloc(dmab, size);
struct sg_table *sgt = dmab->private_data;
struct sg_page_iter iter;
if (!p)
return NULL;
for_each_sgtable_page(sgt, &iter, 0)
set_memory_wc(sg_wc_address(&iter), 1);
return p;
}
static void snd_dma_sg_wc_free(struct snd_dma_buffer *dmab)
{
struct sg_table *sgt = dmab->private_data;
struct sg_page_iter iter;
for_each_sgtable_page(sgt, &iter, 0)
set_memory_wb(sg_wc_address(&iter), 1);
snd_dma_noncontig_free(dmab);
}
static int snd_dma_sg_wc_mmap(struct snd_dma_buffer *dmab,
struct vm_area_struct *area)
{
area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
return dma_mmap_noncontiguous(dmab->dev.dev, area,
dmab->bytes, dmab->private_data);
}
static const struct snd_malloc_ops snd_dma_sg_wc_ops = {
.alloc = snd_dma_sg_wc_alloc,
.free = snd_dma_sg_wc_free,
.mmap = snd_dma_sg_wc_mmap,
.sync = snd_dma_noncontig_sync,
.get_addr = snd_dma_noncontig_get_addr,
.get_page = snd_dma_noncontig_get_page,
.get_chunk_size = snd_dma_noncontig_get_chunk_size,
};
#endif /* CONFIG_SND_DMA_SGBUF */
/*
* Non-coherent pages allocator
*/
@ -679,14 +725,13 @@ static const struct snd_malloc_ops *dma_ops[] = {
[SNDRV_DMA_TYPE_DEV_WC] = &snd_dma_wc_ops,
[SNDRV_DMA_TYPE_NONCONTIG] = &snd_dma_noncontig_ops,
[SNDRV_DMA_TYPE_NONCOHERENT] = &snd_dma_noncoherent_ops,
#ifdef CONFIG_SND_DMA_SGBUF
[SNDRV_DMA_TYPE_DEV_WC_SG] = &snd_dma_sg_wc_ops,
#endif
#ifdef CONFIG_GENERIC_ALLOCATOR
[SNDRV_DMA_TYPE_DEV_IRAM] = &snd_dma_iram_ops,
#endif /* CONFIG_GENERIC_ALLOCATOR */
#endif /* CONFIG_HAS_DMA */
#ifdef CONFIG_SND_DMA_SGBUF
[SNDRV_DMA_TYPE_DEV_SG] = &snd_dma_sg_ops,
[SNDRV_DMA_TYPE_DEV_WC_SG] = &snd_dma_sg_ops,
#endif
};
static const struct snd_malloc_ops *snd_dma_get_ops(struct snd_dma_buffer *dmab)

2
sound/core/oss/pcm_oss.c
View File

@ -2065,7 +2065,7 @@ static int snd_pcm_oss_set_trigger(struct snd_pcm_oss_file *pcm_oss_file, int tr
int err, cmd;
#ifdef OSS_DEBUG
pcm_dbg(substream->pcm, "pcm_oss: trigger = 0x%x\n", trigger);
pr_debug("pcm_oss: trigger = 0x%x\n", trigger);
#endif
psubstream = pcm_oss_file->streams[SNDRV_PCM_STREAM_PLAYBACK];

6
sound/core/pcm.c
View File

@ -810,7 +810,11 @@ EXPORT_SYMBOL(snd_pcm_new_internal);
static void free_chmap(struct snd_pcm_str *pstr)
{
if (pstr->chmap_kctl) {
snd_ctl_remove(pstr->pcm->card, pstr->chmap_kctl);
struct snd_card *card = pstr->pcm->card;
down_write(&card->controls_rwsem);
snd_ctl_remove(card, pstr->chmap_kctl);
up_write(&card->controls_rwsem);
pstr->chmap_kctl = NULL;
}
}

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