The i.MX clock updates for 4.7, take 2:

- Update clk-pllv3 driver to get it return correct frequency for
    Ethernet PLL on i.MX7D.
  - Correct ahb clock mux settings for i.MX7D per latest hardware
    document.
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Merge tag 'imx-clk-4.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next

Pull i.MX clk updates from Shawn Guo:

 - Update clk-pllv3 driver to get it return correct frequency for
   Ethernet PLL on i.MX7D.
 - Correct ahb clock mux settings for i.MX7D per latest hardware
   document.

* tag 'imx-clk-4.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  clk: imx7d: fix ahb clock mux 1
  clk: imx: return correct frequency for Ethernet PLL
This commit is contained in:
Stephen Boyd 2016-05-06 11:02:35 -07:00
commit 3cdaeb7d8b
2 changed files with 9 additions and 2 deletions

View File

@ -56,7 +56,7 @@ static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
"pll_sys_pfd2_135m_clk", "pll_sys_pfd6_clk", "pll_enet_250m_clk",
"pll_audio_main_clk", };
static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
"pll_dram_533m_clk", "pll_sys_pfd0_392m_clk",
"pll_enet_125m_clk", "pll_usb_main_clk", "pll_audio_main_clk",
"pll_video_main_clk", };

View File

@ -44,6 +44,7 @@ struct clk_pllv3 {
u32 powerdown;
u32 div_mask;
u32 div_shift;
unsigned long ref_clock;
};
#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
@ -286,7 +287,9 @@ static const struct clk_ops clk_pllv3_av_ops = {
static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
return 500000000;
struct clk_pllv3 *pll = to_clk_pllv3(hw);
return pll->ref_clock;
}
static const struct clk_ops clk_pllv3_enet_ops = {
@ -326,7 +329,11 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
break;
case IMX_PLLV3_ENET_IMX7:
pll->powerdown = IMX7_ENET_PLL_POWER;
pll->ref_clock = 1000000000;
ops = &clk_pllv3_enet_ops;
break;
case IMX_PLLV3_ENET:
pll->ref_clock = 500000000;
ops = &clk_pllv3_enet_ops;
break;
default: