clk: sunxi: rewrite sun6i-ar100 using factors clk
sun6i's AR100 clock is a classic factors clk case: AR100 = ((parent mux) >> p) / (m + 1) Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Chen-Yu Tsai
Maxime Ripard
parent
a78bb35552
commit
3ca2377b6f
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@ -8,211 +8,97 @@
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*
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*/
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#include <linux/bitops.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#define SUN6I_AR100_MAX_PARENTS 4
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#define SUN6I_AR100_SHIFT_MASK 0x3
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#define SUN6I_AR100_SHIFT_MAX SUN6I_AR100_SHIFT_MASK
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#define SUN6I_AR100_SHIFT_SHIFT 4
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#define SUN6I_AR100_DIV_MASK 0x1f
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#define SUN6I_AR100_DIV_MAX (SUN6I_AR100_DIV_MASK + 1)
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#define SUN6I_AR100_DIV_SHIFT 8
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#define SUN6I_AR100_MUX_MASK 0x3
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#define SUN6I_AR100_MUX_SHIFT 16
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#include "clk-factors.h"
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struct ar100_clk {
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struct clk_hw hw;
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void __iomem *reg;
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};
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static inline struct ar100_clk *to_ar100_clk(struct clk_hw *hw)
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/**
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* sun6i_get_ar100_factors - Calculates factors p, m for AR100
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*
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* AR100 rate is calculated as follows
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* rate = (parent_rate >> p) / (m + 1);
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*/
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static void sun6i_get_ar100_factors(struct factors_request *req)
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{
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return container_of(hw, struct ar100_clk, hw);
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}
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static unsigned long ar100_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct ar100_clk *clk = to_ar100_clk(hw);
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u32 val = readl(clk->reg);
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int shift = (val >> SUN6I_AR100_SHIFT_SHIFT) & SUN6I_AR100_SHIFT_MASK;
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int div = (val >> SUN6I_AR100_DIV_SHIFT) & SUN6I_AR100_DIV_MASK;
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return (parent_rate >> shift) / (div + 1);
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}
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static int ar100_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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int nparents = clk_hw_get_num_parents(hw);
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long best_rate = -EINVAL;
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int i;
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req->best_parent_hw = NULL;
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for (i = 0; i < nparents; i++) {
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unsigned long parent_rate;
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unsigned long tmp_rate;
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struct clk_hw *parent;
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unsigned long div;
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int shift;
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parent = clk_hw_get_parent_by_index(hw, i);
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parent_rate = clk_hw_get_rate(parent);
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div = DIV_ROUND_UP(parent_rate, req->rate);
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/*
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* The AR100 clk contains 2 divisors:
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* - one power of 2 divisor
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* - one regular divisor
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*
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* First check if we can safely shift (or divide by a power
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* of 2) without losing precision on the requested rate.
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*/
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shift = ffs(div) - 1;
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if (shift > SUN6I_AR100_SHIFT_MAX)
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shift = SUN6I_AR100_SHIFT_MAX;
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div >>= shift;
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/*
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* Then if the divisor is still bigger than what the HW
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* actually supports, use a bigger shift (or power of 2
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* divider) value and accept to lose some precision.
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*/
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while (div > SUN6I_AR100_DIV_MAX) {
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shift++;
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div >>= 1;
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if (shift > SUN6I_AR100_SHIFT_MAX)
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break;
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}
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/*
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* If the shift value (or power of 2 divider) is bigger
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* than what the HW actually support, skip this parent.
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*/
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if (shift > SUN6I_AR100_SHIFT_MAX)
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continue;
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tmp_rate = (parent_rate >> shift) / div;
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if (!req->best_parent_hw || tmp_rate > best_rate) {
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req->best_parent_hw = parent;
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req->best_parent_rate = parent_rate;
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best_rate = tmp_rate;
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}
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}
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if (best_rate < 0)
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return best_rate;
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req->rate = best_rate;
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return 0;
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}
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static int ar100_set_parent(struct clk_hw *hw, u8 index)
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{
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struct ar100_clk *clk = to_ar100_clk(hw);
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u32 val = readl(clk->reg);
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if (index >= SUN6I_AR100_MAX_PARENTS)
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return -EINVAL;
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val &= ~(SUN6I_AR100_MUX_MASK << SUN6I_AR100_MUX_SHIFT);
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val |= (index << SUN6I_AR100_MUX_SHIFT);
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writel(val, clk->reg);
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return 0;
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}
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static u8 ar100_get_parent(struct clk_hw *hw)
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{
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struct ar100_clk *clk = to_ar100_clk(hw);
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return (readl(clk->reg) >> SUN6I_AR100_MUX_SHIFT) &
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SUN6I_AR100_MUX_MASK;
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}
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static int ar100_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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unsigned long div = parent_rate / rate;
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struct ar100_clk *clk = to_ar100_clk(hw);
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u32 val = readl(clk->reg);
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unsigned long div;
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int shift;
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if (parent_rate % rate)
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return -EINVAL;
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/* clock only divides */
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if (req->rate > req->parent_rate)
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req->rate = req->parent_rate;
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shift = ffs(div) - 1;
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if (shift > SUN6I_AR100_SHIFT_MAX)
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shift = SUN6I_AR100_SHIFT_MAX;
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div = DIV_ROUND_UP(req->parent_rate, req->rate);
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if (div < 32)
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shift = 0;
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else if (div >> 1 < 32)
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shift = 1;
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else if (div >> 2 < 32)
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shift = 2;
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else
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shift = 3;
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div >>= shift;
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if (div > SUN6I_AR100_DIV_MAX)
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return -EINVAL;
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if (div > 32)
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div = 32;
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val &= ~((SUN6I_AR100_SHIFT_MASK << SUN6I_AR100_SHIFT_SHIFT) |
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(SUN6I_AR100_DIV_MASK << SUN6I_AR100_DIV_SHIFT));
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val |= (shift << SUN6I_AR100_SHIFT_SHIFT) |
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(div << SUN6I_AR100_DIV_SHIFT);
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writel(val, clk->reg);
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req->rate = (req->parent_rate >> shift) / div;
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req->m = div - 1;
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req->p = shift;
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}
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static const struct clk_factors_config sun6i_ar100_config = {
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.mwidth = 5,
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.mshift = 8,
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.pwidth = 2,
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.pshift = 4,
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};
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static const struct factors_data sun6i_ar100_data __initconst = {
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.mux = 16,
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.muxmask = GENMASK(1, 0),
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.table = &sun6i_ar100_config,
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.getter = sun6i_get_ar100_factors,
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};
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static DEFINE_SPINLOCK(sun6i_ar100_lock);
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static int sun6i_a31_ar100_clk_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct resource *r;
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void __iomem *reg;
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struct clk *clk;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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reg = devm_ioremap_resource(&pdev->dev, r);
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if (IS_ERR(reg))
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return PTR_ERR(reg);
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clk = sunxi_factors_register(np, &sun6i_ar100_data, &sun6i_ar100_lock,
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reg);
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if (!clk)
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return -ENOMEM;
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platform_set_drvdata(pdev, clk);
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return 0;
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}
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static struct clk_ops ar100_ops = {
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.recalc_rate = ar100_recalc_rate,
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.determine_rate = ar100_determine_rate,
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.set_parent = ar100_set_parent,
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.get_parent = ar100_get_parent,
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.set_rate = ar100_set_rate,
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};
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static int sun6i_a31_ar100_clk_probe(struct platform_device *pdev)
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static int sun6i_a31_ar100_clk_remove(struct platform_device *pdev)
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{
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const char *parents[SUN6I_AR100_MAX_PARENTS];
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struct device_node *np = pdev->dev.of_node;
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const char *clk_name = np->name;
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struct clk_init_data init;
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struct ar100_clk *ar100;
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struct resource *r;
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struct clk *clk;
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int nparents;
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struct clk *clk = platform_get_drvdata(pdev);
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ar100 = devm_kzalloc(&pdev->dev, sizeof(*ar100), GFP_KERNEL);
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if (!ar100)
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return -ENOMEM;
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sunxi_factors_unregister(np, clk);
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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ar100->reg = devm_ioremap_resource(&pdev->dev, r);
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if (IS_ERR(ar100->reg))
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return PTR_ERR(ar100->reg);
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nparents = of_clk_get_parent_count(np);
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if (nparents > SUN6I_AR100_MAX_PARENTS)
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nparents = SUN6I_AR100_MAX_PARENTS;
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of_clk_parent_fill(np, parents, nparents);
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of_property_read_string(np, "clock-output-names", &clk_name);
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init.name = clk_name;
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init.ops = &ar100_ops;
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init.parent_names = parents;
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init.num_parents = nparents;
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init.flags = 0;
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ar100->hw.init = &init;
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clk = clk_register(&pdev->dev, &ar100->hw);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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return of_clk_add_provider(np, of_clk_src_simple_get, clk);
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return 0;
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}
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static const struct of_device_id sun6i_a31_ar100_clk_dt_ids[] = {
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@ -227,6 +113,7 @@ static struct platform_driver sun6i_a31_ar100_clk_driver = {
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.of_match_table = sun6i_a31_ar100_clk_dt_ids,
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},
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.probe = sun6i_a31_ar100_clk_probe,
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.remove = sun6i_a31_ar100_clk_remove,
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};
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module_platform_driver(sun6i_a31_ar100_clk_driver);
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