hollalinux
/
linux-sg2042
mirror of https://github.com/sophgo/linux-riscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

ARM: EXYNOS: Remove legacy timer initialization code 

This patch removes legacy timer initialization code that was used to
set up system timers when booting with ATAGS, which is not supported
on Exynos any more.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Tomasz Figa 2013-06-15 09:04:58 +09:00 committed by Kukjin Kim
parent d243997f12
commit 3c70348c7c
1 changed files with 2 additions and 37 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

39
arch/arm/mach-exynos/common.c
View File

@ -299,13 +299,6 @@ static struct map_desc exynos5440_iodesc0[] __initdata = {
},
};
static struct samsung_pwm_variant exynos4_pwm_variant = {
.bits = 32,
.div_base = 0,
.has_tint_cstat = true,
.tclk_mask = 0,
};
void exynos4_restart(char mode, const char *cmd)
{
__raw_writel(0x1, S5P_SWRESET);
@ -451,38 +444,10 @@ static void __init exynos5440_map_io(void)
iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
}
void __init exynos_set_timer_source(u8 channels)
{
exynos4_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
exynos4_pwm_variant.output_mask &= ~channels;
}
void __init exynos_init_time(void)
{
unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
EXYNOS4_IRQ_TIMER0_VIC, EXYNOS4_IRQ_TIMER1_VIC,
EXYNOS4_IRQ_TIMER2_VIC, EXYNOS4_IRQ_TIMER3_VIC,
EXYNOS4_IRQ_TIMER4_VIC,
};
if (of_have_populated_dt()) {
of_clk_init(NULL);
clocksource_of_init();
} else {
/* todo: remove after migrating legacy E4 platforms to dt */
#ifdef CONFIG_ARCH_EXYNOS4
exynos4_clk_init(NULL, !soc_is_exynos4210(), S5P_VA_CMU, readl(S5P_VA_CHIPID + 8) & 1);
exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
#endif
#ifdef CONFIG_CLKSRC_SAMSUNG_PWM
if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
samsung_pwm_clocksource_init(S3C_VA_TIMER,
timer_irqs, &exynos4_pwm_variant);
else
#endif
mct_init(S5P_VA_SYSTIMER, EXYNOS4_IRQ_MCT_G0,
EXYNOS4_IRQ_MCT_L0, EXYNOS4_IRQ_MCT_L1);
}
of_clk_init(NULL);
clocksource_of_init();
}
void __init exynos4_init_irq(void)